CN112086367A - TO-220 packaged MOSFET with Clip structure and manufacturing method thereof - Google Patents
TO-220 packaged MOSFET with Clip structure and manufacturing method thereof Download PDFInfo
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- CN112086367A CN112086367A CN202011035819.3A CN202011035819A CN112086367A CN 112086367 A CN112086367 A CN 112086367A CN 202011035819 A CN202011035819 A CN 202011035819A CN 112086367 A CN112086367 A CN 112086367A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 238000003466 welding Methods 0.000 claims abstract description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052802 copper Inorganic materials 0.000 claims abstract description 19
- 239000010949 copper Substances 0.000 claims abstract description 19
- 238000004140 cleaning Methods 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 9
- 238000005520 cutting process Methods 0.000 claims abstract description 8
- 238000005476 soldering Methods 0.000 claims abstract description 8
- 238000004806 packaging method and process Methods 0.000 claims abstract description 5
- 238000012545 processing Methods 0.000 claims abstract description 5
- 239000013078 crystal Substances 0.000 claims abstract description 4
- 238000001035 drying Methods 0.000 claims abstract description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 13
- 239000000956 alloy Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 11
- 238000005245 sintering Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000012360 testing method Methods 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 238000000465 moulding Methods 0.000 claims description 3
- 238000007667 floating Methods 0.000 abstract description 6
- 229910000679 solder Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910002796 Si–Al Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention relates TO the technical field of power devices, in particular TO a TO-220 packaged MOSFET with a Clip structure and a manufacturing method thereof, aiming at solving the problems that the packaging is easy TO generate phenomena such as floating of a connecting line, fracture of a welding spot and the like in the prior art, and the technical key points are as follows: the manufacturing method of the TO-220 packaged MOSFET with the Clip structure comprises the following steps of S5: carrying out blue film pasting, cutting, cleaning and drying processes on the wafer substrate which is subjected TO the chip processing flow TO form a chip, adsorbing and placing the bare chip subjected TO the cutting process on a TO-220 lead frame with soldering paste, and then curing a welding material; s6: and (3) dotting the soldering paste on the grid electrode and source electrode areas on the crystal grains, adsorbing the copper Clip, placing the copper Clip on the corresponding positions of the grid electrode and the source electrode, and putting the copper Clip into a high-temperature welding furnace to bond the metal on the surface of the chip and the welding material. According TO the TO-220 packaged MOSFET with the Clip structure and the manufacturing method thereof, the problems of floating of connecting wires and breakage of welding spots are reduced, and meanwhile, the reliability of products is improved.
Description
Technical Field
The invention relates TO the technical field of power devices, in particular TO a TO-220 packaged MOSFET with a Clip structure and a manufacturing method thereof.
Background
A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has the advantages of high input impedance, low driving power, high switching speed, flat aluminum, good characteristics, high thermal stability and the like, and is a Field-Effect Transistor which can be widely used in analog circuits and digital electric fields.
The development process of power MOSFETs is based on the preservation and exploitation of the characteristics of the MOS period itself, and attempts are made to increase the power, i.e. to increase the operating voltage and current of the device, which greatly limits the increase of the breakdown voltage of the power MOS and also limits its general application in high voltage systems.
At present, the packaging of the MOSFET mostly uses a Wire bond connection mode, the phenomena of Wire floating, welding spot fracture and the like are easily generated, the reliability of a product is also influenced, and open-circuit failure is easily presented in a high-low temperature cycle test.
Disclosure of Invention
Therefore, the technical problem TO be solved by the invention is TO overcome the defects that floating and solder joint fracture are easily generated in the prior art, and the invention provides a manufacturing method of the TO-220 packaged MOSFET with the Clip structure.
The technical purpose of the invention is realized by the following technical scheme:
a manufacturing method of a TO-220 packaged MOSFET with a Clip structure comprises the following steps:
s1: selecting a wafer substrate, cleaning the surface of the wafer substrate to remove surface impurities, and then forming a metal layer on the surface of the wafer substrate;
s2: opening a window to be etched on the surface of the wafer substrate, etching the metal layer on the surface of the wafer substrate, and then performing metal sintering to form an alloy layer on the surface of the wafer substrate;
s3: carrying out secondary cleaning on the wafer substrate with the formed alloy layer to remove surface pollution, and forming the alloy layer on the surface of the wafer substrate again;
s4: opening a region to be etched, performing metal etching, forming a grid electrode and a source electrode on the surface of a wafer substrate, and forming a drain electrode on the back of the wafer substrate, so as to form a complete metal oxide semiconductor unit region;
s5: carrying out blue film pasting, cutting, cleaning and drying processes on the wafer substrate which is subjected TO the chip processing flow TO form a chip, adsorbing and placing the bare chip subjected TO the cutting process on a TO-220 lead frame with soldering paste, and then curing a welding material;
s6: dotting soldering paste on a grid electrode area and a source electrode area on the crystal grain, adsorbing copper Clip, placing the copper Clip on the corresponding positions of the grid electrode area and the source electrode area, and placing the copper Clip in a high-temperature welding furnace to effectively bond the metal on the surface of the chip and a welding material;
s7: and (5) packaging the plastic shell, and assembling the sample through high-temperature baking, electroplating, molding and testing processes.
In some embodiments of the present application, the wafer substrate is a wafer substrate after the contact hole is etched by using a mask.
In some embodiments of the present application, in S1, the wafer substrate surface is cleaned by 5% hydrofluoric acid, and a metal layer is formed on the wafer substrate surface through an evaporation process.
In some embodiments of the present application, the temperature of the metal sintering in S2 is 400 ℃, and a protective gas is introduced during the metal sintering process.
The application also provides a TO-220 packaged MOSFET with a Clip structure and a manufacturing method of the TO-220 packaged MOSFET with the Clip structure.
The manufacturing method of the TO-220 packaged MOSFET with the Clip structure provided by the application reduces the problems of floating of connecting wires and breakage of welding spots, and improves the reliability of products.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic internal cross-sectional view of a TO-220 packaged MOSFET with a Clip structure according TO an embodiment of the present invention;
fig. 2 is another angle internal cross-sectional view of a TO-220 packaged MOSFET with a Clip structure according TO an embodiment of the present invention.
Description of reference numerals:
1 an outer housing; 2. a frame; 3. a pin; 31. a copper Clip; 4. a chip; 41. solder paste
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
A method for manufacturing a TO-220 packaged MOSFET with a Clip structure comprises the following steps,
s1: selecting a wafer substrate, cleaning the surface of the wafer substrate to remove surface impurities, and then forming a metal layer on the surface of the wafer substrate.
Specifically, the wafer substrate is obtained by etching the contact hole by using a mask, and the surface of the wafer substrate is not metallized. In an embodiment, the wafer substrate surface is cleaned by using 5% hydrofluoric acid. And forming a metal layer on the surface of the wafer substrate through an evaporation process, wherein the metal layer is an aluminum layer, and the thickness of the metal layer is 20 KA.
S2: and opening a window to be etched on the surface of the wafer substrate, etching the metal layer on the surface of the wafer substrate, and then performing metal sintering to form an alloy layer on the surface of the wafer substrate.
Specifically, in the implementation, the window to be etched on the surface of the wafer substrate is opened by applying chip processing technologies such as glue coating, exposure, development and the like. And the temperature of the metal sintering is 400 ℃, and a protective gas needs to be introduced during the metal sintering process, wherein in an embodiment, the protective gas is N2+ H2. And the alloy layer formed on the surface of the wafer substrate is Si-Al alloy.
S3: and carrying out secondary cleaning on the wafer substrate with the formed alloy layer to remove surface pollution, and forming the alloy layer on the surface of the wafer substrate again.
Specifically, in the embodiment, the reformed alloy layer is a TiNiAg alloy with a thickness of 25 KA.
S4: and opening the area to be etched, performing metal etching, forming a grid electrode and a source electrode on the surface of the wafer substrate, and forming a drain electrode on the back of the wafer substrate, thereby forming a complete metal oxide semiconductor unit area.
S5: carrying out blue film pasting, cutting, cleaning and drying processes on the wafer substrate which is subjected TO the chip processing flow TO form a chip, adsorbing and placing the bare chip subjected TO the cutting process on a TO-220 lead frame with soldering paste, and then curing the welding material.
S6: and (3) dotting the soldering paste on the grid electrode and source electrode areas on the crystal grains, adsorbing the copper Clip, placing the copper Clip on the corresponding positions of the grid electrode and the source electrode, and placing the copper Clip into a high-temperature welding furnace to effectively bond the metal on the surface of the chip and the welding material.
Specifically, in the embodiment, the peak value of the furnace temperature in the high-temperature welding furnace is 355 ℃, and the furnace temperature is maintained for 2 minutes, so that the metal on the surface of the chip can be well adhered to the welding material, and the tension of the copper Clip, the grid electrode and the source end is correspondingly increased. In other embodiments, the peak temperature in the high-temperature welding furnace may be 355 ℃ to 375 ℃, and specifically, the peak temperature in the high-temperature welding furnace may be any one of 360 ℃, 363 ℃, 365 ℃, 368 ℃, 370 ℃, 373 ℃, and 375 ℃.
S7: and (5) packaging the plastic shell, and assembling the sample through high-temperature baking, electroplating, molding and testing processes.
The application also provides a TO-220 packaged MOSFET with a Clip structure, which is manufactured by the manufacturing method of the TO-220 packaged MOSFET with the Clip structure. Referring TO fig. 1 and 2, the TO-220 packaged MOSFET with the Clip structure includes an outer casing 1, a frame 2 and an inner chip 4, wherein two lead frames 3 are disposed on one side surface of the frame 2, a copper Clip31 is disposed between the lead frames 3 and the frame 2, one end of the copper Clip31 is bonded TO the leads 3, and the other end of the copper Clip extends toward the frame 2 and is connected TO the chip 4.
Referring to fig. 2, a chip 4 is bonded to the frame 2, the copper Clip31, the chip 4 and the frame 2 are bonded by solder paste 41 on two sides of the chip 4, and the copper Clip31 is fixed on the leads 3 by the solder paste 41.
According TO the manufacturing method of the TO-220 packaged MOSFET with the Clip structure, the problems of floating of connecting wires and breakage of welding spots are reduced, and meanwhile, the reliability of products is improved.
It is to be understood that the above embodiments are merely examples for clarity of description and are not to be construed as limiting the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (5)
1. A manufacturing method of a TO-220 packaged MOSFET with a Clip structure is characterized in that: comprises the following steps:
s1: selecting a wafer substrate, cleaning the surface of the wafer substrate to remove surface impurities, and then forming a metal layer on the surface of the wafer substrate;
s2: opening a window to be etched on the surface of the wafer substrate, etching the metal layer on the surface of the wafer substrate, and then performing metal sintering to form an alloy layer on the surface of the wafer substrate;
s3: carrying out secondary cleaning on the wafer substrate with the formed alloy layer to remove surface pollution, and forming the alloy layer on the surface of the wafer substrate again;
s4: opening a region to be etched, performing metal etching, forming a grid electrode and a source electrode on the surface of a wafer substrate, and forming a drain electrode on the back of the wafer substrate, so as to form a complete metal oxide semiconductor unit region;
s5: carrying out blue film pasting, cutting, cleaning and drying processes on the wafer substrate which is subjected TO the chip processing flow TO form a chip, adsorbing and placing the bare chip subjected TO the cutting process on a TO-220 lead frame with soldering paste, and then curing a welding material;
s6: dotting soldering paste on a grid electrode area and a source electrode area on the crystal grain, adsorbing copper Clip, placing the copper Clip on the corresponding positions of the grid electrode area and the source electrode area, and placing the copper Clip in a high-temperature welding furnace to effectively bond the metal on the surface of the chip and a welding material;
s7: and (5) packaging the plastic shell, and assembling the sample through high-temperature baking, electroplating, molding and testing processes.
2. A manufacturing method of a TO-220 packaged MOSFET with a Clip structure is characterized in that: the wafer substrate is formed by etching the contact hole by using a mask.
3. A manufacturing method of a TO-220 packaged MOSFET with a Clip structure is characterized in that: and in the step S1, cleaning the surface of the wafer substrate by 5% hydrofluoric acid, and forming a metal layer on the surface of the wafer substrate by an evaporation process.
4. A manufacturing method of a TO-220 packaged MOSFET with a Clip structure is characterized in that: the sintering temperature of the metal in the S2 is 400 ℃, and protective gas is introduced in the metal sintering process.
5. A TO-220 packaged MOSFET with a Clip structure is characterized in that: a method of manufacturing a MOSFET packaged using the Clip-structured TO-220 according TO any one of claims 1 TO 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011035819.3A CN112086367A (en) | 2020-09-27 | 2020-09-27 | TO-220 packaged MOSFET with Clip structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011035819.3A CN112086367A (en) | 2020-09-27 | 2020-09-27 | TO-220 packaged MOSFET with Clip structure and manufacturing method thereof |
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| CN112086367A true CN112086367A (en) | 2020-12-15 |
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| CN202011035819.3A Pending CN112086367A (en) | 2020-09-27 | 2020-09-27 | TO-220 packaged MOSFET with Clip structure and manufacturing method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101339955A (en) * | 2008-06-16 | 2009-01-07 | 启东市捷捷微电子有限公司 | Gate sensitive triggering unidirectional controlled silicon chip and production method thereof |
| CN102270657A (en) * | 2010-06-07 | 2011-12-07 | 三菱电机株式会社 | Semiconductor device |
| CN103918062A (en) * | 2011-12-12 | 2014-07-09 | 住友电气工业株式会社 | Method for manufacturing semiconductor device |
| CN110246823A (en) * | 2018-03-09 | 2019-09-17 | 英飞凌科技股份有限公司 | Semiconductor devices comprising bonding pad and combination wire or clip |
-
2020
- 2020-09-27 CN CN202011035819.3A patent/CN112086367A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101339955A (en) * | 2008-06-16 | 2009-01-07 | 启东市捷捷微电子有限公司 | Gate sensitive triggering unidirectional controlled silicon chip and production method thereof |
| CN102270657A (en) * | 2010-06-07 | 2011-12-07 | 三菱电机株式会社 | Semiconductor device |
| CN103918062A (en) * | 2011-12-12 | 2014-07-09 | 住友电气工业株式会社 | Method for manufacturing semiconductor device |
| CN110246823A (en) * | 2018-03-09 | 2019-09-17 | 英飞凌科技股份有限公司 | Semiconductor devices comprising bonding pad and combination wire or clip |
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