CN112071842A - Three-dimensional storage structure of non-volatile ferroelectric memory - Google Patents
Three-dimensional storage structure of non-volatile ferroelectric memory Download PDFInfo
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- CN112071842A CN112071842A CN201910442483.3A CN201910442483A CN112071842A CN 112071842 A CN112071842 A CN 112071842A CN 201910442483 A CN201910442483 A CN 201910442483A CN 112071842 A CN112071842 A CN 112071842A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/223—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using MOS with ferroelectric gate insulating film
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B51/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
Abstract
The invention discloses a three-dimensional storage structure of a non-volatile ferroelectric memory, which comprises a substrate layer, a plurality of ferroelectric thin film memory layer wafers arranged on the substrate layer and a metal interconnection layer arranged on the plurality of ferroelectric thin film memory layer wafers, wherein the ferroelectric thin film memory layer wafers are connected up and down through hole electrodes, high-density ferroelectric memory units are arranged on the ferroelectric thin film memory layer wafers, and the substrate layer can control the ferroelectric memory units on each layer; the method solves the problems that the conventional method for improving the capacity of the memory is smaller through a memory unit and semiconductor manufacturing equipment needs to be comprehensively updated, so that the production and construction cost of the whole integrated circuit is high. The method has the advantages that the semiconductor process node of the integrated circuit production line is not changed, and only the structure of the memory device is changed, so that the multiplied data information capacity is improved, the structure is simple, convenience and practicability are realized, and the method can be widely applied to next generation of high-density non-volatile ferroelectric memory chips.
Description
Technical Field
The invention relates to the technical field of microelectronic memories, in particular to a three-dimensional storage structure of a non-volatile ferroelectric memory.
Background
The ferroelectric memory uses ferroelectric material electric domain to keep positive and negative polarization direction state to store nonvolatile memory information (1 and 0). In recent years, with the discovery of the domain wall conduction physical mechanism of the electric domain of the ferroelectric material, the nonvolatile ferroelectric memory based on the domain wall conduction physical mechanism can greatly improve the storage capacity of the ferroelectric memory. The fundamental principle is that large writing voltage is utilized to realize domain inversion of ferroelectric materials in the storage unit, and a conductive domain wall channel with an interface shape is formed with a non-inverted domain of the ferroelectric materials on the substrate around the storage unit, so that the resistance value of the storage unit is changed, and further, 1bit information storage of one storage unit is realized. Traditionally, smaller feature size units have been used to increase storage density capacity, but according to moore's law, semiconductor fabrication techniques now using smaller feature sizes are becoming increasingly difficult as physical limits are approached, and the investment in foundry lines is rapidly rising. How to maintain the current situation of the existing manufacturing nodes and keep the high density of the memory to be continuously developed is becoming the direction of the whole industry nowadays.
Disclosure of Invention
In view of the above-mentioned shortcomings, the present invention provides a three-dimensional storage structure of a non-volatile ferroelectric memory, which is modified in the structure of a storage device, i.e. the improvement of data information capacity by times is realized, the structure is simple, and the structure is convenient and practical.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
the structure of the three-dimensional storage of the nonvolatile ferroelectric memory comprises a substrate layer, a plurality of layers of ferroelectric thin film memory layer wafers arranged on the substrate layer and a metal interconnection layer arranged on the plurality of layers of ferroelectric thin film memory layer wafers, wherein the ferroelectric thin film memory layer wafers are connected up and down through hole electrodes, high-density ferroelectric memory units are arranged on the ferroelectric thin film memory layer wafers, and the substrate layer can control the ferroelectric memory units.
In accordance with one aspect of the invention, the substrate layer is a silicon-based read circuit.
According to one aspect of the invention, the number of layers of the multilayer ferroelectric thin film memory layer wafer is at least 2.
According to one aspect of the invention, the number of layers of the multilayer ferroelectric thin film memory layer wafer is greater than or equal to 2 and less than or equal to 200.
According to one aspect of the invention, the ferroelectric thin film of the ferroelectric thin film memory layer wafer is selected from ion-doped modified ferroelectric crystal thin film materials. The ferroelectric thin film of the ferroelectric thin film storage layer wafer is selected from ion-doped modified ferroelectric crystal thin film materials such as bismuth ferrite, lithium niobate, lithium tantalate, lead zirconate titanate, strontium bismuth tantalate and the like.
According to one aspect of the invention, the base layer, the multilayer ferroelectric thin film memory layer wafer and the metal interconnection layer are stacked using a bonding process. The bonding process can be bonding technologies such as ultrahigh vacuum bonding, surface activation bonding in a vacuum environment, room temperature bonding in an atmospheric environment, fluorine-containing plasma activation room temperature bonding technology and the like.
In accordance with one aspect of the invention, the bonding process is performed at a temperature of no more than 500 degrees.
The implementation of the invention has the advantages that: the three-dimensional storage structure of the non-volatile ferroelectric memory comprises a base layer, a plurality of ferroelectric thin film memory layer wafers arranged on the base layer and a metal interconnection layer arranged on the plurality of ferroelectric thin film memory layer wafers, wherein the ferroelectric thin film memory layer wafers are connected up and down through hole electrodes, high-density ferroelectric memory units are arranged on the ferroelectric thin film memory layer wafers, and the base layer can control the ferroelectric memory units on each layer; stacking a ferroelectric thin film memory layer wafer by adopting a wafer bonding process, and realizing multilayer signal control by interconnecting through hole electrodes penetrating through the wafer in a three-dimensional structure, thereby realizing interconnection of more units in the same chip area and improving the capacity of a single chip; the method solves the problems that the conventional method for improving the capacity of the memory is smaller through a memory unit and semiconductor manufacturing equipment needs to be comprehensively updated, so that the production and construction cost of the whole integrated circuit is high. The method has the advantages that the semiconductor process node of the integrated circuit production line is not changed, and only the structure of the memory device is changed, so that the multiplied data information capacity is improved, the structure is simple, convenience and practicability are realized, and the method can be widely applied to next generation of high-density non-volatile ferroelectric memory chips.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a three-dimensional memory of a nonvolatile ferroelectric memory according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, a three-dimensional storage structure of a non-volatile ferroelectric memory comprises a substrate layer 100, a plurality of ferroelectric thin film memory layer wafers 11 disposed on the substrate layer, and a metal interconnection layer 120 disposed on the plurality of ferroelectric thin film memory layer wafers, wherein the plurality of ferroelectric thin film memory layer wafers are connected up and down through via electrodes, wherein high-density ferroelectric memory cells are arranged on the plurality of ferroelectric thin film memory layer wafers, and the substrate layer can control the plurality of ferroelectric memory cells. In practical application, the number n of the multilayer ferroelectric thin film memory layer wafer is at least 2. The substrate layer (100) is a silicon-based reading circuit, and a first ferroelectric thin film memory layer wafer (11) (1) is bonded on the substrate layer (100) through an ultrahigh vacuum bonding process at the temperature of 200 ℃. The semiconductor process flow adopting the 0.13um process node comprises the working procedures of photoetching, etching, film deposition, chemical mechanical polishing, metal interconnection and the like, the manufacture of the storage unit of the first ferroelectric film storage layer wafer (11) (1) is completed, and the storage unit is connected with the circuit control pad point metal of the substrate layer (100). The above steps are repeated to complete n ferroelectric memory layer wafers (11 (n)). And finally, completing the reading and writing of the metal interconnection layer of the chip storage unit by adopting a semiconductor metal interconnection process.
In practical application, the substrate layer is a silicon-based reading circuit.
In practical application, the number n of the multilayer ferroelectric thin film memory layer wafer is more than or equal to 2 and less than or equal to 200.
In practical application, the ferroelectric thin film of the ferroelectric thin film memory layer wafer is selected from ion doping modified ferroelectric crystal thin film materials. The ferroelectric thin film of the ferroelectric thin film storage layer wafer is selected from ion-doped modified ferroelectric crystal thin film materials such as bismuth ferrite, lithium niobate, lithium tantalate, lead zirconate titanate, strontium bismuth tantalate and the like.
In practical application, the substrate layer, the multilayer ferroelectric thin film memory layer wafer and the metal interconnection layer are stacked by adopting a bonding process. The bonding process can be bonding technologies such as ultrahigh vacuum bonding, surface activation bonding in a vacuum environment, room temperature bonding in an atmospheric environment, fluorine-containing plasma activation room temperature bonding technology and the like.
In practical application, the bonding process adopts the temperature not higher than 500 ℃.
The implementation of the invention has the advantages that: the three-dimensional storage structure of the non-volatile ferroelectric memory comprises a base layer, a plurality of ferroelectric thin film memory layer wafers arranged on the base layer and a metal interconnection layer arranged on the plurality of ferroelectric thin film memory layer wafers, wherein the ferroelectric thin film memory layer wafers are connected up and down through hole electrodes, high-density ferroelectric memory units are arranged on the ferroelectric thin film memory layer wafers, and the base layer can control the ferroelectric memory units on each layer; stacking a ferroelectric thin film memory layer wafer by adopting a wafer bonding process, and realizing multilayer signal control by interconnecting through hole electrodes penetrating through the wafer in a three-dimensional structure, thereby realizing interconnection of more units in the same chip area and improving the capacity of a single chip; the method solves the problems that the conventional method for improving the capacity of the memory is smaller through a memory unit and semiconductor manufacturing equipment needs to be comprehensively updated, so that the production and construction cost of the whole integrated circuit is high. The method has the advantages that the semiconductor process node of the integrated circuit production line is not changed, and only the structure of the memory device is changed, so that the multiplied data information capacity is improved, the structure is simple, convenience and practicability are realized, and the method can be widely applied to next generation of high-density non-volatile ferroelectric memory chips.
The above description is only an embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention disclosed herein are intended to be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (7)
1. The structure for the three-dimensional storage of the nonvolatile ferroelectric memory is characterized by comprising a base layer, a plurality of ferroelectric thin film memory layer wafers arranged on the base layer and a metal interconnection layer arranged on the plurality of ferroelectric thin film memory layer wafers, wherein the ferroelectric thin film memory layer wafers are connected up and down through hole electrodes, high-density ferroelectric memory units are arranged on the ferroelectric thin film memory layer wafers, and the base layer can control the ferroelectric memory units.
2. The structure for three-dimensional storage of a non-volatile ferroelectric memory as claimed in claim 1, wherein the substrate layer is a silicon-based read circuit.
3. The structure for three-dimensional storage of a nonvolatile ferroelectric memory according to claim 1, wherein the number of layers of the multilayer ferroelectric thin film memory layer wafer is at least 2.
4. The structure of the three-dimensional memory of the nonvolatile ferroelectric memory as claimed in claim 3, wherein the number of the layers of the multilayer ferroelectric thin film memory layer wafer is 2 or more and 200 or less.
5. The structure for three-dimensional storage of a nonvolatile ferroelectric memory as claimed in claim 1, wherein the ferroelectric thin film of the ferroelectric thin film memory layer wafer is selected from ion-doped modified ferroelectric crystal thin film materials.
6. The structure of the three-dimensional memory of the nonvolatile ferroelectric memory as in one of claims 1 to 5, wherein the substrate layer, the multilayer ferroelectric thin film memory layer wafer and the metal interconnection layer are stacked by a bonding process.
7. The structure of the three-dimensional memory of the nonvolatile ferroelectric memory as claimed in claim 6, wherein the temperature used in the bonding process is not higher than 500 degrees.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201910442483.3A CN112071842A (en) | 2019-05-25 | 2019-05-25 | Three-dimensional storage structure of non-volatile ferroelectric memory |
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| CN201910442483.3A CN112071842A (en) | 2019-05-25 | 2019-05-25 | Three-dimensional storage structure of non-volatile ferroelectric memory |
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| CN112071842A true CN112071842A (en) | 2020-12-11 |
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