WO2022067587A1

WO2022067587A1 - Three-dimensional memory and manufacturing method therefor, and electronic device

Info

Publication number: WO2022067587A1
Application number: PCT/CN2020/119098
Authority: WO
Inventors: 江安全; 杨喜超; 张岩; 江钧; 柴晓杰; 魏侠; 秦健鹰
Original assignee: 华为技术有限公司; 复旦大学
Priority date: 2020-09-29
Filing date: 2020-09-29
Publication date: 2022-04-07
Also published as: CN116076163A; CN116076163A8

Abstract

A three-dimensional memory and a manufacturing method therefor, and an electronic device. The three-dimensional memory comprises a first chip and a second chip that are interconnected. The first chip comprises a stacked three-dimensional storage array and first bonding layer, and a plurality of first surface electrodes in the first bonding layer are correspondingly coupled to the three-dimensional storage array. The second chip comprises a stacked read-write circuit and second bonding layer, and a plurality of second surface electrodes in the second bonding layer are correspondingly coupled to the read-write circuit. The interconnection of the first chip and the second chip is realized by the bonding of the first bonding layer and the second bonding layer. In addition, the first surface electrodes in the first bonding layer and the second surface electrodes in the second bonding layer are coupled in a one-to-one correspondence.

Description

Three-dimensional memory, preparation method thereof, and electronic device

technical field

The present application relates to the field of storage technology, and in particular, to a three-dimensional memory, a preparation method thereof, and an electronic device.

Background technique

With the development of communication technology and digital technology, people's demand for digital storage capacity is increasing. The use of three-dimensional storage technology to improve the storage density of the memory has become one of the important development trends in the field of storage technology.

At present, the preparation technology of two-dimensional memory has become mature. Taking the two-dimensional ferroelectric memory as an example, the preparation method is as follows. First, the read and write logic circuit transistors are prepared, and then a ferroelectric thin film is prepared on the top of the read and write logic circuit transistors, so that a plurality of ferroelectric memory cell patterns located on the same plane can be prepared on the surface of the ferroelectric thin film. Since the distance between the surface of the ferroelectric memory cell facing away from the read-write circuit and the surface of the read-write circuit close to the ferroelectric film is small, for example, its size unit is nanoscale, a plurality of via holes are formed in the ferroelectric film, And by preparing metal lines in each via hole, the metal lines can be used to realize the corresponding coupling between the ferroelectric memory cell array and the read-write logic circuit transistors.

However, it is difficult to directly apply the above two-dimensional memory preparation method to a three-dimensional memory. For example, in a three-dimensional memory, the stacking of multiple layers of memory cells is not conducive to forming vias from the side of the memory cell away from the read-write circuit to the surface of the read-write circuit; that is, from the side of the memory cell away from the read-write circuit It is difficult to prepare vias penetrating the surface of the read-write circuit, and problems such as metal wire breakage caused by the small diameter and large hole depth of the vias are prone to occur, which easily affects the reliability of the three-dimensional memory.

SUMMARY OF THE INVENTION

Embodiments of the present disclosure provide a three-dimensional memory, a preparation method thereof, and an electronic device, which are used to solve the problem of reliable coupling between a three-dimensional memory array and a read-write circuit in a three-dimensional memory, and are beneficial to improve the reliability of use of the three-dimensional memory.

In one aspect, some embodiments of the present disclosure provide a three-dimensional memory. The three-dimensional memory includes: a first chip and a second chip. The first chip includes a three-dimensional memory array and a first bonding layer. The second chip includes a read-write circuit and a second bonding layer. The first bonding layer is located on the side of the three-dimensional storage array close to the read-write circuit; the first bonding layer includes a plurality of first surface electrodes correspondingly coupled to the three-dimensional storage array. The second bonding layer is located on the side of the read-write circuit close to the three-dimensional memory array; the second bonding layer includes a plurality of second surface electrodes correspondingly coupled to the read-write circuit. The plurality of first surface electrodes and the plurality of second surface electrodes are coupled in one-to-one correspondence.

In some embodiments of the present disclosure, the three-dimensional storage array and the read-write circuit in the three-dimensional memory are prepared in different chips, for example, the three-dimensional storage array is prepared in the first chip, and the read-write circuit is prepared in the second chip. In this way, the manufacturing process flow of the three-dimensional memory array and the read-write circuit can be carried out separately.

In the preparation process of the first chip, after the stacking of the multi-layer memory cells in the three-dimensional memory array is completed, the signal lines corresponding to each layer of the memory cells can be led out to the surface of the three-dimensional memory array along with the preparation of the memory cells. In this way, the first bonding layer is formed on the prepared surface of the three-dimensional storage array, that is, the surface of the three-dimensional storage array close to the read-write circuit, so that the first surface electrode in the first bonding layer can be connected to the surface of the three-dimensional storage array. The corresponding signal lines are directly coupled.

Similarly, in the preparation process of the second chip, after the preparation of the read-write circuit is completed, a plurality of input/output terminals of the read-write circuit can be located on the surface thereof. In this way, the second bonding layer is formed on the prepared surface of the read-write circuit, that is, the surface of the read-write circuit close to the three-dimensional memory array, so that the second surface electrode in the second bonding layer can be connected with the read-write circuit. The corresponding input/output terminals are directly coupled.

On this basis, the first bonding layer in the first chip and the second bonding layer in the second chip are bonded, so that the first surface electrode in the first bonding layer and the By directly coupling the second surface electrodes, it is possible to simply and directly realize the corresponding coupling between the three-dimensional storage array and the read-write circuit in the three-dimensional memory, that is, the alignment and buckle between the three-dimensional storage array and the read-write circuit can be realized. way of coupling. In this way, the three-dimensional storage array is prepared on the surface of the read-write circuit, and via holes are formed from the surface of the three-dimensional storage array away from the read-write circuit to the read-write circuit, so as to realize the connection between the signal line in the three-dimensional storage array and the input/output end of the read-write circuit. Compared with coupling, the embodiment of the present disclosure adopts the direct bonding method of the first chip and the second chip, and the preparation process is relatively simple. surface vias. In this way, there will be no problems such as difficulty in preparing vias due to the avoidance of the positions between the vias and signal lines in the three-dimensional memory array, and metal wire breakage due to the small aperture and large hole depth of the vias. . In addition, the first surface electrode in the first chip and the second surface electrode in the second chip are in contact and coupling, which is beneficial to ensure reliable coupling between the three-dimensional memory array and the read-write circuit. Therefore, it is beneficial to improve the reliability of the coupling between the three-dimensional memory array and the read-write circuit, thereby improving the use reliability of the three-dimensional memory.

In addition, since the manufacturing process of the first chip and the second chip can be performed separately, the first chip and the second chip can be manufactured simultaneously, thereby effectively shortening the production cycle of the three-dimensional memory. In addition, the preparation of the three-dimensional memory array in the first chip is performed on its independent production line, which can avoid adverse effects of other production materials on the production line, such as the problem of cross-contamination of production materials caused by shared production lines.

In some embodiments, the first bonding layer further includes a first dielectric layer having a plurality of first vias. The plurality of first surface electrodes are located in the plurality of first via holes in a one-to-one correspondence, and the surfaces of the plurality of first surface electrodes and the first dielectric layer close to the second bonding layer are located on the same plane. The second bonding layer also includes a second dielectric layer having a plurality of second vias. The plurality of second surface electrodes are located in the plurality of second via holes in a one-to-one correspondence, and the surfaces of the plurality of second surface electrodes and the second dielectric layer close to the first bonding layer are located on the same plane.

In the embodiment of the present disclosure, the first surface electrode is disposed in the first via hole of the first dielectric layer, and the second surface electrode is disposed in the second via hole of the second dielectric layer, and the first dielectric layer can be used. The presence of the layer and the second dielectric layer improves the quality of the bonding surface between the first bonding layer and the second bonding layer, for example ensuring that the bonding surface between the first bonding layer and the second bonding layer is relatively flat or smooth. In this way, after the first dielectric layer is formed on the surface of the three-dimensional memory array, the position and size of the first surface electrode can be accurately defined by using the first via hole therein. After the second dielectric layer is formed on the surface of the read-write circuit, the position and size of the second surface electrode can be accurately defined by using the second via hole therein. Therefore, it is ensured that the first surface electrode and the three-dimensional storage array, the first surface electrode and the second surface electrode, and the second surface electrode and the read-write circuit can be aligned and coupled, and have good coupling performance, which can further improve Use reliability of three-dimensional memory. In addition, the bonding mode of the first bonding layer and the second bonding layer is hybrid bonding, which can achieve both good bonding strength and electrical conductivity.

In some embodiments, the material of at least one of the first dielectric layer and the second dielectric layer includes monocrystalline silicon, silicon oxide, silicon nitride, benzocyclobutene, lithium tantalate, or lithium niobate.

In some embodiments, the first chip further includes a first substrate. In this way, the three-dimensional memory array in the first chip can be disposed on the first substrate. In this case, the first bonding layer is located on the surface of the three-dimensional memory array facing away from the first substrate.

Optionally, the material of the first substrate includes: ferroelectric single crystal material or single crystal silicon. The ferroelectric single crystal material includes lithium tantalate, lithium niobate, lithium tantalate, lithium niobate, blackened lithium tantalate or lithium niobate, or doping selected from magnesium oxide, two oxide pentoxide Lithium tantalate or lithium niobate of at least one of manganese, iron oxide or lanthanum oxide.

In some embodiments, the second chip further includes a second substrate. In this way, the read-write circuit can be arranged on the second substrate. In this case, the second bonding layer is located on the surface of the read-write circuit facing away from the second substrate.

In some embodiments, the material of at least one of the plurality of first surface electrodes and the plurality of second surface electrodes includes: iridium, platinum, tungsten, nickel, cobalt, copper, aluminum, polysilicon, a silicon-doped metal, or At least one of metal silicides. In this way, at least one of the first surface electrode and the second surface electrode is formed by using a material with good electrical conductivity, which can ensure that the first surface electrode and the second surface electrode have good electrical connection after bonding.

In some embodiments, a three-dimensional memory array includes: a plurality of bit lines, a plurality of word lines, and a plurality of memory cells distributed in an array in a three-dimensional space. One end of each memory cell is coupled to a word line, and the other end of the word line is coupled to a first surface electrode. The other end of each memory cell is coupled to a bit line, and the other end of the bit line is coupled to a first surface electrode. In addition, any two adjacent memory cells are insulated. The two first surface electrodes respectively coupled to the word line and the bit line coupled to the same memory cell are different.

In some embodiments, the three-dimensional memory array further includes a plurality of reference cells. Each memory cell is also connected to at least one reference cell among the plurality of reference cells, and the orthographic projection of the at least one reference cell on the first bonding layer is located in at least one of the word line and the bit line in the first bonding layer Outside the orthographic projection on the layer.

Optionally, the materials of the memory cell and the reference cell are both ferroelectric materials. The storage unit and the reference unit connected thereto are integrally formed, which can simplify the preparation process of the three-dimensional storage array.

In some embodiments, the read and write circuit includes multiple input/output terminals. The plurality of input/output terminals are coupled to the plurality of second surface electrodes in a one-to-one correspondence, and are configured to transmit control signals to word lines and/or bit lines in the three-dimensional memory array.

In some embodiments, the read and write circuit further includes: an address register, a decoder, a data input and output buffer, and a control logic circuit. The address register is configured to transmit address information to the decoder. The decoder is coupled to the address register and at least a part of the input/output terminals among the plurality of input/output terminals, and is configured to receive address information and address the corresponding input/output terminals according to the address information. The data input/output buffer is coupled to at least a part of the input/output terminals among the plurality of input/output terminals, and is configured to: write data information to the input/output terminal, or read data information from the input/output terminal. The control logic circuit is coupled to at least a part of the input/output terminals among the plurality of input/output terminals, and is configured to: write control information to the input/output terminals.

On the other hand, some embodiments of the present disclosure provide a method for manufacturing a three-dimensional memory, which is used to manufacture the three-dimensional memory described in some of the above embodiments. The preparation method of the three-dimensional memory includes: providing a first chip; the first chip includes a three-dimensional storage array and a first bonding layer, and the first bonding layer includes a plurality of first surface electrodes correspondingly coupled to the three-dimensional storage array. A second chip is provided; the second chip includes a read-write circuit and a second bonding layer, and the second bonding layer includes a plurality of second surface electrodes correspondingly coupled to the read-write circuit. The first bonding layer in the first chip is bonded with the second bonding layer in the second chip, so that the plurality of first surface electrodes and the plurality of second surface electrodes are coupled in a one-to-one correspondence.

In some embodiments, the first bonding layer further includes a first dielectric layer.

Optionally, the preparation method of the first chip includes: preparing a three-dimensional storage array; preparing a first dielectric layer on one side surface of the three-dimensional storage array; forming a plurality of first via holes in the first dielectric layer; First surface electrodes are respectively prepared in each of the first via holes, so that a plurality of first surface electrodes are correspondingly coupled to the three-dimensional memory array.

Optionally, the method for preparing the first chip includes: providing a first substrate, laminating and preparing a three-dimensional memory array and a first dielectric layer on one surface of the first substrate; forming a plurality of a first via hole; depositing a first metal film so that the part of the first metal film inside the first via hole is correspondingly coupled to the three-dimensional memory array; removing the part of the first metal film outside the first via hole, and polishing The surface of the first dielectric layer facing away from the three-dimensional storage array; the metal part exposed in the first via hole is the first surface electrode.

In some embodiments, the second bonding layer further includes a second dielectric layer.

Optionally, the preparation method of the second chip includes: preparing a read-write circuit; preparing a second dielectric layer on one surface of the read-write circuit; forming a plurality of second via holes in the second dielectric layer; Second surface electrodes are respectively prepared in the plurality of second via holes, so that the plurality of second surface electrodes are correspondingly coupled to the read-write circuit.

Optionally, the preparation method of the second chip includes: providing a second substrate, laminating and preparing a read-write circuit and a second dielectric layer on one surface of the second substrate; forming multiple layers in the second dielectric layer. forming a second via hole; depositing a second metal film so that the part of the second metal film inside the second via hole is correspondingly coupled to the read-write circuit; removing the part of the second metal film outside the second via hole, and The surface of the second dielectric layer facing away from the read-write circuit is polished; the metal part exposed in the second via hole is the second surface electrode.

In some embodiments, the first bonding layer further includes a first dielectric layer; the surfaces of the plurality of first surface electrodes and the first dielectric layer close to the second bonding layer are located on the same plane. The second bonding layer further includes a second dielectric layer; the surfaces of the plurality of second surface electrodes and the second dielectric layer close to the first bonding layer are located on the same plane. Bonding the first bonding layer with the second bonding layer includes: mixing the first bonding layer with the second bonding layer.

The technical effects that can be achieved by the methods for preparing a three-dimensional memory in some embodiments of the present disclosure are the same as the technical effects of the three-dimensional memory in some of the foregoing embodiments, which will not be repeated here.

In yet another aspect, some embodiments of the present disclosure provide an electronic device. Electronic devices include circuit boards and memory integrated on the circuit boards. The memory includes a three-dimensional memory as described in some of the above embodiments. The electronic device in some embodiments of the present disclosure may have better data storage capability and higher reliability in use.

Description of drawings

In order to illustrate the technical solutions in some embodiments of the present disclosure more clearly, the following briefly introduces the accompanying drawings used in the description of some embodiments. Obviously, the accompanying drawings in the following description are only some implementations of the present disclosure. For example, for those skilled in the art, other drawings can also be obtained from these drawings.

FIG. 1 is a schematic structural diagram of a three-dimensional memory according to some embodiments of the present disclosure;

2 is a partial cross-sectional view of a three-dimensional memory according to some embodiments of the present disclosure;

3 is a schematic diagram illustrating the relationship between relative positions between a memory cell and word lines, bit lines, and reference cells according to some embodiments of the present disclosure;

4A is a schematic diagram of the electric field of a memory cell shown in FIG. 3 when storing "1";

4B is a schematic diagram of the electric field of the memory cell shown in FIG. 3 when storing "0";

4C is a schematic diagram of the electric field of the memory cell shown in FIG. 3 when reading "1";

5A is a block diagram of a read-write circuit according to some embodiments of the present disclosure;

5B is a schematic diagram of the connection positions of some devices and the three-dimensional storage array in the read-write circuit shown in FIG. 5A;

6A is a schematic structural diagram of another three-dimensional memory according to some embodiments of the present disclosure;

6B is a schematic diagram of a bonding surface between a first surface electrode and a second surface electrode according to some embodiments of the present disclosure;

Fig. 7 is a manufacturing process diagram of a three-dimensional memory according to some embodiments of the present disclosure;

8 is a schematic structural diagram of still another three-dimensional memory according to some embodiments of the present disclosure;

FIG. 9 is a manufacturing process diagram of still another three-dimensional memory according to some embodiments of the present disclosure;

10A is a partial top view of a first chip according to some embodiments of the present disclosure;

Figure 10B is a cross-sectional view of the first chip shown in Figure 10A along the MM' direction;

Fig. 10C is a cross-sectional view of the first chip shown in Fig. 10A along the NN' direction;

10D is an enlarged schematic view of the I1 region in the first chip shown in FIG. 10C;

11A is a partial top view of another first chip according to some embodiments of the present disclosure;

Fig. 11B is a cross-sectional view of the first chip shown in Fig. 11A along the PP' direction;

Fig. 11C is a cross-sectional view of the first chip shown in Fig. 11A along the QQ' direction;

Fig. 11B' is a cross-sectional view along the PP' direction of another first chip shown in Fig. 11A;

Fig. 11C' is a cross-sectional view along the QQ' direction of another first chip shown in Fig. 11A;

Figure 11B" is a cross-sectional view of another first chip shown in Figure 11A along the PP' direction;

Fig. 11C" is a cross-sectional view of another first chip shown in Fig. 11A along the QQ' direction;

12A is a partial top view of yet another first chip according to some embodiments of the present disclosure;

Fig. 12B is a cross-sectional view along the RR' direction of a first chip shown in Fig. 12A;

Fig. 12C is a cross-sectional view of the first chip shown in Fig. 12A along the TT' direction;

12D is an enlarged schematic view of the I2 region in the first chip shown in FIG. 12A;

Fig. 12E is a cross-sectional view along the TT' direction of another first chip shown in Fig. 12A;

FIG. 13 is a schematic structural diagram of yet another storage unit according to some embodiments of the present disclosure;

14 is a partial cross-sectional view of a second chip in accordance with some embodiments of the present disclosure;

FIG. 15 is a schematic structural diagram of an electronic device according to some embodiments of the present disclosure.

Reference number:

1000-three-dimensional memory; 1001-first chip; 1002-second chip;

100-three-dimensional memory array; 101-memory cell; 102-bit line; 103-word line;

104-reference cell; 105-insulation layer; 106-bit layer; 107-interconnection layer; 108-first connection line;

200-first bonding layer; 201-first surface electrode; 202-first dielectric layer;

300-first substrate; 301-buffer medium layer; 400-reading and writing circuit;

401-input/output terminal; 4011-first type I/O; 4012-second type I/O;

402-data input and output buffer; 403-address register; 404-control logic circuit;

405-row decoder; 406-column decoder; 407-sense amplifier; 408-high voltage charge pump;

409-processor; 410-input/output electrode; 10-ferroelectric block;

500 - the second bonding layer; 501 - the second surface electrode; 502 - the second dielectric layer; 503 - the second connection line;

600-second substrate; 610-isolation barrier; 620-insulation layer; 630-diffusion barrier;

701-first metal pattern; 702-second metal pattern; 703-third metal pattern;

1-electronic equipment; 11-housing; 12-circuit board.

Detailed ways

The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in some embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all of the embodiments. . Based on some embodiments in the present disclosure, all other embodiments that can be obtained by those of ordinary skill in the art fall within the protection scope of the present disclosure.

Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms such as the third person singular "comprises" and the present participle "comprising" are used It is interpreted as the meaning of openness and inclusion, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" example)" or "some examples" and the like are intended to indicate that a particular feature, structure, material or characteristic related to the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

Hereinafter, ordinal numbers such as the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first", "second", etc., may expressly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

In describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also mean that two or more components are not in direct contact with each other, yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited by the content herein.

"At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: A only, B only, C only, A and B , A and C, B and C, and A, B, and C.

"A and/or B" includes the following three combinations: A only, B only, and a combination of A and B.

The use of "adapted to" or "configured to" herein means open and inclusive language that does not preclude devices adapted or configured to perform additional tasks or steps. Additionally, the use of "based on" is meant to be open and inclusive, as a process, step, calculation or other action "based on" one or more of the stated conditions or values may in practice be based on additional conditions or beyond the stated values.

Furthermore, for clearly representing various layers and regions in the drawings, the thicknesses of each layer in the drawings are exaggerated, so as to clearly illustrate the relative positions of the various layers. When a section stated as a layer, film, region, panel, etc. is "over" or "on" another section, the expression includes not only "directly" over the other section, but also intervening other layers.

Ferromagnetic Random Access Memory (FRAM) stores data based on the ferroelectric effect of ferroelectric crystals, and has the performance of non-volatile memory. Two-dimensional ferroelectric memories, also known as planar ferroelectric memories, can be scaled smaller by improving fabrication processes, circuit designs, and programming algorithms to increase their storage density. However, as the size of each memory cell in the two-dimensional ferroelectric memory approaches the minimum limit, the storage density of the two-dimensional ferroelectric memory will also reach the maximum limit, making it difficult to further effectively improve. Therefore, applying three-dimensional storage technology in ferroelectric memory, for example, stacking multiple layers of memory cells in the vertical direction of the two-dimensional plane, so that each memory cell can also extend in the vertical direction of the two-dimensional plane, which can effectively improve the storage capacity of the ferroelectric memory. density, so as to facilitate the realization of large-capacity and fast storage of data in memory.

Based on this, some embodiments of the present disclosure provide a three-dimensional memory, such as a three-dimensional ferroelectric memory.

Please refer to FIG. 1 , the three-dimensional memory 1000 includes a first chip 1001 and a second chip 1002 . The first chip 1001 includes the three-dimensional memory array 100 and the first bonding layer 200 . The second chip 1002 includes the read-write circuit 400 and the second bonding layer 500 . The first bonding layer 200 is located on a side of the three-dimensional memory array 100 close to the read-write circuit 400 . The first bonding layer 200 includes a plurality of first surface electrodes 201 correspondingly coupled to the three-dimensional memory array 100 . The second bonding layer 500 is located on the side of the read/write circuit 400 close to the three-dimensional memory array 100 . The second bonding layer 500 includes a plurality of second surface electrodes 501 correspondingly coupled to the read-write circuit 400 . The first bonding layer 200 and the second bonding layer 500 are bonded, and the plurality of first surface electrodes 201 are coupled to the plurality of second surface electrodes 501 in a one-to-one correspondence.

Here, the first chip 1001 and the second chip 1002 may be obtained by wafer fabrication. For example, the first chip 1001 and the second chip 1002 are chips obtained by dicing after being fabricated on a wafer. Optionally, the dicing of the first chip 1001 and the second chip 1002 may be performed after the bonding of the corresponding two wafers. This embodiment of the present disclosure does not limit this.

The three-dimensional memory array 100 may have various structures. FIG. 2 shows a partial cross-sectional structure of the three-dimensional memory 1000 . The following description about the three-dimensional memory array 100 and the read-write circuit 400 can be understood in conjunction with FIG. 2 .

As shown in FIG. 2 , the three-dimensional memory array 100 at least includes a plurality of memory cells 101 , a plurality of bit lines 102 and a plurality of word lines 103 . The plurality of storage units 101 are distributed in an array in a three-dimensional space.

FIG. 3 shows a relative positional relationship between the memory cell 101 , the word line 103 and the bit line 102 . As shown in FIG. 3 , one end (eg, the first surface S1 ) of each memory cell 101 is coupled to a word line 103 , and the other end (eg, the second surface S2 ) is coupled to a bit line 102 , and the memory cell 101 can be in The read and write operations of the data signals are performed under the control of the electric field formed by the electrical signals provided by the word lines 103 and the bit lines 102 . In addition, any two adjacent memory cells 101 are insulated to ensure that the memory operations between the two adjacent memory cells 101 do not affect each other.

In some embodiments, as shown in FIG. 2 , the extending direction of the word line 103 and the extending direction of the bit line 102 intersect, eg, perpendicular. One word line 103 is correspondingly coupled to the memory cells 101 located in the same row, and one bit line 102 is correspondingly coupled to the memory cells 101 located in the same column. Therefore, it is beneficial to simplify the wiring design of the word lines 103 and the bit lines 102 in the three-dimensional memory array 100 .

Here, the shape of the storage unit 101 can be selected according to actual needs, for example, the shape of the storage unit 101 is a prism such as a triangular prism or a quadrangular prism; or the shape of the storage unit 101 is a block such as a cuboid or a cube. The two ends of the aforementioned memory cell 101 refer to its surfaces located in different directions, for example, the first surface S1 and the second surface S2 located in different directions respectively. That is, the first surface S1 and the second surface S2 may be two opposite surfaces, or may be two intersecting surfaces (for example, as shown in subsequent FIGS. 10D , 12D and 13 ).

In some embodiments in which the three-dimensional memory array 100 is a three-dimensional ferroelectric memory array, the memory cells 101 are made of ferroelectric materials, and their electric domains can undergo polarization inversion under the action of an external electric field to realize unidirectional conduction. The direction of the applied electric field is not perpendicular to the initial polarization direction of the electric domain in the memory cell 101 , for example, the direction of the applied electric field is parallel to the initial polarization direction of the electric domain in the memory cell 101 or forms an included angle not equal to 90 degrees.

Please continue to refer to FIG. 2 and FIG. 3 , the three-dimensional ferroelectric memory array further includes a plurality of reference cells 104 . One or more reference cells 104 are correspondingly disposed on the peripheral side of each storage cell 101. The third surface S3 of each memory cell 101 is connected to the corresponding reference cell 104 . The third surface S3 of the memory cell 101 refers to a surface other than the aforementioned first surface S1 and second surface S2 (eg, as shown in subsequent FIGS. 10D , 12D , and 13 ). The number of the third surfaces S3 may be one or more.

Each reference unit 104 is formed by using a ferroelectric material, and can be formed in the same production process as the corresponding memory unit 101 , for example, integrally formed. The orthographic projection of the reference cell 104 on the surface of the first bonding layer 200 is located outside the orthographic projection of at least one of the word line 103 and the bit line 102 on the first bonding layer 200 . In this way, each reference cell 104 can be located outside the electric field formed by the corresponding word line 103 and the bit line 102 , and the electric domain of the ferroelectric material in the reference cell 104 will not be generated under the action of the electric field formed by the word line 103 and the bit line 102 Polarization reversal. The initial polarization directions of the electric domains of the reference cell 104 and the memory cell 101 are the same. The electric domain of the reference cell 104 is used as a reference for the inversion of the electric domain polarization of the memory cell 101, and the polarization direction of the electric domain of the reference cell 104 remains unchanged. In this way, when the polarization direction of the electric domain of the memory cell 101 is different from the polarization direction of the electric domain of the reference cell 104, a conductive domain wall is formed between the memory cell 101 and the corresponding reference cell 104, and the memory cell 101 can store non- Volatile logical data. When the polarization direction of the electric domain of the memory cell 101 is the same as the polarization direction of the electric domain of the reference cell 104, there is no conductive domain wall between the memory cell 101 and the corresponding reference cell 104, and the memory cell 101 does not store a volatile logical data is erased.

The following is a schematic description of the read/write control of one storage unit 101 shown in FIG. 3 .

Illustratively, as shown in FIG. 3 , the initial polarization directions of the electric domains in the memory cell 101 and the reference cell 104 are horizontal to the left. The coercive electric field of the memory cell 101 is Ec.

As shown in FIG. 4A , a first electric field E1 is applied to the memory cell 101 through the word line 103 and the bit line 102 , and the direction of the first electric field E1 is, for example, horizontal to the right. The first electric field E1 is greater than the coercive electric field Ec of the memory cell 101 , so that the electric domain of the memory cell 101 undergoes the first polarization inversion. For example, the direction of the electric domain of the memory cell 101 after the first polarization reversal is horizontal to the right. In this case, conductive domain walls are formed between the memory cells 101 and the corresponding reference cells 104 . After the first electric field E1 is removed, the aforementioned conductive domain walls still exist. The storage unit 101 is capable of storing nonvolatile logical data, that is, the storage unit 101 writes a digital signal "1".

As shown in FIG. 4B , a second electric field E2 is applied to the memory cell 101 through the word line 103 and the bit line 102 , and the direction of the second electric field E2 is, for example, horizontal to the left. The second electric field E2 is greater than the coercive electric field Ec of the memory cell 101 , so that the electric domain of the memory cell 101 undergoes a second polarization inversion. For example, the direction of the electric domain of the memory cell 101 after the second polarization reversal is horizontal to the left, that is, reversed back to the initial polarization direction. In this way, the conductive domain wall between the memory cell 101 and the reference cell 104 disappears. The nonvolatile logical data stored in the memory cell 101 is erased, that is, the memory cell 101 writes a digital signal "0".

As shown in FIG. 4C , a third electric field E3 is applied to the memory cell 101 through the word line 103 and the bit line 102 . The direction of the third electric field E3 is the same as that of the first electric field E1 , for example, horizontal to the right. The third electric field E3 is smaller than the coercive electric field Ec of the memory cell 101, and the voltage difference between the two ends of the memory cell 101 coupled to the word line 103 and the bit line 102 in the third electric field should be greater than the threshold voltage of the memory cell 101 as Vth. In this case, if the conductive domain wall between the memory cell 101 and the reference cell 104 still exists, a conductive current will be generated between the word line 103 and the bit line 102, so that the memory cell can be read by the current value output by the bit line 102 101 The currently stored digital signal "1". If the conductive domain wall between the memory cell 101 and the reference cell 104 disappears, the conductive current generated between the word line 103 and the bit line 102 is extremely small, so that the memory cell 101 can be read through the extremely small current value output by the bit line 102 The currently stored digital signal "0". That is to say, according to the magnitude of the current value output by the bit line 102, it can be determined whether the digital signal currently stored in the storage unit 101 is "1" or "0".

Here, the threshold voltage Vth of the memory cell 101 refers to the minimum voltage value for realizing the conduction of the domain wall, for example, 1V. That is, in the case where the voltage difference between the two ends of the memory cell 101 coupled to the word line 103 and the bit line 102 in the third electric field is less than its threshold voltage Vth, even if there is conduction between the memory cell 101 and the reference cell 104 Domain walls, no conduction current is generated between the word line 103 and the bit line 102 .

It can be seen from the above that after the first electric field E1 is applied to the memory cell 101, the electric domain polarization direction of the memory cell 101 is different from the electric domain polarization direction of the corresponding reference cell 104, and a conductive domain wall is formed between the two, and the memory cell 101 is in the on state (ie, the conduction state). After the second electric field E2 is applied to the memory cell 101, the electric domain polarization direction of the memory cell 101 is the same as the electric domain polarization direction of the corresponding reference cell 104, the memory cell 101 and the reference cell 104 are in an insulating state as a whole, and the memory cell 101 is OFF state (ie, non-conducting state). The memory cell 101 has a unidirectional conduction characteristic. In addition, the initial state of the memory cell 101 is an off state.

It can be understood that by respectively inputting voltage signals to the word line 103 and the bit line 102 corresponding to each memory cell 101 , a corresponding electric field can be applied to the memory cell 101 through the two voltage signals. The input of the voltage signals on the word line 103 and the bit line 102 is controlled by the read and write circuit 400 in the second chip 1002 . Please continue to refer to FIG. 2 , the read/write circuit 400 includes a plurality of input/output terminals (I/O) 401 . The structure, quantity and distribution of the input/output terminals 401 can be selected and set according to actual requirements. Exemplarily, a plurality of input/output terminals 401 in the read/write circuit 400 are distributed in an array, and each input/output terminal 401 is configured to be coupled to a second surface electrode 501 . After the second surface electrode 501 and the first surface electrode 201 are coupled, the first surface electrode 201 is correspondingly coupled to a word line 103 or a bit line 102 . Therefore, using the two input/output terminals 401, a control signal can be provided to a word line 103 and a bit line 102, respectively, so as to provide a control signal (ie, apply an electric field) to the corresponding memory cell 101 through the word line 103 and the bit line 102. , in order to perform read and write operations.

Here, the structure of the read/write circuit 400 can be selected and set according to actual requirements, limited to outputting control signals to the word line 103 and the bit line 102 to control the corresponding memory cell 101 to perform read and write operations. This embodiment of the present disclosure does not limit this.

Optionally, referring to FIG. 5A and FIG. 5B , the plurality of input/output terminals 401 include a first type of I/O (eg row I/O) 4011 and a second type of I/O (eg column I/O) 4012 . The read/write circuit 400 further includes a data input/output buffer 402, an address register 403, a control logic circuit 404, a row decoder 405, a column decoder 406, and the like. The row decoder 405 is coupled to the first type I/O 4011 correspondingly. The column decoder 406 is coupled to the second type I/O 4012 correspondingly. The row decoder 405 and the column decoder 406 are respectively coupled to the address register 403 . Address register 403 is configured to transfer address information to row decoder 405 and column decoder 406 . Row decoder 405 and column decoder 406 are configured to receive address information and address corresponding input/output terminals 401 according to the address information. The data input/output buffer 402 is coupled to a plurality of input/output terminals 401 and is configured to: write data information to the input/output terminal 401 or read data information from the input/output terminal 401 . The control logic circuit 404 is coupled to the plurality of input/output terminals 401 and is configured to: write control information to the input/output terminals 401 .

In some embodiments where the second type I/O 4012 is correspondingly coupled to each bit line 102 , the read/write circuit 400 further includes a sense amplifier 407 coupled to the second type I/O 4012 and the data input and output buffer 402 , respectively. The sense amplifier 407 is configured to read data information from the input/output terminal 401 and transmit the amplified data information to the data input/output buffer 402 .

It should be noted that the data input and output buffer 402 , the address register 403 and the control logic circuit 404 in the read-write circuit 400 can be coupled to external control devices such as processors or executors, so as to execute corresponding control instructions according to the control instructions of the external control devices. action. For example, the external control device is a central processing unit (Central Processing Unit, CPU for short), a single-chip microcomputer, or a digital signal processor. For example, the external control device is the processor 409 . In the case of performing a read operation, the data read from the second type I/O 4012 can be stored in the data input and output buffer 402 through the sense amplifier 407 for the processor 409 to read. In the case of performing a write operation, the address register 403 can output address information to the row decoder 405 and the column decoder 406 (that is, the addressing unit) under the control command transmitted by the external control device, so as to pass the corresponding first A type of I/O 4011 and a second type of I/O 4012 write data into the three-dimensional storage array 100 .

In addition, optionally, the read-write circuit 400 further includes a high-voltage charge pump 408 coupled to the control logic circuit 404 . The high-voltage charge pump 408 can write the boost signal into the three-dimensional memory array 100 under the action of the control command transmitted by the control logic circuit 404 . For example, the high-voltage charge pump 408 is coupled to the aforementioned row I/O 4011 and column I/O 4012, respectively, and can output a boost signal through the corresponding row I/O 4011 or column I/O 4012 when needed. In some examples, as shown in FIG. 5B , the row decoder 405 , the column decoder 406 and the high voltage charge pump 408 are located on different sides of the three-dimensional memory array 100 , which facilitates the wiring design of the read-write circuit 400 and simplifies the The structure of the read/write circuit 400 .

In some embodiments of the present disclosure, please continue to refer to FIG. 1 , the three-dimensional memory array 100 and the read-write circuit 400 in the three-dimensional memory 1000 are respectively prepared in different chips. For example, the three-dimensional memory array 100 is prepared in the first chip 1001 , and the read-write circuit 400 is prepared in the second chip 1002 . In this way, the manufacturing process flow of the three-dimensional memory array 100 and the read-write circuit 400 can be performed separately.

In the preparation process of the first chip 1001 , after the stacking of the multi-layer memory cells 101 in the three-dimensional memory array 100 is completed, the signal lines (including the word line 103 , the bit line 102 or its extension lines) can be drawn to the surface of the three-dimensional memory array 100 as the memory cells 101 are fabricated. In this way, the first bonding layer 200 is formed on the prepared surface of the three-dimensional memory array 100, that is, the surface of the three-dimensional memory array 100 close to the read-write circuit 400, so that the first surface electrodes in the first bonding layer 200 can be formed. 201 is directly coupled to the corresponding signal line in the three-dimensional memory array 100 . For example, each first surface electrode 201 of the plurality of first surface electrodes 201 is correspondingly coupled to one word line 103 or one bit line 102 in the three-dimensional memory array 100 .

Similarly, in the preparation process of the second chip 1002, after the read-write circuit 400 is prepared, the plurality of input/output terminals 401 of the read-write circuit 400 can be located on the surface thereof. In this way, the second bonding layer 500 is formed on the prepared surface of the read-write circuit 400, that is, the surface of the read-write circuit 400 close to the three-dimensional memory array 100, so that the second surface electrode in the second bonding layer 500 can be formed. 501 is directly coupled to the corresponding input/output terminal 401 in the read/write circuit 400 . For example, each of the plurality of second surface electrodes 501 is coupled to one input/output (I/O) 401 correspondingly.

On this basis, the first bonding layer 200 in the first chip 1001 and the second bonding layer 500 in the second chip 1002 are bonded, so that the first surface electrode 201 in the first bonding layer 200 and the second bonding layer 500 in the second chip 1002 are bonded. The direct coupling of the second surface electrodes 501 in the two-bond layer 500 can simply and directly realize the corresponding coupling between the three-dimensional memory array 100 and the read-write circuit 400 in the three-dimensional memory 1000 . It is coupled with the read-write circuit 400 by means of alignment and snapping. In this way, the three-dimensional storage array is prepared on the surface of the read-write circuit, and via holes are formed from the surface of the three-dimensional storage array away from the read-write circuit to the read-write circuit, so as to realize the connection between the signal line in the three-dimensional storage array and the input/output end of the read-write circuit. Compared with coupling, the embodiment of the present disclosure adopts the direct bonding method of the first chip 1001 and the second chip 1002, and the preparation process is relatively simple. 100 to the vias on the surface of the read-write circuit 400 . In this way, there will be no difficulty in preparing vias due to the avoidance of the positions between the vias and signal lines in the three-dimensional memory array 100, and metal lines breakage due to the small aperture and large hole depth of the vias, etc. question. In addition, the first surface electrode 201 in the first chip 1001 and the second surface electrode 501 in the second chip 1002 are in contact and coupled, which is beneficial to ensure reliable coupling between the three-dimensional memory array 100 and the read-write circuit 400 . Therefore, it is beneficial to improve the reliability of the coupling between the three-dimensional memory array 100 and the read-write circuit 400 , thereby improving the use reliability of the three-dimensional memory 1000 .

Here, the first bonding layer 200 and the second bonding layer 500 may be independent layer structures, or may be a bonding surface. The first surface electrode 201 refers to an electrode exposed in the surface of the first bonding layer 200 away from the three-dimensional memory array 100 and arranged in a planar shape; the first surface electrode 201 may be close to the second bond of the first bonding layer 200 The surfaces of the laminate 500 are located on the same plane. The second surface electrode 501 refers to an electrode exposed in the surface of the second bonding layer 500 away from the read-write circuit 400 and arranged in a planar shape; the second surface electrode 501 may be close to the first bond of the second bonding layer 500 The surfaces of the laminate 200 are located on the same plane.

In some examples, please continue to refer to FIG. 1 , the first bonding layer 200 further includes a first dielectric layer 202 . The first dielectric layer 202 has a plurality of first via holes H1. The multiple first surface electrodes 201 are located in the multiple first via holes H1 in a one-to-one correspondence, and the surfaces of the first surface electrodes 201 and the first dielectric layer 202 close to the second bonding layer 500 are located on the same plane. The second bonding layer 500 also includes a second dielectric layer 502 . The second dielectric layer 502 has a plurality of second via holes H2. The plurality of second surface electrodes 501 are located in the plurality of second via holes H2 in a one-to-one correspondence, and the surfaces of the plurality of second surface electrodes 501 and the second dielectric layer 502 close to the first bonding layer 200 are located in the same flat. The plurality of second surface electrodes 501 are in one-to-one correspondence with the plurality of first surface electrodes 201 described above. The bonding method of the first bonding layer 200 and the second bonding layer 500 may be hybrid bonding; that is, the first dielectric layer 202 and the second dielectric layer 502 are bonded, and the first surface electrode 201 is connected to the corresponding The second surface electrode 501 is bonded.

In the embodiment of the present disclosure, the first surface electrode 201 is disposed in the first via hole H1 of the first dielectric layer 202, and the second surface electrode 501 is disposed in the second via hole H2 of the second dielectric layer 502, The existence of the first dielectric layer 202 and the second dielectric layer 502 can be used to improve the quality of the bonding surface between the first bonding layer 200 and the second bonding layer 500, for example, to ensure that the first bonding layer 200 and the second bonding layer The bonding surfaces between the bonding layers 500 are relatively flat or smooth. In this way, after the first dielectric layer 202 is formed on the surface of the three-dimensional memory array 100, the position and size of the first surface electrode 201 can be accurately defined by using the first via hole H1 therein. After the second dielectric layer 502 is formed on the surface of the read-write circuit 400 , the position and size of the second surface electrode 501 can be accurately defined by using the second via hole H2 therein. Therefore, it is ensured that the first surface electrode 201 and the three-dimensional memory array 100, the first surface electrode 201 and the second surface electrode 501, and the second surface electrode 501 and the read-write circuit 400 can be aligned and coupled, and have better coupling. performance, so that the use reliability of the three-dimensional memory 1000 can be further improved. In addition, the word lines 103 or bit lines 102 of each layer in the three-dimensional memory array 100 can be drawn out section by section along with the fabrication of signal lines in some different layers (including the word lines 103 or bit lines 102 of different layers), thereby avoiding Prepare vias with larger hole depths. In addition, the bonding method of the first bonding layer 200 and the second bonding layer 500 is hybrid bonding, which can achieve both good bonding strength and electrical conductivity.

It should be noted that the to-be-bonded interface of the first bonding layer 200 and the second bonding layer 500 is flat and smooth, which is beneficial to realize the alignment bonding between the first surface electrode 201 and the corresponding second surface electrode 501, So as to achieve a good electrical connection between the two. However, in the actual preparation process, the to-be-bonded interface of the first bonding layer 200 and the second bonding layer 500 may be uneven. For example, as shown in FIG. 6A , the surface of the first surface electrode 201 close to the second bonding layer 500 protrudes from the first dielectric layer 202 , and the surface of the second surface electrode 501 close to the first bonding layer 200 protrudes from the second surface The dielectric layer 502 is formed such that there is an interval L between the first dielectric layer 202 and the second dielectric layer 502 . In this case, the first surface electrodes 201 in the first bonding layer 200 and the second surface electrodes 501 in the second bonding layer 500 are correspondingly bonded, and can also have good electrical connection.

In addition, on the basis of some of the above-mentioned embodiments, please refer to FIG. 6B , when the bonding surface between the first surface electrode 201 and the second surface electrode 501 occurs in the following situations, the first surface electrode 201 and the corresponding Effective electrical connection can also be achieved between the second surface electrodes 501. Illustratively, as shown in A in FIG. 6B , there is a gap between the first surface electrode 201 and the second surface electrode 501 . Alternatively, as shown in B in FIG. 6B , at least one of the first surface electrode 201 and the second surface electrode 501 is in a pressed and bent state. Alternatively, as shown in C in FIG. 6B , the first surface electrode 201 and the second surface electrode 501 are bonded by dislocation. Alternatively, as shown in D and E in FIG. 6B , the orthographic projection area of one of the first surface electrode 201 and the second surface electrode 501 on the bonding surface is larger than the orthographic projection area of the other on the bonding surface , which can effectively ensure that the first surface electrode 201 and the second surface electrode 501 still have a good bonding effect in the case of dislocation between the first surface electrode 201 and the second surface electrode 501 . Alternatively, as shown in F in FIG. 6B , the first surface electrode 201 and the second surface electrode 501 are stepped electrodes, and the larger surface of the stepped electrodes is used for bonding, which can ensure that the first surface electrode 201 and the second surface electrode 501 are The second surface electrode 501 has a good bonding effect. It can be understood that the setting situation of the bonding surface between the first surface electrode 201 and the second surface electrode 501 is not limited to this, and any other situation that can realize the electrical connection between the first surface electrode 201 and the second surface electrode 501 are applicable.

The above-mentioned first surface electrode 201 and second surface electrode 501 are both made of materials with good electrical conductivity, which is beneficial to ensure that the first surface electrode 201 and the second surface electrode 501 can have good electrical connection after bonding. Optionally, the preparation material of at least one of the first surface electrode 201 and the second surface electrode 501 includes: iridium, platinum, tungsten, nickel, cobalt, copper, aluminum, polysilicon, silicon-doped metal or metal silicide at least one of them.

The materials of the dielectric layers in the first bonding layer 200 and the second bonding layer 500 can be selected and set according to actual requirements.

In some embodiments, the first dielectric layer 202 may be formed directly on the surface of the three-dimensional memory array 100 . The second dielectric layer 502 may be formed directly on the surface of the read-write circuit 400 . FIG. 7 shows a manufacturing process of the three-dimensional memory 1000 . The first dielectric layer 202 in the first bonding layer 200 and the second dielectric layer 502 in the second bonding layer 500 may be silicon oxide, silicon nitride, or benzocyclobutene (BCB for short) , lithium tantalate (LiTaO3) or lithium niobate (LiNbO3) and other dielectric materials are prepared.

Exemplarily, as shown in FIG. 7 , when the first chip 1001 in the three-dimensional memory 1000 is prepared, the three-dimensional memory array 100 is first prepared. For example, the three-dimensional storage array 100 is a three-dimensional ferroelectric storage array, and the three-dimensional storage array 100 is formed by digging holes in a ferroelectric single crystal wafer and filling electrode lines. Here, the material of the ferroelectric single crystal wafer includes but is not limited to lithium tantalate (LiTaO3), lithium niobate (LiNbO3), blackened lithium tantalate (LiTaO3) or lithium niobate (LiNbO3) ), or doped with at least one lithium tantalate (LiTaO3) or lithium niobate ( LiNbO3).

In addition, optionally, doping lithium tantalate (LiTaO3) or niobium selected from at least one of magnesium oxide (MgO), manganese pentoxide (Mn2O5), iron oxide (Fe2O3) or lanthanum oxide (La2O3) In the lithium acid salt (LiNbO3), the molar percentage of the dopant material ranges from 0.1 mol% to 10 mol%. Optionally, the value range of the resistivity of the blackened lithium tantalate (LiTaO3) or lithium niobate (LiNbO3) is 1×10 6Ω·cm～1×10 13Ω·cm.

Then, the first dielectric layer 202 is prepared directly on the surface of the three-dimensional memory array 100 . After that, a plurality of first via holes H1 are formed in the first dielectric layer 202, and a plurality of first surface electrodes 201 correspondingly coupled to the three-dimensional memory array 100 are formed in the plurality of first via holes H1, so that the first surface electrode 201 can be obtained. A chip 1001.

Similarly, as shown in FIG. 7 , when preparing the second chip 1002 in the three-dimensional memory 1000 , the read-write circuit 400 is first prepared independently, and then the second dielectric layer 502 is directly prepared on the surface of the read-write circuit 400 . Then, a plurality of second via holes H2 corresponding to each input/output terminal (I/O) 401 one-to-one are formed in the second dielectric layer 502, and an input/output port H2 is formed in each second via hole H2 The terminal (I/O) 401 is correspondingly coupled to the second surface electrode 501, and the second chip 1002 can be obtained.

In other embodiments, the three-dimensional memory array 100 in the first chip 1001 can be directly fabricated on a wafer or other substrates. The read/write circuit 400 in the second chip 1002 can also be directly fabricated on a wafer or other substrates. The first dielectric layer 202 in the first bonding layer 200 and the second dielectric layer 502 in the second bonding layer 500 can be formed by using common insulating materials, such as insulating resins or silicon oxide materials, benzo rings Butene (benzocyclobutene, BCB) and so on. This embodiment of the present disclosure does not limit this.

Illustratively, as shown in FIG. 8 , the first chip 1001 further includes a first substrate 300 . The three-dimensional memory array 100 is disposed on the first substrate 300 . The first bonding layer 200 is located on the surface of the three-dimensional memory array 100 facing away from the first substrate 300 . The second chip 1002 also includes a second substrate 600 . The read-write circuit 400 is disposed on the second substrate 600 . The second bonding layer 500 is located on the surface of the read-write circuit 400 facing away from the second substrate 600 .

Here, the material of the first substrate 300 may be a ferroelectric single crystal material or a material such as single crystal silicon. The ferroelectric single crystal material is the same as that of the aforementioned ferroelectric single crystal wafer, and will not be described in detail here. The first substrate 300 is, for example, diced particles from a wafer, that is, the first chip 1001 can be obtained by dicing after being prepared on the wafer.

Optionally, the three-dimensional storage array 100 is a three-dimensional ferroelectric storage array. That is, each memory cell 101 and each reference cell 104 in the three-dimensional memory array 100 are constituted by patterned multilayer ferroelectric thin films. The materials of ferroelectric thin films include but are not limited to lithium tantalate (LiTaO3), lithium niobate (LiNbO3), bismuth ferrite (BiFeO3), lead zirconate titanate [(Pb, Zr)TiO3] or barium titanate (BaTiO3) ), blackened lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), or doped with magnesium oxide (MgO), manganese pentoxide (Mn2O5), iron oxide (Fe2O3) or lanthanum oxide (La2O3) at least one of lithium tantalate (LiTaO3), lithium niobate LiNbO3 or bismuth ferrite BiFeO3. The ferroelectric thin film (including the memory cell 101 and the reference cell 104 ) can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or thin film bonding.

Optionally, the ferroelectric thin film in the three-dimensional storage array 100 is fabricated on the first substrate 300 by a thin film bonding process, which can obtain a high-quality ferroelectric thin film, thereby ensuring that the three-dimensional storage array 100 has good storage performance. For example, an ion layer of a target thickness, such as helium (He) ions or hydrogen (H) ions, is implanted on the surface of a high-quality ferroelectric single crystal wafer by an ion implantation process. Then, the ferroelectric single crystal wafer is directly bonded to a first substrate 300, such as a silicon wafer. Finally, an annealing process is used to reduce the interlayer ions in the ion layer to a gas (helium or hydrogen) to ensure that the gas escapes from the interlayer and leaves a gap between the layers, so that the ferroelectric of the target thickness can be directly stripped film. Alternatively, the bonded ferroelectric single crystal wafer is polished to a target thickness thin film by direct polishing. Here, the target thickness is, for example, 100 nm±5 nm.

In addition, as shown in FIG. 8 , in the first chip 1001 , a buffer medium layer 301 may be epitaxially formed on the surface of the first substrate 300 to optimize the surface quality of the first substrate 300 by using the buffer medium layer 301 . In this way, after the three-dimensional storage array 100 is fabricated on the surface of the buffer medium layer 301 , a higher-quality ferroelectric thin film can be obtained, so as to improve the storage performance of the three-dimensional storage array 100 .

Here, the second substrate 600 is used as a carrier of the read-write circuit 400, and its preparation material may be monocrystalline silicon or SOI (Silicon-on-Insulator) base material or the like. The second substrate 600 is, for example, diced particles from a wafer, that is, the second chip 1002 can be obtained by dicing after being prepared on the wafer.

It should be added that the first chip 1001 and the second chip 1002 can be obtained by dicing after the wafer-level bonding is completed.

FIG. 9 shows a manufacturing process of the three-dimensional memory 1000 shown in FIG. 8 . As shown in FIG. 9 , when the first chip 1001 in the three-dimensional memory 1000 is prepared, a first substrate 300 is first provided, and the first substrate 300 may include a buffer medium layer 301 epitaxially grown on its surface (in FIG. 9 ). not shown). Then, the three-dimensional memory array 100 and the first dielectric layer 202 are sequentially prepared on the first substrate 300 , and a plurality of first via holes H1 are formed in the first dielectric layer 202 . After that, a first metal film 2010 is deposited, so that the portion of the first metal film 2010 located in the first via hole H1 is coupled to the three-dimensional memory array 100 correspondingly. The first metal film 2010 at least partially covers the surface of the first dielectric layer 202 facing away from the three-dimensional memory array 100 . Finally, the part of the first metal film 2010 outside the first via hole H1 is removed, and the surface of the first dielectric layer 202 facing away from the three-dimensional memory array 100 is polished; thus, the exposed metal part in the first via hole H1 is The first surface electrode 201 . Thus, the first chip 1001 can be obtained.

Here, removing the portion of the first metal film 2010 outside the first via hole H1 and polishing the surface of the first dielectric layer 202 away from the three-dimensional memory array 100 can be accomplished through the same polishing process, such as chemical mechanical polishing. (Chemical Mechanical Polish, referred to as CMP) polishing, but not limited to this.

Similarly, as shown in FIG. 9 , when the second chip 1002 in the three-dimensional memory 1000 is fabricated, the second substrate 600 is first provided. Then, the read/write circuit 400 and the second dielectric layer 502 are sequentially prepared on the second substrate 600 , and multiple input/output terminals (I/O) 401 corresponding to each input/output terminal (I/O) 401 are formed in the second dielectric layer 502 in one order. a second via H2. After that, a second metal film 5010 is deposited, so that the portion of the second metal film 5010 located in the second via hole H2 is coupled to the read-write circuit 400 correspondingly. The second metal film 5010 at least partially covers the surface of the second dielectric layer 502 facing away from the read/write circuit 400 . Finally, the part of the second metal film 5010 located outside the second via hole H2 is removed, and the surface of the second dielectric layer 502 facing away from the read-write circuit 400 is polished; thus, the exposed metal part in the second via hole H2 is The second surface electrode 501 . Thus, the second chip 1002 can be obtained.

Here, removing the part of the second metal film 5010 outside the second via hole H2 and polishing the surface of the second dielectric layer 502 away from the read-write circuit 400 can be completed by the same polishing process, such as CMP polishing, but It is not limited to this.

In the embodiment of the present disclosure, the similar preparation processes of the first chip 1001 and the second chip 1002 are placed in the same drawing to express, which does not mean that the preparation processes of the two need to be implemented correspondingly; that is, the first chip 1001 and the second chip 1002 The chip 1002 can be prepared by any feasible preparation method according to its structure, which is not limited in this embodiment of the present disclosure. In addition, the preparation of the first chip 1001 and the second chip 1002 may be performed on different production lines, and the different production lines may be different production lines of the same manufacturer, or may be production lines of different manufacturers. Of course, the bonding of the first chip 1001 and the second chip 1002 is also allowed at the manufacturer of the first chip 1001, the manufacturer of the second chip 1002, or other different manufacturers. This embodiment of the present disclosure does not limit this.

It should be added that in the process of preparing the first chip 1001 and the second chip 1002, alignment marks are usually formed on the first substrate 300 and the second substrate 600 or the wafers to which they belong. In this way, after the first chip 1001 and the second chip 1002 are prepared separately, the first chip 1001 and the second chip 1002 are aligned and bonded according to the alignment marks, so that a plurality of first surface electrodes 201 and a plurality of second chips can be formed. The surface electrodes 501 are coupled in one-to-one correspondence. Here, the shape, quantity and setting position of the alignment marks can be selected and set according to actual needs. This embodiment of the present disclosure does not limit this.

To sum up, in the embodiment of the present disclosure, the three-dimensional memory 1000 is formed by bonding the first chip 1001 and the second chip 1002, so that the manufacturing process flow of the first chip 1001 and the second chip 1002 can be performed separately. In this way, the first chip 1001 and the second chip 1002 can be fabricated at the same time, thereby effectively shortening the production cycle of the three-dimensional memory 1000 . In addition, the preparation of the first chip 1001 is performed on its independent production line, which can avoid adverse effects of other production materials on the production line, such as the problem of cross-contamination of production materials caused by shared production lines.

In addition, in some embodiments where the three-dimensional storage array 100 is a three-dimensional ferroelectric storage array, the preparation of the three-dimensional ferroelectric storage array requires high temperature annealing of ferroelectric materials such as ferroelectric single crystal wafers or ferroelectric thin films to repair the ferroelectric Defects in materials. Since the read-write circuit 400 in the second chip 1002 is usually made of conductive metal (eg, copper, aluminum, etc.), it is easily affected by high temperature. Therefore, the preparation process of the three-dimensional ferroelectric memory array and the read-write circuit 400 are carried out separately, which can also avoid adverse effects on the read-write circuit 400 due to high temperature annealing when stacking the three-dimensional ferroelectric memory array on the read-write circuit 400, so that the read-write circuit 400 can be avoided. The risk of failure of the read/write circuit 400 due to high temperature or damage to the micro-region is reduced.

In the three-dimensional storage array 100 of some of the above embodiments, the distribution of the plurality of storage cells 101 and their corresponding reference cells 104 in a three-dimensional space (for example, a three-dimensional space constructed with the X-axis, the Y-axis and the Z-axis as the three-dimensional coordinate axes) There can be many.

In an example, as shown in FIGS. 10A to 10C , in the three-dimensional memory array 100 , a plurality of word lines 103 and a plurality of bit lines 102 are cross-insulated and distributed, for example, the plurality of word lines 103 are distributed along a first horizontal direction ( The X direction) is distributed in parallel, and the plurality of bit lines 102 are distributed perpendicular to the first substrate 300 along the vertical direction (Z direction). Each memory cell 101 is convexly disposed on the surface of the corresponding reference cell 104 facing away from the first substrate 300 , and is located between the corresponding word line 103 and the bit line 102 along the first horizontal direction (X direction). The initial electric domain polarization direction in the memory cell 101 and the reference cell 104 is the second horizontal direction (Y direction), eg, horizontally to the left. After the domain polarization of the memory cell 101 is reversed under the action of the electric field provided by the corresponding word line 103 and the bit line 102, its domain polarization direction is the opposite direction, for example, horizontally to the right. shown in Figure 10D. One end of the plurality of bit lines 102 facing away from the first substrate 300 is coupled to the bit layer 106 , and the bit layer 106 can also be regarded as an extension of the plurality of bit lines 102 . The material of the bit layer 106 is the same as the material of the plurality of bit lines 102 , and the bit layer 106 is a patterned electrode layer. For example, as shown in FIG. 10A , the bit layer 106 includes a plurality of bit lines distributed in parallel along the second horizontal direction (Y direction), and each bit line is respectively coupled to a plurality of bit lines 102 located in the same direction. The three-dimensional memory array 100 also includes a first interconnect layer 107 on the surface of the bit layer 106 facing away from the first substrate 300 . The first interconnect layer 107 is located between the bit layer 106 and the first dielectric layer 202 . The first interconnection layer 107 is provided with third via holes H3 corresponding to the first surface electrodes 201 one-to-one, and first connection lines 108 filled in the third via holes H3. The first interconnection layer 107 is made of insulating material.

In the process of preparing the three-dimensional memory array 100 as above, the first substrate 300 is first provided. The insulating layer 105 and the first layer of ferroelectric thin film are prepared in sequence on the first substrate 300 , and the first layer of ferroelectric thin film is patterned to obtain the reference cell 104 and the memory cell 101 located on the reference cell 104 . Then, word lines 103 corresponding to the memory cells 101 and insulating layers 105 covering the word lines 103 and the memory cells 101 are prepared. And, the above process is repeated until the stacking of each memory cell 101 is completed. After that, dig holes on the side of each memory cell 101 away from the corresponding word line 103 to the surface of the reference cell 104 in the first layer of ferroelectric thin film, and prepare the bit line 102 and the bit layer 106 filled in the hole . Finally, a first interconnect layer 107 is prepared on the surface of the bit layer 106 , and a plurality of third via holes H3 are formed in the first interconnect layer 107 , wherein a part of the third via holes H3 extend to the corresponding word lines 103 s surface. The number of the third via holes H3 is the same as the number of the first surface electrodes 201 , and the first connection lines 108 are formed in each of the third via holes H3 . A part of the first connection lines 108 are coupled to the plurality of bit lines 102 through the bit layer 106 , and another part of the first connection lines 108 are coupled to the plurality of word lines 103 .

In another example, please refer to FIGS. 11A to 11C ″, in the three-dimensional memory array 100 , a plurality of word lines 103 and a plurality of bit lines 102 are cross-insulated and distributed, for example: a plurality of word lines 103 and a plurality of bit lines 102 are respectively located in different layers, a plurality of word lines 103 are distributed in parallel along the second horizontal direction (Y direction), and a plurality of bit lines 102 are distributed in parallel along the first horizontal direction (X direction). Each memory cell 101 is associated with a corresponding reference cell 104 are juxtaposed along the first horizontal direction (X direction), and each memory cell 101 is located between the corresponding word line 103 and the bit line 102 along the vertical direction (Z direction).

In a possible implementation manner, as shown in FIGS. 11B to 11C and FIGS. 11B′ to 11C′, in any two adjacent ferroelectric films, the

memory cells

101 and 101 in the upper ferroelectric film Opposing memory cells 101 in the underlying ferroelectric thin film may be directly coupled through word lines 103 or bit lines 102 . In this way, the word line 103 or the bit line 102 located between any two adjacent ferroelectric thin films can respectively provide voltage signals to the memory cells 101 on both sides thereof.

On this basis, optionally, the initial domain polarization directions of any two adjacent ferroelectric thin films are the same. For example, as shown in FIGS. 11B to 11C , the initial domain polarization directions in the memory cell 101 and the reference cell 104 in each layer of ferroelectric thin film are vertical direction (Z direction), for example, vertically upward. After the domain polarization of the memory cell 101 is reversed under the action of the electric field provided by the corresponding word line 103 and the bit line 102 , the direction of the domain polarization of the memory cell 101 is the opposite direction, for example, vertically downward. Here, the voltage signals provided by the word line 103 and the bit line 102 can be selected and set according to actual requirements, so as to control the electric domain polarization inversion of the corresponding memory cell 101 . For example, in the case where the memory cells 101 in the lower ferroelectric film and the upper ferroelectric film are coupled through the bit line 102, the word line 103 under the lower ferroelectric film and the word line 103 over the upper ferroelectric film respectively provide different voltage signal. In the case where the memory cells 101 in the lower ferroelectric film and the upper ferroelectric film are coupled through word lines 103, the bit lines 102 under the lower ferroelectric film and the bit lines 102 above the upper ferroelectric film respectively provide different voltage signals .

Optionally, the initial electric domain polarization directions of any two adjacent ferroelectric thin films are opposite. Referring to FIGS. 11B' to 11C', in any two adjacent ferroelectric films, the initial domain polarization directions in the lower ferroelectric film and the upper ferroelectric film are different, for example, the initial domain polarization of the lower ferroelectric film The polarization direction is vertical upward, and the initial domain polarization direction of the upper ferroelectric film is vertical downward. In this way, in the case where the memory cells 101 in the lower ferroelectric film and the upper ferroelectric film are coupled through the bit line 102, the word line 103 below the lower ferroelectric film and the word line 103 above the upper ferroelectric film provide the same voltage The signal can make the memory cells 101 in the lower ferroelectric thin film and the upper ferroelectric thin film realize electric domain polarization inversion. Similarly, in the case where the memory cells 101 in the lower ferroelectric film and the upper ferroelectric film are coupled through the word line 103, the bit line 102 under the lower ferroelectric film and the bit line 102 above the upper ferroelectric film provide the same The voltage signal can make the memory cells 101 in the lower ferroelectric thin film and the upper ferroelectric thin film realize electric domain polarization inversion.

In addition, the three-dimensional memory array 100 further includes a first interconnection layer 107 covering the plurality of word lines 103 and the plurality of bit lines 102 . The first interconnection layer 107 is formed by using an insulating material, and the first interconnection layer 107 is provided with third via holes H3 corresponding to the first surface electrodes 201 one-to-one. The three-dimensional memory array 100 further includes a first connection line 108 formed in each third via hole H3; wherein a part of the first connection line 108 is coupled with the plurality of bit lines 102, and another part of the first connection line 108 is connected with A plurality of word lines 103 are coupled.

In the process of preparing the three-dimensional memory array 100 as above, the first substrate 300 is first provided. A plurality of word lines 130 and insulating layers 105 are sequentially prepared on the first substrate 300 . The insulating layers 105 do not cover the top surfaces of the word lines 103 , that is, the top surfaces of the word lines 103 are exposed. A first layer of ferroelectric thin film and a plurality of bit lines 102 are sequentially stacked on the surface of the insulating layer 105 and the plurality of word lines 103, wherein the extension direction of the bit lines 102 and the extension direction of the word lines 103 intersect, eg, perpendicular. The first layer of the ferroelectric thin film includes a plurality of reference cells 104 and memory cells 101 located beside the reference cells 104, wherein the part of the ferroelectric thin film located in the intersection area of the corresponding word line 103 and the bit line 102 is the memory cell 101, and the iron The portion of the electrical thin film outside the intersection area of the corresponding word line 103 and the bit line 102 is the reference cell 104 . Then, an insulating layer 105 , a second layer of ferroelectric thin film and a plurality of word lines 103 are sequentially laminated on the surfaces of the plurality of bit lines 102 , wherein the insulating layer 105 does not cover the top surfaces of the plurality of bit lines 102 . And so on, until the stacking of the memory cells 101 is completed. In addition, the above-mentioned multiple word lines 103 and multiple bit lines 102 can be respectively drawn out to the edge of the three-dimensional memory array 100 along their extending directions, so as to realize their corresponding coupling with the subsequent first connection lines 108 . After that, a first interconnection layer 107 is formed on the surface of the outermost word lines 103 by using an insulating material, and a plurality of third via holes H3 are formed in the first interconnection layer 107 , wherein a part of the third via holes H3 extends to the surface of the corresponding bit line 102 . The number of the third via holes H3 is the same as the number of the first surface electrodes 201 , and the first connection lines 108 are formed in each of the third via holes H3 , wherein a part of the first connection lines 108 are coupled to the plurality of word lines 103 , and another part of the first connection line 108 is coupled to the plurality of bit lines 102 .

In another possible implementation manner, as shown in FIGS. 11B ″ to 11C ″, in any two ferroelectric thin films disposed adjacently, the memory cell 101 in the upper ferroelectric thin film and the lower ferroelectric thin film Insulation isolation between the opposite memory cells 101 . That is, an entire insulating layer 105 is provided between any two adjacent ferroelectric thin films. In this way, the initial domain polarization directions in each ferroelectric thin film can be the same. The domain polarization of the memory cell 101 in each ferroelectric thin film is independently controlled by its corresponding word line 103 and bit line 102 .

Here, the preparation method of the three-dimensional memory array 100 can be carried out with reference to the relevant contents in the foregoing embodiments, for example, the preparation of the insulating layer 105 may be added in the corresponding process according to its structure.

In another example, please refer to FIGS. 12A to 12C , the three-dimensional memory array 100 includes a first substrate 300 , an insulating layer 105 and a ferroelectric block 10 having a certain thickness stacked on the first substrate 300 in sequence. A plurality of long grooves are formed in the ferroelectric block 10 by digging holes, and the longitudinal direction of the long grooves is, for example, the Z direction or the X direction. A part of the long trench is filled with conductive material to form a plurality of bit lines 102 . By alternately stacking conductive material and insulating material in another part of the long groove, an insulating layer 105 located between a plurality of word lines 103 and any two word lines 103 in different layers can be formed. In this way, the part of the ferroelectric block 10 located in any intersection area of each word line 103 and the corresponding bit line 102 is the memory cell 101, and the part located outside the intersection area of each word line 103 and the corresponding bit line 102 is the reference unit 104. Optionally, the bit line 102 extends along the Z direction, and the word line 103 extends along the X direction. The initial domain polarization direction in the memory cell 101 and the reference cell 104 is the second horizontal direction (Y direction), eg, horizontally to the left. After the domain polarization of the memory cell 101 is reversed under the action of the electric field provided by the corresponding word line 103 and the bit line 102, its domain polarization direction is the opposite direction, for example, horizontally to the right. shown in Figure 12D.

Please continue to refer to FIG. 12C , the three-dimensional memory array 100 further includes a bit layer 106 . The bit layer 106 is coupled to one end of the plurality of bit lines 102 facing away from the first substrate 300 , and the bit layer 106 can also be regarded as an extension of the plurality of bit lines 102 . The material of the bit layer 106 is the same as the material of the plurality of bit lines 102 , and the bit layer 106 is a patterned electrode layer. The three-dimensional memory array 100 also includes a first interconnect layer 107 on the surface of the bit layer 106 facing away from the first substrate 300 . The first interconnect layer 107 is located between the bit layer 106 and the first dielectric layer 202 . The first interconnection layer 107 is provided with third via holes H3 corresponding to the first surface electrodes 201 one-to-one, and first connection lines 108 filled in the third via holes H3. The first interconnection layer 107 is made of insulating material, and a part of the third via hole H3 extends to the surface of the corresponding word line 103 . In this way, a part of the first connection lines 108 are respectively coupled to the plurality of word lines 103 , and another part of the first connection lines 108 are coupled to the plurality of bit lines 102 through the bit layer 106 .

In addition, optionally, as shown in FIG. 12E , the three-dimensional memory array 100 is directly fabricated in the ferroelectric block 10 . That is, the first substrate 300 and the insulating layer 105 between the first substrate 300 and the ferroelectric block 10 need not be disposed in the three-dimensional memory array 100 .

It can be seen that in some of the above examples, the ferroelectric thin film stacking process is not used to prepare the three-dimensional memory array 100, but the ferroelectric block 10 is prepared on the first substrate 300, and the ferroelectric block 10 is formed by digging holes and filling. A plurality of word lines 103 and a plurality of bit lines 102 are formed directly in the ferroelectric block 10 by means of digging and filling, thereby completing the preparation of the three-dimensional memory array 100 .

The structure of the three-dimensional memory array 100 and the manufacturing method thereof are not limited to those described in the above examples, and variations or substitutions can be easily conceived, which should all fall within the protection scope of the present disclosure. For example, please refer to FIG. 13 . In this example, the structure of one storage unit 101 is used as an example for description. The word line 103 corresponding to the memory cell 101 extends in the X direction, and the bit line 102 corresponding to the memory cell 101 extends in the Z direction. If the orthographic projections of the word line 103 and the bit line 102 corresponding to the same memory cell 101 on the X-Z plane do not overlap 13, the memory cell 101 between the word line 103 and the bit line 102 is, for example, a triangular prism; or for example, the interface between the memory cell 101 and the reference cell 104 is a curved surface.

In the second chip 1002 of some of the above-mentioned embodiments, the structure of the read/write circuit 400 may be various. The following description will be given by taking an example that the read/write circuit 400 has the structure shown in FIG. 3 .

Illustratively, as shown in FIG. 3, the data input and output buffer 402, the address register 403, the control logic circuit 404, the row decoder 405, the column decoder 406, the sense amplifier 407 or the high voltage in the read and write circuit 400 The electrical devices such as the charge pump 408 employ integrated circuits. In this way, the basic constituent units in the read/write circuit 400 may be electrical devices with the same or similar characteristics, such as field effect transistors (MOS) or thin film transistors (TFT). That is to say, the read/write circuit 401 may be composed of electronic devices such as multiple field effect transistors and/or at least one capacitor. Here, the field effect transistor can also be replaced by a thin film transistor or other devices with the same characteristics. In addition, the read-write circuit 400 may also include any active or passive components (eg, transistors, diodes, resistors or capacitors) required for connection between the various electrical devices.

By way of example, please understand with reference to FIG. 2 and FIG. 14 , the read/write circuit 400 includes a plurality of Complementary Metal Oxide Semiconductor (Complementary Metal Oxide Semiconductor, CMOS for short). CMOS is composed of p-MOS and n-MOS, and its static power consumption is very small, which is beneficial to reduce the overall power consumption of the read-write circuit 400 .

In some embodiments, please continue to refer to FIG. 2 and FIG. 14 , the second substrate 600 is a polysilicon (p-Si) substrate. The p-MOS and the n-MOS are respectively formed on the surface of the second substrate 600, and an isolation barrier 610 is provided between any two adjacent MOSs. The surfaces of the p-MOS and the n-MOS are sequentially laminated with an insulating layer 620 and a first metal pattern 701 . The first metal pattern 701 includes a plurality of electrode blocks and/or a plurality of signal lines. The electrode block or signal line is coupled to the corresponding p-MOS or n-MOS through the via hole in the insulating layer 620, for example, to the input/output electrode 410 in the p-MOS, or to the input/output electrode 410 in the n-MOS. The input/output electrodes are coupled. In this embodiment, a schematic illustration is given by taking the adjacent arrangement of p-MOS and n-MOS as an example, but this description is not regarded as a limitation on the connection relationship between p-MOS and n-MOS in CMOS. In addition, the embodiment of the present disclosure does not limit the connection relationship between the MOSs.

Please continue to refer to FIG. 2 and FIG. 14 , an insulating layer 621 , a second metal pattern 702 and an insulating layer 622 are stacked on the side of the first metal pattern 701 away from the second substrate 600 in sequence. The second metal pattern 702 includes a plurality of electrode blocks and/or a plurality of signal lines. The electrode blocks or signal lines pass through the via holes in the insulating layer 621 and are correspondingly coupled to the electrode blocks or signal lines in the first metal pattern 701 , which facilitates the design of circuit switching and wiring in the read-write circuit 400 . Optionally, the second metal pattern 702 includes the input/output terminal 401 in some of the foregoing embodiments.

It can be understood that, according to the structure of each electrical device in the read-write circuit 400 and the connection relationship between them, the number of layers of the metal pattern disposed on the side of the first metal pattern 701 away from the second substrate 600 can also be more. layer, which is not limited in this embodiment of the present disclosure.

Exemplarily, an insulating layer 623 and a third metal pattern 703 are stacked on the side of the second metal pattern 702 away from the second substrate 600 in sequence. The third metal pattern 703 includes a plurality of electrode blocks and/or a plurality of signal lines. The electrode blocks or signal lines pass through the via holes in the insulating layer 623 and are correspondingly coupled to the electrode blocks or signal lines in the second metal pattern 702 . The plurality of electrode blocks in the third metal pattern 703 include the second surface electrodes 501 in some of the foregoing embodiments, and the plurality of signal lines include second connection lines 503 configured to connect the second surface electrodes 501 and the input/output terminals 401 . On this basis, optionally, as shown in FIG. 14 , a diffusion barrier layer 630 is further disposed between the third metal pattern 703 and the second metal pattern 702 . The diffusion barrier layer 630 is located between the insulating layer 623 and the second metal pattern 702 , and the diffusion barrier layer 630 has a plurality of via holes at the same positions as the via holes in the insulating layer 623 . The diffusion barrier layer 630 is made of inorganic insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride.

In some embodiments, the read/write circuit 400 also typically includes a plurality of signal lines (not shown in the figure) configured to transmit information, such as control information, data information, and the like, to the CMOS or other electronic devices. The signal line can be arranged in the same layer as any of the above-mentioned metal patterns, or arranged in the same layer as a certain metal electrode in CMOS. Here, the arrangement on the same layer means that the same material is used for forming in the same patterning process. The patterning process generally refers to a process for forming a predetermined pattern, such as a photolithography process. The structure of the CMOS and its arrangement position in FIG. 2 are only exemplary expressions of the cross-section of the second chip 1002 in a certain direction. In the second chip 1002, the connection relationship between multiple CMOSs, and the connection relationship between each of the p-MOS or n-MOS in each CMOS and the corresponding signal lines, etc. are not clearly shown, and the settings can be selected according to actual needs. Can.

It should be added that, in some of the drawings involved in the above-mentioned embodiments, some insulating films are illustrated or omitted to be transparent, in order to more clearly reflect the positional relationship between other films, rather than for the three-dimensional memory 1000 . Structural restrictions.

Based on the three-dimensional memory 1000 in some of the above embodiments, some embodiments of the present disclosure provide a method for preparing a three-dimensional memory. Please understand with reference to FIG. 1 , FIG. 7 , FIG. 8 and FIG. 9 , the preparation method of the three-dimensional memory includes S100 to S300 .

S100, a first chip 1001 is provided. The first chip 1001 includes the three-dimensional memory array 100 and the first bonding layer 200 . The first bonding layer 200 includes a plurality of first surface electrodes 201 correspondingly coupled to the three-dimensional memory array 100 .

Here, for the structures of the three-dimensional memory array 100 and the first bonding layer 200, reference may be made to the relevant descriptions in some of the foregoing embodiments.

In some examples, as shown in FIG. 1 , the first bonding layer 200 further includes a first dielectric layer 202 . There are various methods for preparing the first chip 1001 .

In a possible implementation manner, as shown in FIG. 7 , the method for preparing the first chip 1001 provided in S100 includes S101 to S103 .

S101, a three-dimensional storage array 100 is prepared. A first dielectric layer 202 is prepared on one side surface of the three-dimensional memory array 100 .

S102 , forming a plurality of first via holes H1 in the first dielectric layer 202 .

S103 , first surface electrodes 201 are respectively prepared in the plurality of first via holes H1 , so that the plurality of first surface electrodes 201 are correspondingly coupled to the three-dimensional memory array 100 .

In yet another possible implementation manner, as shown in FIG. 8 , the three-dimensional memory 1000 further includes a first substrate 300 , and the three-dimensional memory array 100 is fabricated on the first substrate 300 . The first bonding layer 200 also includes a first dielectric layer 202 . The first dielectric layer 202 is located on a side of the three-dimensional memory array 100 facing away from the first substrate 300 .

As shown in FIG. 9 , the preparation method of the first chip 1001 provided in S100 includes S101' to S104'.

S101', a first substrate 300 is provided, and a three-dimensional memory array 100 and a first dielectric layer 202 are prepared by lamination on one surface of the first substrate 300.

Here, the first substrate 300 serves as a carrier of the three-dimensional memory array 100 . For example, the first substrate 300 is a ferroelectric single crystal wafer. The first dielectric layer 202 is made of common insulating material, such as insulating resin.

S102', forming a plurality of first via holes H1 in the first dielectric layer 202.

S103', depositing a first metal film 2010, so that a portion of the first metal film 2010 located in the first via hole H1 is correspondingly coupled to the three-dimensional memory array 100.

Here, the first metal film 2010 at least partially covers the surface of the first dielectric layer 202 facing away from the three-dimensional memory array 100 .

S104', removing the part of the first metal thin film 2010 outside the first via hole H1, and polishing the surface of the first dielectric layer 202 away from the three-dimensional memory array 100. The metal portion exposed in the first via hole H1 in this way is the first surface electrode 201 . Thus, the first chip 1001 is obtained.

In some of the above-mentioned embodiments, the structures of the three-dimensional memory array 100 are different, and the corresponding fabrication processes thereof are different. According to different structures of the three-dimensional memory array 100 , the corresponding preparation processes have been described in some of the foregoing embodiments, and will not be repeated here. In addition, the first via hole H1 may be formed by an etching process, such as a dry etching process or a wet etching process; but not limited thereto.

In some of the above embodiments, the plurality of first surface electrodes 201 are correspondingly coupled to the three-dimensional memory array 100 , which means that each first surface electrode 201 in the plurality of first surface electrodes 201 is connected to a word in the three-dimensional memory array 100 The line 103 or a bit line 102 is correspondingly coupled.

S200, the second chip 1002 is provided. The second chip 1002 includes a read-write circuit 400 and a second bonding layer 500 , and the second bonding layer 500 includes a plurality of second surface electrodes 501 correspondingly coupled to the read-write circuit 400 .

Here, for the structures of the read-write circuit 400 and the second bonding layer 500, reference may be made to the relevant descriptions in the foregoing embodiments.

In some examples, as shown in FIG. 1 , the second bonding layer 500 further includes a second dielectric layer 502 . There are various methods for preparing the second chip 1002 .

In a possible implementation manner, as shown in FIG. 7 , the method for preparing the second chip 1002 provided in S200 includes S201 to S203.

S201, a read-write circuit 400 is prepared. A second dielectric layer 502 is prepared on one side surface of the read-write circuit 400 .

S202 , forming a plurality of second via holes H2 in the second dielectric layer 502 .

S203 , preparing second surface electrodes 501 in the plurality of second via holes H2 respectively, so that the plurality of second surface electrodes 501 are correspondingly coupled to the read-write circuit 400 .

In yet another possible implementation manner, as shown in FIG. 8 , the three-dimensional memory 1000 further includes a second substrate 600 on which the read-write circuit 400 is fabricated. The second bonding layer 500 also includes a second dielectric layer 502 . The second dielectric layer 502 is located on the side of the read/write circuit 400 facing away from the second substrate 600 .

As shown in FIG. 9 , the preparation method of the second chip 1002 provided in S200 includes S201' to S204'.

S201', a second substrate 600 is provided, and a read-write circuit 400 and a second dielectric layer 502 are prepared by lamination on one surface of the second substrate 600.

Here, the second substrate 600 is used as a carrier of the read-write circuit 400, and its preparation materials include but are not limited to monocrystalline silicon, polycrystalline silicon, lithium tantalate LiTaO3 and lithium niobate LiNbO3. The second dielectric layer 502 is formed by using common insulating materials, such as insulating resin.

S202', forming a plurality of second via holes H2 in the second dielectric layer 502.

S203', depositing a second metal film 5010, so that the part of the second metal film 5010 located in the second via hole H2 is correspondingly coupled to the read-write circuit 400.

Here, the second metal film 5010 at least partially covers the surface of the second dielectric layer 502 facing away from the read-write circuit 400 .

S204', removing the part of the second metal film 5010 outside the second via hole H2, and polishing the surface of the second dielectric layer 502 away from the read-write circuit 400. The metal portion exposed in the second via hole H2 in this way is the second surface electrode 501 . Thus, the second chip 1002 is obtained.

In some of the above-mentioned embodiments, the structure of the read-write circuit 400 is different, and the corresponding preparation process thereof is slightly different. This embodiment of the present disclosure does not limit this. In addition, the second via hole H2 may be formed by an etching process, such as a dry etching process or a wet etching process.

In some of the above-mentioned embodiments, the plurality of second surface electrodes 501 are in one-to-one correspondence with the plurality of first surface electrodes 201 described above. The plurality of second surface electrodes 501 are correspondingly coupled to the read-write circuits 400 , and it is shown that each read-write circuit 401 is correspondingly coupled to at least two second surface electrodes 501 .

S300, bonding the first bonding layer 200 in the first chip 1001 with the second bonding layer 500 in the second chip 1002, so that the plurality of first surface electrodes 201 correspond to the plurality of second surface electrodes 501 one-to-one the coupling.

For the structures of the first bonding layer 200 and the second bonding layer 500, reference may be made to the relevant descriptions in some of the foregoing embodiments.

In some examples, the surfaces of the plurality of first surface electrodes 201 and the first dielectric layer 202 close to the second bonding layer 500 are located on the same plane. The surfaces of the plurality of second surface electrodes 501 and the second dielectric layers 502 close to the first bonding layer 200 are located on the same plane. In S300, bonding the first bonding layer 200 and the second bonding layer 500 includes: mixing the first bonding layer 200 and the second bonding layer 500 to bond.

In the preparation methods of some of the above embodiments, the preparation of S100 and S200 is not limited in order, and can be performed simultaneously. In this way, the manufacturing process flow of the first chip 1001 and the second chip 1002 can be performed separately. In this way, the first chip 1001 and the second chip 1002 can be fabricated at the same time, thereby effectively shortening the production cycle of the three-dimensional memory 1000 . In addition, the preparation of the first chip 1001 is performed on its independent production line, which can avoid adverse effects of other production materials on the production line, such as the problem of cross-contamination of production materials caused by shared production lines.

Some embodiments of the present disclosure provide an electronic device, such as a data storage device, a photocopier, a network device, a household appliance, an instrument, a mobile phone, a computer, and other devices with a data storage function. For example, as shown in FIG. 15 , the electronic device 1 includes a casing 11 , a circuit board 12 disposed in the casing 11 , and a memory integrated on the circuit board 12 . The memory may be the three-dimensional memory 1000 in some of the above embodiments. The electronic device 1 may further include other necessary elements or components, which are not limited in this embodiment of the present disclosure.

Optionally, external control devices such as processors or actuators coupled to the read/write circuit 400 in the three-dimensional memory 1000 in the foregoing embodiments may also be integrated on the circuit board 12 . For example, the electronic device 1 also includes a processor 409 integrated on the circuit board 12 . The processor 409 is coupled to the read-write circuit 400 , and the processor 409 can control the read-write operation of the three-dimensional memory array 100 through the read-write circuit 400 .

In some embodiments of the present disclosure, the electronic device 1 adopts the three-dimensional memory 1000, which can have better data storage capability. In addition, the three-dimensional memory 1000 is fabricated by using the structures and preparation methods in the above-mentioned embodiments, and can have high reliability in use, thereby ensuring that the electronic device 1 has high reliability in use.

In the foregoing description of the embodiments, the particular features, structures, materials or characteristics may be combined in any suitable manner in any one or more of the embodiments or examples.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited to this. should be included within the scope of protection of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

A three-dimensional memory includes: a first chip and a second chip; the first chip includes a three-dimensional memory array and a first bonding layer; the second chip includes a read-write circuit and a second bonding layer;

The first bonding layer is located on the side of the three-dimensional storage array close to the read-write circuit; the first bonding layer includes a plurality of first surface electrodes correspondingly coupled to the three-dimensional storage array;

The second bonding layer is located on the side of the read-write circuit close to the three-dimensional storage array; the second bonding layer includes a plurality of second surface electrodes correspondingly coupled to the read-write circuit;

The plurality of first surface electrodes are coupled to the plurality of second surface electrodes in a one-to-one correspondence.
The three-dimensional memory of claim 1, wherein the first bonding layer further comprises a first dielectric layer having a plurality of first vias; the second bonding layer further comprises a plurality of second vias a second dielectric layer of the hole;

The plurality of first surface electrodes are located in the plurality of first via holes in a one-to-one correspondence, and both the plurality of first surface electrodes and the first dielectric layer are close to the second bonding layer the surfaces lie in the same plane;

The plurality of second surface electrodes are located in the plurality of second via holes in a one-to-one correspondence, and both the plurality of second surface electrodes and the second dielectric layer are close to the first bonding layer the surfaces lie in the same plane;

The bonding mode of the first bonding layer and the second bonding layer is hybrid bonding.
The three-dimensional memory of claim 2, wherein the material of at least one of the first dielectric layer and the second dielectric layer comprises: silicon oxide, silicon nitride, benzocyclobutene, tantalic acid Lithium or lithium niobate.
The three-dimensional memory according to any one of claims 1 to 3, wherein the first chip further comprises a first substrate;

The three-dimensional memory array is disposed on the first substrate; and the first bonding layer is located on a surface of the three-dimensional memory array facing away from the first substrate.
The three-dimensional memory according to claim 4, wherein the material of the first substrate comprises: ferroelectric single crystal material or single crystal silicon;

The ferroelectric single crystal material includes: lithium tantalate, lithium niobate, lithium tantalate, lithium niobate, blackened lithium tantalate or lithium niobate, or dopant selected from magnesium oxide, Lithium tantalate or lithium niobate of at least one of manganese pentoxide, iron oxide or lanthanum oxide.
The three-dimensional memory according to any one of claims 1 to 3, wherein the second chip further comprises a second substrate;

The read-write circuit is arranged on the second substrate; the second bonding layer is located on the surface of the read-write circuit that is away from the second substrate.
The three-dimensional memory according to claim 1, wherein the materials of the plurality of first surface electrodes and/or the plurality of second surface electrodes include: iridium, platinum, tungsten, nickel, cobalt, copper, aluminum, At least one of polysilicon, silicon-doped metal, or metal silicide.
The three-dimensional memory according to any one of claims 1 to 7, wherein the three-dimensional memory array comprises: a plurality of bit lines, a plurality of word lines, and a plurality of memory cells distributed in an array in a three-dimensional space;

One end of each memory cell in the plurality of memory cells is coupled to a word line, and the other end of the word line is coupled to a first surface electrode; the other end is coupled to a bit line, and the other end of the bit line is coupled to a first surface electrode;

In addition, any two adjacent memory cells are insulated; the two first surface electrodes respectively coupled to the word line and the bit line coupled to the same memory cell are different.
The three-dimensional memory according to claim 8, wherein the three-dimensional memory array further comprises a plurality of reference cells; wherein each memory cell is further connected to at least one reference cell among the plurality of reference cells, the The orthographic projection of at least one reference cell on the first bonding layer is located outside the orthographic projection of at least one of the word line and the bit line on the first bonding layer.
The three-dimensional memory according to claim 9, wherein the materials of the storage unit and the reference unit are both ferroelectric materials; the storage unit and the reference unit connected thereto are integrally formed.
A preparation method of a three-dimensional memory, used for preparing the three-dimensional memory according to any one of claims 1 to 10; the preparation method of the three-dimensional memory comprises:

A first chip is provided; the first chip includes a three-dimensional storage array and a first bonding layer, the first bonding layer includes a plurality of first surface electrodes correspondingly coupled to the three-dimensional storage array;

A second chip is provided; the second chip includes a read-write circuit and a second bonding layer, the second bonding layer includes a plurality of second surface electrodes correspondingly coupled to the read-write circuit;

bonding the first bonding layer in the first chip with the second bonding layer in the second chip, so that the plurality of first surface electrodes and the plurality of second surface electrodes correspond one-to-one ground coupling.
The method for preparing a three-dimensional memory according to claim 11, wherein the method for preparing the first chip comprises:

preparing the three-dimensional storage array;

preparing a first dielectric layer on one side surface of the three-dimensional memory array;

forming a plurality of first vias in the first dielectric layer;

First surface electrodes are respectively prepared in the plurality of first via holes, so that the plurality of first surface electrodes are correspondingly coupled to the three-dimensional memory array.
The method for preparing a three-dimensional memory according to claim 11, wherein the method for preparing the first chip comprises:

a first substrate is provided, and the three-dimensional memory array and the first dielectric layer are prepared by lamination on one surface of the first substrate;

forming a plurality of first vias in the first dielectric layer;

depositing a first metal thin film, so that a portion of the first metal thin film located in the first via hole is correspondingly coupled to the three-dimensional memory array;

removing the portion of the first metal film outside the first via hole, and polishing the surface of the first dielectric layer away from the three-dimensional memory array; the metal portion exposed in the first via hole is the first surface electrode.
The method for preparing a three-dimensional memory according to claim 11, wherein the method for preparing the second chip comprises:

preparing the read-write circuit;

preparing a second dielectric layer on one side surface of the read-write circuit;

forming a plurality of second vias in the second dielectric layer;

Second surface electrodes are respectively prepared in the plurality of second via holes, so that the plurality of second surface electrodes are correspondingly coupled to the read-write circuit.
The method for preparing a three-dimensional memory according to claim 11, wherein the method for preparing the second chip comprises:

a second substrate is provided, and the read-write circuit and the second dielectric layer are prepared by lamination on one surface of the second substrate;

forming a plurality of second vias in the second dielectric layer;

depositing a second metal film, so that the part of the second metal film located in the second via hole is correspondingly coupled to the read-write circuit;

removing the part of the second metal film outside the second via hole, and polishing the surface of the second dielectric layer away from the read-write circuit; the metal part exposed in the second via hole is the second surface electrode.
The method for manufacturing a three-dimensional memory according to any one of claims 11 to 15, wherein the first bonding layer further comprises a first dielectric layer; the plurality of first surface electrodes and the first dielectric layer The surfaces of the two electrical layers close to the second bonding layer are located on the same plane; the second bonding layer further includes a second dielectric layer; the plurality of second surface electrodes and the second dielectric layer are two The surfaces close to the first bonding layer are located in the same plane;

Bonding the first bonding layer with the second bonding layer includes: mixing the first bonding layer with the second bonding layer.
An electronic device includes a circuit board and a memory coupled with the circuit board; the memory comprises the three-dimensional memory according to any one of claims 1-10.