WO2022110218A1 - Ferroelectric random access memory and electronic device - Google Patents

Abstract

A ferroelectric random access memory (FRAM) (1) and an electronic device, the FRAM (1) comprising: at least one storage unit (10); the storage units (10) each comprise: an outer side electrode (101), a center electrode (102), and a ferroelectric structure (103); the ferroelectric structures (103) each comprise: a ferroelectric material, and a through hole (U) which penetrates the ferroelectric material in a first direction (F1); the center electrodes (102) are strip-shaped structures located in the through holes (U); the outer side electrodes (101) surround a portion of the ferroelectric structures (103); and an initial electrical polarization direction (T) of the ferroelectric structures (103) is any direction that is parallel to the first plane, the first plane being a plane that is perpendicular to the first direction (F1) and that passes through the outer side electrode (101). In the FRAM (1), the outer side electrodes (101) are provided surrounding a portion of the ferroelectric structures (103) and the center electrodes (102) are located within the through holes (U) of the ferroelectric structures (103). When manufacturing the FRAM (1), the initial electric polarization direction (T) of the ferroelectric structures (103) only needs to be parallel to a first plane, precisely designing and calculating the polarization direction and micro-nano machining direction of ferroelectric materials are not required, machining precision requirements are low, and manufacturing process difficulty is relatively low.

Description

A ferroelectric memory and electronic equipment technical field

The present application relates to the technical field of data storage, and in particular, to a ferroelectric memory and an electronic device.

Background technique

With the continuous development of information technology, from the transmission of simple digital sequences to today's big data era, it is inseparable from the storage of massive data, and even more inseparable from the rapid development of memory data.

Ferroelectric random access memory (FRAM) stores data based on the ferroelectric effect of ferroelectric materials. Ferroelectric materials refer to substances that can spontaneously polarize crystals within a certain temperature range. Since the positive and negative centers in the lattice of ferroelectric materials do not overlap, each unit cell has an electric dipole moment, and the unit cells are arranged periodically. Constitutes the initial polarization direction of the ferroelectric material. The polarization direction and polarization intensity of ferroelectric materials can be adjusted by an applied electric field. Specifically, when the initial polarization direction of the ferroelectric material is reversed, there is a domain wall between the reversed region and the unreversed region, and when the polarization directions of the reversed region and the unreversed region are opposite, the domain wall is opened, which is conductive When the polarization direction of the reversed region and the uninverted region is the same, the domain wall is closed, and it is an insulating state, that is, a high-resistance state, and the stored "0" is represented by a high-resistance state and a low-resistance state, respectively. , "1" state to realize the data storage function.

However, the initial polarization direction of the ferroelectric material needs to be set parallel to the electric field direction, which makes it necessary to accurately design and calculate the polarization direction of the ferroelectric material and the direction of micro-nano processing during the fabrication of the ferroelectric memory. The production process is more difficult.

SUMMARY OF THE INVENTION

The present application provides a ferroelectric memory and electronic equipment, which are used to reduce the difficulty of the fabrication process of the ferroelectric memory.

In a first aspect, the present application provides a ferroelectric memory, the ferroelectric memory includes at least one storage unit, wherein the storage unit includes: an outer electrode, a center electrode, and a ferroelectric structure; the ferroelectric structure includes: a ferroelectric material, and a through hole penetrating the ferroelectric material in the first direction; the central electrode is a strip-like structure located in the through hole; the outer electrode surrounds part of the ferroelectric structure; the initial electric polarization direction of the ferroelectric structure is any direction parallel to the first plane. In one direction, the first plane is a plane perpendicular to the first direction and passing through the outer electrodes.

In the embodiment of the present application, the outer electrodes are arranged to surround part of the ferroelectric structure, and the central electrode is located in the through hole of the ferroelectric structure. Therefore, the direction of the electric field formed by the outer electrodes and the central electrode is divergent as a whole, so that the electric field There are multiple angles between the direction and the polarization direction of the ferroelectric material. The initial polarization direction of the ferroelectric structure is any direction parallel to the first plane. In this way, in the electric field formed by the outer electrode and the central electrode, there must be an electric field direction (or a component of the electric field direction) and the initial pole of the ferroelectric structure. the opposite direction. Therefore, as long as a sufficiently large voltage is applied to the outer and center electrodes, the resulting electric field can reverse the ferroelectric material in the ferroelectric structure. In this way, in the production process of the ferroelectric memory, as long as the initial polarization direction of the ferroelectric structure is parallel to the first plane, there is no need to accurately design and calculate the polarization direction and micro-nano machining direction of the ferroelectric material, which will affect the machining accuracy. The requirements are lower, the manufacturing process is less difficult, and it is easier to manufacture memory cells with better miniaturization.

In a possible implementation manner, the material of the outer electrode and the center electrode may be the same or different, and optionally, the material of the outer electrode or the center electrode may include: titanium nitride, tungsten, nickel, platinum, titanium, nitride Tungsten, ruthenium, ruthenium oxide, iridium, iridium oxide, tantalum nitride, cobalt, aluminum, copper, polysilicon or a compound of silicon and metal, of course, other materials that can be used as electrodes can also be used for the outer electrode or the center electrode. Do limit. In addition, the above-mentioned ferroelectric materials may include: lithium niobate, blackened lithium niobate, doped lithium niobate, lithium tantalate, blackened lithium tantalate, doped lithium tantalate, bismuth ferrite, barium titanate, titanium Barium strontium acid or strontium titanate, and the ferroelectric material can also be other materials with ferroelectric properties, which are not limited here.

In a possible implementation manner, the outer electrode has two end points on the edge of the first plane, which are the first end point and the second end point respectively; the geometric center of the center electrode is connected to the first end point and the second end point, respectively. Among the included angles between the lines, the included angle toward the outer electrode is less than or equal to 180°. In this way, the phenomenon in which the electric field components cancel each other can be avoided.

In a possible implementation manner, the memory cell may further include: a switch control layer located between the outer electrode and the ferroelectric structure; the switch control layer covers the surface of the outer electrode facing the side of the ferroelectric structure, so that the outer electrode is connected to the ferroelectric structure. The structures are not in direct contact. In specific implementation, when the voltage applied to the switch control layer is greater than the turn-on threshold, the switch control layer is turned on, and when the voltage applied to the switch control layer is less than the turn-on threshold, the switch control layer is turned off, so that the iron can be selected Which storage units in the electric memory are read and written to improve the flexibility of the ferroelectric memory. The switch control layer may include: titanium oxide film, composite film of copper oxide and indium zinc oxide, hafnium oxide film, doped hafnium oxide film, doped nickel oxide film, composite film of tungsten oxide and zinc oxide or tantalum nitride, Composite film of silicon nitride and tantalum nitride.

In a possible implementation manner, the memory cell may further include: a switch control layer located between the outer electrode and the ferroelectric structure; the switch control layer covers the surface of the outer electrode facing the side of the ferroelectric structure, so that the outer electrode is connected to the ferroelectric structure. The structures are not in direct contact. In specific implementation, when the voltage applied to the switch control layer is greater than the turn-on threshold, the switch control layer is turned on, and when the voltage applied to the switch control layer is less than the turn-on threshold, the switch control layer is turned off, so that the iron can be selected Which storage units in the electric memory are read and written to improve the flexibility of the ferroelectric memory. In the ferroelectric structure, a plurality of metal particles are distributed within a set depth from the surface of the ferroelectric structure facing the outer electrode, and a part of the ferroelectric structure having the plurality of metal particles serves as a switch control layer. Optionally, the material of the metal particles may include titanium, chromium, iridium or platinum, and other metal materials may also be used for the metal particles, which are not limited here.

In a possible implementation manner, the memory cell may further include: a switch control layer located between the ferroelectric structure and the center electrode; the switch control layer covers the side surface of the center electrode so that the center electrode and the ferroelectric structure are not in direct contact. In specific implementation, when the voltage applied to the switch control layer is greater than the turn-on threshold, the switch control layer is turned on, and when the voltage applied to the switch control layer is less than the turn-on threshold, the switch control layer is turned off, so that the iron can be selected Which storage units in the electric memory are read and written to improve the flexibility of the ferroelectric memory. The switch control layer includes: titanium oxide film, composite film of copper oxide and indium zinc oxide, hafnium oxide film, doped hafnium oxide film, doped nickel oxide film, composite film of tungsten oxide and zinc oxide or tantalum nitride, nitrogen oxide film Composite film of silicon oxide and tantalum nitride.

In a possible implementation manner, the memory cell may further include: a switch control layer located between the ferroelectric structure and the center electrode; the switch control layer covers the side surface of the center electrode so that the center electrode and the ferroelectric structure are not in direct contact. In specific implementation, when the voltage applied to the switch control layer is greater than the turn-on threshold, the switch control layer is turned on, and when the voltage applied to the switch control layer is less than the turn-on threshold, the switch control layer is turned off, so that the iron can be selected Which storage units in the electric memory are read and written to improve the flexibility of the ferroelectric memory. In the ferroelectric structure, a plurality of metal particles are distributed within a set depth from the surface of the ferroelectric structure toward the center electrode, and a part of the ferroelectric structure with the plurality of metal particles serves as a switch control layer. Optionally, the material of the metal particles may include titanium, chromium, iridium or platinum, and other metal materials may also be used for the metal particles, which are not limited here.

In a possible implementation, the ferroelectric memory includes at least one memory string; the memory string includes a plurality of memory cells arranged in a first direction; the plurality of memory cells in the memory string share a central electrode and a ferroelectric structure , by sharing the center electrode and the ferroelectric structure, the fabrication process of the storage string can be made simpler and the fabrication cost can be saved. The storage string may further include a plurality of insulating isolation layers; the multiple insulating isolation layers and the multiple outer electrodes in the storage string are alternately arranged in the first direction, and the multiple insulating isolation layers and the multiple outer electrodes both surround part of the ferroelectric structure . In this way, the outer electrodes in different memory cells can be insulated from each other, so that different memory cells can be controlled to perform data read and write operations respectively. The material of the insulating isolation layer may include: silicon dioxide, silicon nitride, titanium dioxide, hafnium dioxide, aluminum nitride or aluminum oxide.

In a possible implementation manner, in a memory string, one end of the central electrode is located outside the first outer electrode, and the other end is located outside the last outer electrode. In this way, it can be ensured that each outer electrode has a center electrode at the corresponding position, so that the electric field formed by the center electrode and the outer electrode has a higher electric field component in the first plane, thereby improving the electrical performance of the storage string.

In a possible implementation manner, the ferroelectric memory may further include a plurality of memory strings arranged in a second direction and a third direction; the second direction is perpendicular to the first direction, the third direction is perpendicular to the first direction, The second direction and the third direction are perpendicular to each other. In this way, the ferroelectric memory can be formed into a three-dimensional three-dimensional structure, and the structure of the ferroelectric memory is relatively compact, the density of the memory cells is relatively high, and therefore, the capacity of the ferroelectric memory is relatively large. Multiple memory strings in a ferroelectric memory share a ferroelectric structure. On the one hand, the structure of the ferroelectric memory can be made more compact; on the other hand, the manufacturing process of the ferroelectric memory can be made simpler, and the cost of raw materials and the manufacturing cost can be lower.

In a possible implementation manner, the ferroelectric memory may further include: a plurality of lead-out electrodes; in a row of memory strings arranged in the second direction, the i-th outer electrode in each memory string is connected to the lead-out electrodes; wherein, i takes any positive integer from 1 to N, where N is the number of memory cells in the memory string; at the edge of a row of memory strings arranged in the second direction, a plurality of insulating isolation layers and a plurality of outer electrodes are stacked It is stepped to expose each lead-out electrode. In actual use, a voltage can be applied to the outer electrodes of a row of memory cells arranged in the second direction through the lead-out electrodes, and a voltage can be applied to the central electrodes of a row of memory cells arranged in the first direction through the central electrode Therefore, in the present application, the read and write operations of each memory cell can be controlled separately through each lead electrode and each center electrode.

In a possible implementation manner, the minimum distance between the central electrode and the outer electrodes belonging to the same memory cell is the first distance; the distance between two adjacent rows of memory strings in the third direction is the second distance ; The first distance is smaller than the second distance. For example, the first distance can be set to be less than half of the second distance, so that the crosstalk of the electric field between adjacent memory cells can be prevented, and the electrical performance of the ferroelectric memory can be improved.

In a second aspect, the present application also provides an electronic device, the electronic device may include: any of the above-mentioned ferroelectric memories, and a storage controller; and a storage controller for controlling reading and writing of the ferroelectric memory. Optionally, voltages can be applied to the outer electrodes and the center electrodes in the ferroelectric memory through the memory controller, so as to control the ferroelectric memory to realize read and write operations. The electronic device in this application may be a processor, a computer, a server, or the like.

Description of drawings

FIG. 1a is a schematic structural diagram of a ferroelectric memory provided by an embodiment of the present disclosure applied to an electronic device;

FIG. 1b is a schematic three-dimensional structure diagram of a storage unit in an embodiment of the present application;

Fig. 1c is a schematic cross-sectional view of the plane where the dotted frame W is located in Fig. 1b;

Fig. 1d is another cross-sectional schematic diagram of the plane where the dotted frame W is located in Fig. 1b;

FIG. 2a is a schematic diagram of another three-dimensional structure of a storage unit in an embodiment of the present application;

Figure 2b is a schematic cross-sectional view of the plane where the dotted frame W is located in Figure 2a;

Fig. 2c is another cross-sectional schematic diagram of the plane where the dotted frame W is located in Fig. 2a;

FIG. 3a is another three-dimensional schematic diagram of a storage unit in an embodiment of the present application;

Figure 3b is a schematic cross-sectional view of the plane where the dotted frame W is located in Figure 3a;

Fig. 3c is another cross-sectional schematic diagram of the plane where the dotted frame W is located in Fig. 3a;

3d is a schematic cross-sectional view of the memory cell in the first plane when the included angle α is greater than 180°;

4a and 4b are schematic diagrams of the working principle of the storage unit in the embodiment of the present application;

Fig. 5a is another cross-sectional schematic diagram of the plane where the dotted frame W is located in Fig. 1b;

Fig. 5b is another cross-sectional schematic diagram of the plane where the dotted frame W is located in Fig. 2a;

Fig. 5c is another cross-sectional schematic diagram of the plane where the dotted frame W is located in Fig. 3a;

Figure 5d is a schematic cross-sectional view at the dotted line MM' in Figure 5a;

Fig. 6a is another cross-sectional schematic diagram of the plane where the dotted frame W is located in Fig. 1b;

Fig. 6b is another cross-sectional schematic diagram of the plane where the dotted frame W is located in Fig. 2a;

Fig. 6c is another cross-sectional schematic diagram of the plane where the dotted frame W is located in Fig. 3a;

Figure 6d is a schematic cross-sectional view at the dotted line KK' in Figure 6a;

FIG. 7 is a schematic three-dimensional structure diagram of a storage string in an embodiment of the present application;

Figure 8 is a schematic cross-sectional view at the dotted line NN' in Figure 7;

9 is a schematic three-dimensional structure diagram of a ferroelectric memory in an embodiment of the present application;

Figure 10 is a top view of the ferroelectric memory shown in Figure 9;

Figure 11 is a schematic cross-sectional view of the dotted line RR' in Figure 9;

Figure 12 is a schematic cross-sectional view of the dotted line QQ' in Figure 9;

13 is another top view of the ferroelectric memory in the embodiment of the application;

14 is another top view of the ferroelectric memory in the embodiment of the application;

15 is another top view of the ferroelectric memory in the embodiment of the application;

FIG. 16 is another top view of the ferroelectric memory in the embodiment of the application.

Reference number:

1-ferroelectric memory; 10-memory cell; 101-outside electrode; 102-center electrode; 103-ferroelectric structure; 104-switch control layer; 105-insulation isolation layer; 106-lead electrode; 20-storage string; 11 -interface; 2-memory controller; U-through hole; A1-first endpoint; A2-second endpoint; C-geometric center; T-initial polarization direction; E-electric field direction; P-metal particle; V - strip groove; F1 - first direction; F2 - second direction; F3 - third direction.

Detailed ways

Ferroelectric memory can be applied to various data information storage fields, for example, can be applied to the memory in electronic equipment such as processors, computers or servers, the processors can be central processing units, artificial intelligence processors, digital signal processing of course, the ferroelectric memory in this embodiment of the present application can also be applied to other electronic devices, which is not limited here.

In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings.

It should be noted that in this specification, like numerals and letters refer to like items in the following figures, so that once an item is defined in one figure, it need not be used in subsequent figures. for further definitions and explanations.

In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed to indicate or imply relative importance.

In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood in specific situations.

Current ferroelectric memory FRAMs store data based on the ferroelectric effect of ferroelectric materials. However, the initial polarization direction of the ferroelectric material needs to be set parallel to the electric field direction, which makes it necessary to accurately design and calculate the polarization direction of the ferroelectric material and the direction of micro-nano processing during the fabrication of the ferroelectric memory. This makes the manufacturing process more difficult. In order to reduce the difficulty of the fabrication process of the ferroelectric memory. FIG. 1 a is a schematic structural diagram of a ferroelectric memory provided by an embodiment of the present disclosure applied to an electronic device. As shown in FIG. 1 a , the electronic device includes a ferroelectric memory 1 and a storage controller 2 . Among them, the storage controller 2 is used to control the reading and writing of the ferroelectric memory 1 . The ferroelectric memory 1 may include: at least one storage unit 10 , and an interface 11 . In FIG. 1a, the ferroelectric memory 1 includes three storage units 10 and one interface 11 as an example for illustration, and the number of the storage units 10 and the interfaces 11 in the ferroelectric memory 1 is not limited. 1b is a schematic three-dimensional structure diagram of a memory cell in an embodiment of the present application, and FIG. 1c is a schematic cross-sectional view of the plane where the dotted frame W in FIG. 1b is located. Combined with FIG. 1b and FIG. 1c, the memory cell 10 includes: an outer electrode 101, a center electrode 102, and a ferroelectric structure 103; the ferroelectric structure 103 includes: a ferroelectric material, and a through hole U penetrating the ferroelectric material in the first direction F1; the central electrode 102 is a strip-shaped structure located in the through hole U; 101 surrounds part of the ferroelectric structure 103; the initial electric polarization direction T of the ferroelectric structure 103 is any direction parallel to the first plane, and the first plane is a plane perpendicular to the first direction F1 and passing through the outer electrode 101, as shown in Fig. The plane specified by the direction vector indicated by the arrow F2 and the direction vector indicated by the arrow F3 in 1b, for example, the first plane may be the plane where the dotted frame W in FIG. 1b is located. In practical applications, the initial polarization direction of the ferroelectric material can be directly observed by a high-precision scanning electron microscope (SEM), or the ferroelectric material can be placed in an electric field to observe the response of the ferroelectric material to the electric field. , to indirectly detect the initial polarization direction of ferroelectric materials. 1b and 1c, in the embodiment of the present application, the outer electrode 101 surrounds part of the ferroelectric structure 103, and the central electrode 102 is located in the through hole U of the ferroelectric structure 103. Therefore, the electric field formed by the outer electrode 101 and the central electrode 102 The direction of the electric field is divergent as a whole, that is, the electric field direction is multiple directions from the central electrode 102 to the outer electrode 101, or the electric field direction is multiple directions from the outer electrode 101 to the central electrode 102, so that the electric field direction is different from the ferroelectric material. There are multiple angles in the polarization direction. The initial polarization direction T of the ferroelectric structure 103 is any direction parallel to the first plane. In this way, in the electric field formed by the outer electrode 101 and the central electrode 102, there must be an electric field direction (or a component of the electric field direction) and the ferroelectric field. The initial polarization directions T of the structures 103 are opposite. Therefore, as long as a sufficiently large voltage is applied to the outer electrode 101 and the center electrode 102 , the electric field formed can reverse the ferroelectric material in the ferroelectric structure 103 . In this way, in the production process of the ferroelectric memory, as long as the initial polarization direction T of the ferroelectric structure 103 is parallel to the first plane, there is no need to accurately design and calculate the polarization direction and the micro-nano processing direction of the ferroelectric material. The requirement of machining accuracy is lower, the difficulty of the fabrication process is smaller, and it is easier to fabricate a storage unit with better miniaturization.

In the embodiment of the present application, the structure of the storage unit is relatively simple, and it is easy to stack into a two-dimensional or three-dimensional ferroelectric memory with a relatively compact structure, so that it is easy to obtain a ferroelectric memory with a large storage capacity. The polarization direction reversal of the ferroelectric material is driven by an electric field to realize data read and write operations without current driving, so the power consumption is lower, and the polarization direction reversal speed of the ferroelectric material under the control of the electric field is faster than Fast, so that the read and write speed of the ferroelectric memory is faster. In addition, parallel random storage can be used to make the transmission bandwidth of the ferroelectric memory higher.

Optionally, in the present application, as shown in FIG. 1b, the surface of the outer electrode 101 on the side close to the central electrode 102 is a curved surface with a certain radian, the ferroelectric structure 103 is in contact with the curved surface of the outer electrode 101, and the central electrode 102 is located in the inside the hole U, and the center electrode 102 is in contact with the ferroelectric structure 103 . The outer electrode 101 may be a polyhedron structure of various shapes. As shown in FIG. 1b and FIG. 1c , the outer electrode 101 may be a “U”-shaped polyhedron structure. FIG. 2a is another three-dimensional schematic diagram of the memory cell in the embodiment of the application, and FIG. 2b is a cross-sectional schematic diagram of the plane where the dotted frame W in FIG. 2a is located. As shown in FIGS. 2a and 2b, the outer electrode 101 may also be triangular Polyhedral structure. 3a is another three-dimensional schematic diagram of the memory cell in the embodiment of the application, and FIG. 3b is a schematic cross-sectional view of the plane where the dotted frame W in FIG. 3a is located. As shown in FIGS. 3a and 3b, the outer electrode 101 may also be semicircular. Polyhedral structure. In addition, the outer electrode 101 may have other shapes as long as it can surround part of the ferroelectric structure 103 , and the shape of the outer electrode 101 is not limited here. In addition, the cross-section of the central electrode 102 can also be in various shapes. For example, the cross-sectional shape of the central electrode 102 in FIG. 1b is a square, and the cross-sectional shape of the central electrode 102 in FIG. The cross-sectional shape of the center electrode 102 is circular, and the cross-section of the center electrode 102 may also be other shapes, which are not limited here.

In the embodiment of the present application, the initial polarization direction of the ferroelectric structure is any direction parallel to the first plane. For example, in FIG. 1c, FIG. 2b and FIG. 3b, the initial polarization direction T of the ferroelectric structure 103 is an arrow in the figure In the direction shown in F3, FIG. 1d is another schematic cross-sectional view of the plane where the dotted frame W in FIG. 1b is located, FIG. 2c is another schematic cross-sectional view of the plane where the dotted frame W is located in FIG. 2a, and FIG. Another schematic cross-sectional view of the plane, for example, in FIG. 1d, FIG. 2c and FIG. 3c, the initial polarization direction T of the ferroelectric structure 103 is the direction between the arrows F2 and F3. Of course, the initial polarization direction of the ferroelectric structure 103 T can also be other directions parallel to the first plane, which is not limited here.

4a and 4b are schematic diagrams of the working principle of the memory cell in the embodiment of the present application, and in FIGS. 4a and 4b, the outer electrode 101 is taken as an example in a semicircular shape for illustration. The working principle will be described in detail below by taking the memory cells shown in FIG. 4a and FIG. 4b as an example. As shown in FIG. 4a, the initial polarization direction T of the ferroelectric structure 103 is rightward. When a reverse electric field is applied to the outer electrode 101 and the central electrode 102, a high potential voltage is applied to the central electrode 102, and a low potential is applied to the outer electrode 101. The voltage of the potential, the electric field direction E in the ferroelectric material is a plurality of directions from the center electrode 102 to the outer electrode 101 . At the central position of the outer electrode 101, the electric field direction E is opposite to the initial polarization direction T. If the electric field strength is greater than the critical reversal electric field of the ferroelectric material, the polarization reversal of the ferroelectric material at this position will cause a new domain to form. At the core, the polarization direction of the ferroelectric material is reversed, and the resulting polarization direction is shown by the arrow T' in Fig. 4a, and a reverse electric domain is formed between the outer electrode 101 and the center electrode 102 at this position, Fig. 4a The area between the dashed line L1 and the dashed line L2 is where the reverse electric domain is located. Subsequently, the reversed domain expands laterally, that is, along the arrow F2 and the reverse expansion of the arrow F2, to form the reversed domain located between the dashed line L1 and the dashed line L2 as shown in FIG. 4b. Since the electric field is distributed along the radial direction, there is a certain angle θ between the electric field direction E and the domain wall (at the dotted line L1 in the figure), which can increase the read current, and the read voltage is low, thereby reducing the iron Power consumption of electrical memory.

In some embodiments of the present application, the material of the outer electrode and the center electrode may be the same or different, and optionally, the material of the outer electrode or the center electrode may include: titanium nitride (TiN), tungsten (W), nickel ( Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir), iridium oxide (IrOx), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si) or a compound of silicon and metal, of course, other materials that can be used as electrodes can also be used for the outer electrode or the center electrode, which is not limited here. In addition, the above-mentioned ferroelectric materials may include: lithium niobate, blackened lithium niobate, doped lithium niobate, lithium tantalate, blackened lithium tantalate, doped lithium tantalate, bismuth ferrite, barium titanate, titanium Barium strontium acid or strontium titanate, and the ferroelectric material can also be other materials with ferroelectric properties, which are not limited here. In addition, the ferroelectric material can be a thin-film ferroelectric material or a bulk ferroelectric material (eg, a ferroelectric wafer, etc.), and the form of the ferroelectric material is not limited here.

As shown in FIG. 3b , in the ferroelectric memory provided by the embodiment of the present application, the outer electrode 101 has two endpoints at the edge of the first plane, which are the first endpoint A1 and the second endpoint A2 respectively; the geometry of the center electrode 102 Among the included angles between the center C and the connecting lines of the first endpoint A1 and the second endpoint A2 respectively, the included angle α toward the outer electrode 101 is less than or equal to 180°, and FIG. 3d shows that when the included angle α is greater than 180°, the memory cell is in The cross-sectional schematic diagram of the first plane, and referring to FIG. 3d, the electric field direction E in the ferroelectric material is a plurality of directions from the central electrode 102 to the outer electrode 101. If the geometric center C of the central electrode 102 is connected to the first endpoint A1, the If the angle α between the lines connecting the two endpoints A2 is greater than 180°, there will be electric field components in opposite directions, so that the electric field components will cancel each other out, weakening the electric field strength of the electric field in a certain direction.

In some embodiments of the present application, a switch control layer may also be set in the storage unit, and several implementation manners of the switch control layer will be described in detail below with reference to the accompanying drawings.

method one:

5a is another schematic cross-sectional view of the plane where the dotted frame W in FIG. 1b is located, FIG. 5b is another schematic cross-sectional view of the plane where the dotted frame W is located in FIG. 2a, and FIG. 5c is another schematic cross-sectional view of the plane where the dotted frame W is located in FIG. 3a 5a to 5c, the memory cell may further include: a switch control layer 104 located between the outer electrode 101 and the ferroelectric structure 103; the switch control layer 104 covers the surface of the outer electrode 101 facing the ferroelectric structure 103 side, The outer electrodes 101 are not in direct contact with the ferroelectric structure 103 . In specific implementation, when the voltage applied to the switch control layer 104 is greater than the turn-on threshold, the switch control layer 104 is turned on, and then the data read operation can be realized by applying a voltage to the outer electrode 101 and the center electrode 102 . When the voltage applied to the switch control layer 104 is less than the turn-on threshold, the switch control layer 104 is turned off. At this time, even if a voltage is applied to the outer electrode 101 and the center electrode 102, the data reading operation cannot be performed. Which storage units in the ferroelectric memory perform read and write operations to improve the flexibility of the ferroelectric memory.

In the actual process, a switch control layer can be deposited on the sidewall of the ferroelectric structure by means of thin film deposition. Optionally, the switch control layer may include: a titanium oxide (TiO _x ) thin film, a composite thin film of copper oxide (CuO) and indium zinc oxide (InZnO _x ), a hafnium oxide (HfO _x ) thin film, a doped hafnium oxide thin film, Doped nickel oxide (NiO _x ) film, composite film of tungsten oxide (WO ₃ ) and zinc oxide (ZnO) or composite film of tantalum nitride (TaN), silicon nitride (SiN _x ), and tantalum nitride (TaN) .

Method two:

As shown in FIGS. 5 a to 5 c , the memory cell may further include: a switch control layer 104 between the outer electrode 101 and the ferroelectric structure 103 ; the switch control layer 104 covers the surface of the outer electrode 101 facing the ferroelectric structure 103 . The function of the switch control layer in the second mode is the same as the function of the switch control layer in the first mode, which is not repeated here.

5d is a schematic cross-sectional view at the dotted line MM' in FIG. 5a. As shown in FIG. 5d, in the ferroelectric structure 103, a plurality of metal particles P are distributed within a set depth from the surface of the ferroelectric structure 103 toward the outer electrode 101, The partial ferroelectric structure 103 having a plurality of metal particles P serves as the switching control layer 104 . In the actual process, the metal particles P can be diffused into the depth set on the surface of the ferroelectric structure 103 by means of element diffusion. Optionally, the material of the metal particles P may include titanium (Ti), chromium (Cr), iridium (Ir) or platinum (Pt). In addition, the metal particles P may also use other metal materials, which are not limited here.

Method three:

Fig. 6a is another schematic cross-sectional view of the plane where the dotted frame W in Fig. 1b is located, Fig. 6b is another schematic cross-sectional view of the plane where the dotted frame W is located in Fig. 2a, Fig. 6c is another schematic cross-sectional view of the plane where the dotted frame W is located in Fig. 3a 6a to 6c, the memory cell may further include: a switch control layer 104 located between the ferroelectric structure 103 and the center electrode 102; the switch control layer 104 covers the side of the center electrode 102, so that the center electrode 102 and the iron The electrical structures 103 are not in direct contact. In specific implementation, when the voltage applied to the switch control layer 104 is greater than the turn-on threshold, the switch control layer 104 is turned on, and then the data read operation can be realized by applying a voltage to the outer electrode 101 and the center electrode 102. When the voltage applied to the switch control layer 104 is less than the turn-on threshold, the switch control layer 104 is turned off. At this time, even if a voltage is applied to the outer electrode 101 and the center electrode 102, the data reading operation cannot be performed. Which storage units in the ferroelectric memory perform read and write operations to improve the flexibility of the ferroelectric memory.

In the actual process, a switch control layer can be deposited on the sidewall of the ferroelectric structure by means of thin film deposition. Optionally, the switch control layer includes: a titanium oxide (TiO _x ) thin film, a composite thin film of copper oxide (CuO) and indium zinc oxide (InZnO _x ), a hafnium oxide (HfO _x ) thin film, a doped hafnium oxide thin film, and a doped hafnium oxide thin film. Hetero nickel oxide (NiO _x ) films, composite films of tungsten oxide (WO ₃ ) and zinc oxide (ZnO) or composite films of tantalum nitride (TaN), silicon nitride (SiN _x ), and tantalum nitride (TaN).

Method four:

As shown in FIGS. 6 a to 6 c , the memory cell may further include: a switch control layer 104 located between the ferroelectric structure 103 and the center electrode 102 ; the switch control layer 104 covers the side of the center electrode 102 . The function of the switch control layer in the fourth mode is the same as the function of the switch control layer in the third mode, and details are not repeated here.

6d is a schematic cross-sectional view at the dotted line KK' in FIG. 6a. As shown in FIG. 6d, in the ferroelectric structure 103, a plurality of metal particles P are distributed within a set depth from the surface of the ferroelectric structure 103 toward the center electrode 102, The partial ferroelectric structure 103 having a plurality of metal particles P serves as the switching control layer 104 . In the actual process, the metal particles P can be diffused into the depth set on the surface of the ferroelectric structure 103 by means of element diffusion. Optionally, the material of the metal particles P may include titanium (Ti), chromium (Cr), iridium (Ir) or platinum (Pt). In addition, the metal particles P may also use other metal materials, which are not limited here.

In other embodiments, the ferroelectric memory may include at least one memory string. FIG. 7 is a schematic three-dimensional structure diagram of a memory string in an embodiment of the present application, and FIG. 8 is a schematic cross-sectional view at the dotted line NN' in FIG. 7 , as shown in FIGS. 7 and 7 . As shown in FIG. 8 , the memory string 20 may include a plurality of memory cells 10 arranged in the first direction F1 ; the plurality of memory cells 10 in the memory string 20 share a central electrode 102 and a ferroelectric structure 103 . By sharing the center electrode 102 and the ferroelectric structure 103, the fabrication process of the memory string 20 can be made simpler and the fabrication cost can be saved. Specifically, during the fabrication process, holes can be punched in the first direction F1 in the entire piece of ferroelectric material. , forming a through hole U penetrating the ferroelectric material in the first direction F1 , and then filling the through hole U with a metal material to form a center electrode 102 located in the through hole U. In addition, by disposing the central electrode 102 in the through hole U of the ferroelectric material, the structure of the memory string 20 can be made more compact.

7 and 8, the memory string 20 may further include a plurality of insulating isolation layers 105; the plurality of insulating isolation layers 105 and the plurality of outer electrodes 101 in the memory string 20 are alternately arranged in the first direction F1, and a plurality of Both the insulating isolation layer 105 and the plurality of outer electrodes 101 surround part of the ferroelectric structure 103 . In this way, the outer electrodes 101 in different memory cells 10 can be insulated from each other, so that different memory cells 10 can be controlled to perform data read and write operations respectively. The material of the insulating isolation layer 105 may include: silicon dioxide, silicon nitride, titanium dioxide, hafnium dioxide, aluminum nitride or aluminum oxide, in addition, the insulating isolation layer 105 may also include other insulating materials, which are not limited herein.

Optionally, in the above-mentioned ferroelectric memory provided by the embodiment of the present application, referring to FIGS. 7 and 8 , in a memory string 20, one end of the center electrode 102 is located outside the first outer electrode 101, and the other end is located at the last one. The outside of the outer electrode 101 , that is, the top surface of the center electrode 102 is higher than the top surface of the first outer electrode 101 , and the bottom surface of the center electrode 102 is lower than the bottom surface of the last outer electrode 101 . In this way, the corresponding positions of the outer electrodes 101 can be ensured to have the central electrodes 102, so that the electric field formed by the central electrodes 102 and the outer electrodes 101 has a larger electric field component in the first plane, thereby improving the electrical performance of the storage string.

9 is a schematic three-dimensional structure diagram of a ferroelectric memory in an embodiment of the application, and FIG. 10 is a top view of the ferroelectric memory shown in FIG. 9 . As shown in FIGS. 9 and 10 , the ferroelectric memory further includes a plurality of The memory strings 20 arranged on F2 and the third direction F3; the second direction F2 and the first direction F1 are perpendicular to each other, the third direction F3 and the first direction F1 are perpendicular to each other, the second direction F2 and the third direction F3 are perpendicular to each other, so that , the ferroelectric memory can be formed into a three-dimensional structure, and the structure of the ferroelectric memory is relatively compact, and the density of the storage unit is relatively large, so the capacity of the ferroelectric memory is relatively large. In addition, the plurality of storage strings 20 in the ferroelectric memory share one ferroelectric structure 103. On the one hand, the structure of the ferroelectric memory can be made more compact; on the other hand, the manufacturing process of the ferroelectric memory can be made simpler, and the cost of raw materials The production cost is relatively low. Figure 11 is a schematic cross-sectional view of the dotted line RR' in Figure 9. Combined with Figures 9 and 11, in the production process, single-layer ferroelectric materials or bulk ferroelectric materials (such as ferroelectric crystals) can be selected. circle, etc.) for processing. A plurality of strip-shaped grooves V can be formed in the ferroelectric material, and the strip-shaped grooves V are used to accommodate each outer electrode 101 and each insulating isolation layer 105 of a row of memory strings 20. The shapes of the outer electrodes 101 are consistent, so that the outer electrodes 101 subsequently disposed in the strip-shaped grooves V surround part of the ferroelectric structure 103, and then, in the area surrounded by the outer electrodes 101, through holes U penetrating the ferroelectric structure are arranged to pass through the ferroelectric structure. The depth of the hole U is greater than the depth of the strip groove V. After that, each through hole U is filled with a metal material to form a plurality of central electrodes 102 , and the outer electrodes 101 and insulating isolation layers 105 are deposited in each strip-shaped groove V layer by layer. Optionally, the strip-shaped groove V, the through hole U, the outer electrode 101 and the insulating isolation layer 105 may be fabricated by an etching process, or other processes may be used, which is not limited here. In the manufacturing process of the three-dimensional ferroelectric memory, a plurality of memory cells can share the process steps, for example, can share the etching process, so as to save the manufacturing cost. Moreover, in the production process layer, the tolerance of the error of the production process is high. As long as the outer electrode and the center electrode can be in contact with the ferroelectric material, the memory cell can realize the storage function, and the requirements for the production accuracy are low, and the production is difficult. and lower cost.

FIG. 12 is a schematic cross-sectional view of the dotted line QQ' in FIG. 9. With reference to FIG. 9 and FIG. 12, the ferroelectric memory in the embodiment of the present application may further include: a plurality of lead-out electrodes 106; a row of storage electrodes arranged in the second direction F2 In the string, the i-th outer electrode 101 in each storage string is connected to the lead-out electrode 106; wherein, i takes any positive integer from 1 to N, and N is the number of storage cells in the storage string; in the second direction F2 At the edge of an array of memory strings, a plurality of insulating isolation layers 105 and a plurality of outer electrodes 101 are stacked in a stepped shape to expose each lead-out electrode 106 . For ease of control, the i-th outer electrodes 101 of each memory string in a row of memory strings can be connected as a whole, that is, each outer electrode 101 belonging to the same layer in a row of memory strings is connected as a whole. Optionally, the i-th outer electrode 101 in each memory string may be connected to one lead-out electrode 106, or may be connected to one lead-out electrode 106 at both ends. Each lead electrode 106 can be used as a word line (WL) of the ferroelectric memory, and each center electrode 102 can be used as a bit line (BL) of the ferroelectric memory. A voltage is applied to the outer electrodes 101 in a row of memory cells arranged in the second direction F2, and through the central electrode 102, a voltage can be applied to the central electrodes 102 of a row of memory cells arranged in the first direction F1. Therefore, in this application , the read and write operations of each memory cell can be controlled separately through each lead electrode 106 and each center electrode 102 .

As shown in FIG. 10 , in the embodiment of the present application, the minimum distance between the central electrode 102 and the outer electrodes 101 belonging to the same memory cell is the first distance d1; two adjacent rows of memory cells in the third direction F3 The spacing between the strings 20 is the second distance d2; the first distance d1 is smaller than the second distance d2, for example, the first distance d1 can be set to be less than half of the second distance d2, so that adjacent memory cells can be prevented from being separated from each other. Crosstalk occurs between the electric fields between them, which improves the electrical properties of the ferroelectric memory.

FIG. 13 is another top view of the ferroelectric memory in the embodiment of the application. As shown in FIG. 13 , the surface of the outer electrode 101 away from the center electrode 102 can be set to be flat, as long as the outer electrode 101 faces the center electrode 102 side. The surface may be a curved surface with a certain radian, so that the manufacturing difficulty can be reduced. FIG. 14 is another top view of the ferroelectric memory in the embodiment of the application. As shown in FIG. 14 , the surface of the outer electrode 101 on the side away from the center electrode 102 may also be a curved surface, and the side of the outer electrode 101 away from the center electrode 102 is not used here. The shape of the surface is defined.

FIG. 15 is another top view of the ferroelectric memory in the embodiment of the application, and FIG. 16 is another top view of the ferroelectric memory in the embodiment of the application. As shown in FIG. 15 and FIG. In the row memory cells, the shape of the connection position between the adjacent outer electrodes 101 can be set according to the actual situation, and it can be the shape shown in FIG. 15 or the shape shown in FIG. 16 , which is not limited here. . In addition, as shown in FIG. 15 , the center electrode 102 may be located at the center position of the corresponding outer electrode 101 , or, as shown in FIG. 16 , the center electrode 102 may also be deviated from the center position of the corresponding outer electrode 101 , not to the outer side here. The relative positions of the electrode 101 and the center electrode 102 are defined. That is to say, the structure of the ferroelectric memory of the present application has a relatively large tolerance to the process. For example, the center electrode 102 deviates from the center position of the corresponding outer electrode 101 due to errors during processing, which will not affect the device performance.

Based on the same technical concept, an embodiment of the present application also provides an electronic device, as shown in FIG. 1a, comprising: any of the above-mentioned ferroelectric memory 1, and a storage controller 2; and a storage controller 2 for controlling the ferroelectric memory 1 read and write. Optionally, voltages can be applied to the outer electrodes and the center electrodes in the ferroelectric memory 1 through the memory controller 2 to control the ferroelectric memory 1 to implement read and write operations. The electronic device in this application may be a processor, a computer or a server, etc., or may be other electronic devices, which are not limited here.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, and should cover within the scope of protection of this application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (12)

1. A ferroelectric memory, comprising: at least one storage unit;

   The storage unit includes: an outer electrode, a center electrode, and a ferroelectric structure;

   The ferroelectric structure includes: a ferroelectric material, and a through hole penetrating the ferroelectric material in the first direction; the central electrode is a strip-shaped structure located in the through hole; the ferroelectric structure;

   The initial electric polarization direction of the ferroelectric structure is any direction parallel to a first plane, and the first plane is a plane perpendicular to the first direction and passing through the outer electrode.
2. The ferroelectric memory according to claim 1, wherein the outer electrode has two end points on the edge of the first plane, which are a first end point and a second end point;

   Among the included angles between the geometric center of the central electrode and the connecting line of the first end point and the second end point, the included angle toward the outer electrode is less than or equal to 180°.
3. The ferroelectric memory of claim 1, wherein the memory cell further comprises: a switch control layer located between the outer electrode and the ferroelectric structure;

   the switch control layer covers the surface of the outer electrode facing the side of the ferroelectric structure;

   The switch control layer includes: titanium oxide film, composite film of copper oxide and indium zinc oxide, hafnium oxide film, doped hafnium oxide film, doped nickel oxide film, composite film of tungsten oxide and zinc oxide or tantalum nitride , Silicon nitride, tantalum nitride composite film.
4. The ferroelectric memory of claim 1, wherein the memory cell further comprises: a switch control layer located between the outer electrode and the ferroelectric structure;

   the switch control layer covers the surface of the outer electrode facing the side of the ferroelectric structure;

   In the ferroelectric structure, a plurality of metal particles are distributed within a set depth from the surface of the ferroelectric structure facing the outer electrode, and a part of the ferroelectric structure having the plurality of metal particles serves as the switch control layer .
5. The ferroelectric memory of claim 1, wherein the storage unit further comprises: a switch control layer located between the ferroelectric structure and the center electrode;

   the switch control layer covers the side surface of the center electrode;

   The switch control layer includes: titanium oxide film, composite film of copper oxide and indium zinc oxide, hafnium oxide film, doped hafnium oxide film, doped nickel oxide film, composite film of tungsten oxide and zinc oxide or tantalum nitride , Silicon nitride, tantalum nitride composite film.
6. The ferroelectric memory of claim 1, wherein the storage unit further comprises: a switch control layer located between the ferroelectric structure and the center electrode;

   the switch control layer covers the side surface of the center electrode;

   In the ferroelectric structure, a plurality of metal particles are distributed within a set depth from the surface of the ferroelectric structure facing the center electrode, and a part of the ferroelectric structure having the plurality of metal particles serves as the switch control layer .
7. The ferroelectric memory according to any one of claims 1 to 6, wherein the ferroelectric memory comprises at least one memory string;

   The memory string includes a plurality of the memory cells arranged in the first direction; the plurality of the memory cells in the memory string share one of the central electrodes and one of the ferroelectric structures;

   The storage string further includes a plurality of insulating isolation layers; a plurality of the insulating isolation layers and a plurality of the outer electrodes in the storage string are alternately arranged in the first direction, and a plurality of the insulating isolation layers and a plurality of the outer electrodes surround part of the ferroelectric structure.
8. The ferroelectric memory according to claim 7, wherein, in one of the memory strings, one end of the central electrode is located outside the first outer electrode, and the other end is located outside the last outer electrode. outside.
9. The ferroelectric memory of claim 7, wherein the ferroelectric memory further comprises a plurality of the memory strings arranged in a second direction and a third direction; the second direction and the first direction perpendicular to each other, the third direction and the first direction are perpendicular to each other, the second direction and the third direction are perpendicular to each other;

   A plurality of the memory strings in the ferroelectric memory share one of the ferroelectric structures.
10. The ferroelectric memory of claim 9, wherein the ferroelectric memory further comprises: a plurality of extraction electrodes;

    In a row of the memory strings arranged in the second direction, the i-th outer electrode in each of the memory strings is connected to the lead-out electrode; wherein the i is taken from any value from 1 to N. A positive integer, the N is the number of the storage units in the storage string;

    At the edge of a row of the memory strings arranged in the second direction, a plurality of insulating isolation layers and a plurality of the outer electrodes are stacked in a stepped shape to expose each of the lead electrodes.
11. The ferroelectric memory according to claim 9, wherein the minimum distance between the central electrode and the outer electrodes belonging to the same memory cell is the first distance;

    The distance between two adjacent rows of the storage strings in the third direction is the second distance;

    The first distance is smaller than the second distance.
12. An electronic device, comprising: the ferroelectric memory according to any one of claims 1 to 11, and a memory controller;

    The storage controller is used to control the reading and writing of the ferroelectric memory.

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