CN112382720A - Device structure for increasing working current of ferroelectric tunneling junction and preparation method thereof - Google Patents
Device structure for increasing working current of ferroelectric tunneling junction and preparation method thereof Download PDFInfo
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- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
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- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
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- H—ELECTRICITY
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Abstract
The application provides a device structure for increasing the working current of a ferroelectric tunneling junction and a preparation method thereof, wherein the device structure comprises: an upper electrode, a ferroelectric layer and a lower electrode; the upper electrode is cylindrical, the ferroelectric layer wraps the outer side of the upper electrode, and the lower electrode wraps the outer side of the ferroelectric layer. According to the device structure of the embodiment of the application, the working current of the ferroelectric tunneling junction can be increased.
Description
Technical Field
The application relates to the technical field of microelectronic devices, in particular to a device structure for increasing working current of a ferroelectric tunneling junction and a preparation method thereof.
Background
The performance of computing systems depends on the performance of memory systems, the mainstream commercial memories include dynamic random access memories and flash memories, and the working mechanism of these memory technologies is charge storage: dynamic random access memory stores charge in a capacitor and flash memory stores charge in a floating gate of a transistor. As integrated circuit process feature sizes shrink, the amount of stored charge decreases and is more easily lost, and devices relying on charge to store information present greater challenges in performance and reliability as feature sizes shrink to 10 nm.
The ferroelectric tunneling junction is a device for storing information by depending on the polarization direction of a ferroelectric material, and has a simple two-terminal structure, a nonvolatile characteristic, a good size reduction characteristic (expected to reach below 10 nm), a very fast switching speed (usually several nanoseconds), and a good erasing-writing resistance characteristic (up to 10 ns)11-1012Second), good retention properties (up to 10 years). Ferroelectric tunnel junctions are expected to replace dynamic random access memories and flash memories in some applications. On the other hand, mainstream computing systems are based on a von neumann architecture under which a storage unit is separated from a computing unit, and further, data handling accompanying an arithmetic process limits the speed and energy efficiency of the computing system, which becomes particularly serious in applications requiring processing of a large amount of data typified by deep learning. The ferroelectric tunneling junction can be used for memory computing, and in a memory computing framework, the ferroelectric tunneling junction crisscross array can efficiently realize matrix vector multiplication and further be used for realizing an artificial neural network.
A ferroelectric tunnel junction is composed of two electrodes and a barrier layer with ferroelectric properties sandwiched between them, the thickness of the barrier layer being typically a few nanometers-thin enough to allow direct tunneling. The polarization direction of the ferroelectric barrier layer affects the band structure of the ferroelectric tunneling junction, and further affects the magnitude of the tunneling current, which represents the information stored therein. The traditional ferroelectric barrier layer is made of lead zirconate titanate, barium titanate and other single crystal materials, and the growth temperature of the single crystal materials is too high, so that the traditional ferroelectric barrier layer is incompatible with the existing integrated circuit process. Zirconium-doped hafnium oxide annealed at about 400 c forms a poly crystal with ferroelectric properties in the temperature range that transistors can withstand, and hafnium oxide is the gate dielectric material in integrated circuits, and thus has found wide interest in the hafnium oxide material family. However, the working current of the ferroelectric tunneling junction based on the hafnium oxide material is usually small, even less than 1nA, and when the ferroelectric tunneling junction is used in a memory application, the reading speed is limited by the too small working current; for memory calculations, too small an operating current makes the design of the analog-to-digital converter very difficult. Therefore, it is necessary to increase the operating current of the ferroelectric tunnel junction.
Disclosure of Invention
The present application is directed to solving, at least to some extent, one of the technical problems in the conventional art.
Therefore, the application provides a device structure for increasing the working current of the ferroelectric tunneling junction and a preparation method thereof, so as to increase the working current of the ferroelectric tunneling junction.
An embodiment of a first aspect of the present application provides a device structure for increasing an operating current of a ferroelectric tunneling junction, including:
an upper electrode, a ferroelectric layer and a lower electrode;
the upper electrode is cylindrical, the ferroelectric layer wraps the outer side of the upper electrode, and the lower electrode wraps the outer side of the ferroelectric layer.
Optionally, the material of the upper electrode is at least one of a simple metal and a conductive metal compound.
Optionally, the material of the lower electrode is at least one of a simple metal and a conductive metal compound.
Optionally, the ferroelectric layer is composed of a material having ferroelectric properties.
Optionally, the upper electrode has a thickness of 50-500 nm.
Optionally, the thickness of the lower electrode is 50-500 nm.
Optionally, the ferroelectric layer has a thickness of 2-10 nm.
The embodiment of the second aspect of the present application provides a method for preparing a device structure for increasing an operating current of a ferroelectric tunneling junction, including:
preparing a lower electrode on a substrate material;
depositing an insulating material to form an insulating medium layer and carrying out polishing treatment;
forming a hole on the lower electrode in a photoetching and etching mode;
depositing a ferroelectric material and an upper electrode material, forming a ferroelectric layer and an upper electrode, and polishing;
and patterning the upper electrode in a photoetching and etching mode to prepare the device structure.
Optionally, the preparing a lower electrode on a substrate material includes: depositing a lower electrode material on the insulating substrate to form a lower electrode material layer; spin-coating photoresist on the lower electrode material layer, and exposing and developing; and performing reactive ion etching on the lower electrode material layer until the position without the photoresist is exposed out of the insulating substrate, and removing the photoresist to form the patterned lower electrode.
Optionally, the forming the hole on the lower electrode by photolithography and etching includes: spin-coating photoresist on the insulating medium layer, and exposing and developing; and performing reactive ion etching on the basis of the insulating medium layer and the lower electrode until the substrate material is exposed at the position without the photoresist, and removing the photoresist.
According to the device structure of the above embodiment of the present application, the working current of the ferroelectric tunneling junction can be increased, so that the ferroelectric tunneling junction is matched with a read circuit in a memory application and a storage and computation integrated application.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
Fig. 1 is a schematic structural diagram of a device structure for increasing an operating current of a ferroelectric tunneling junction according to an embodiment of the present application;
fig. 2 is a schematic diagram of a method for manufacturing a device structure for increasing an operating current of a ferroelectric tunneling junction according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.
The device structure for increasing the operating current of the ferroelectric tunneling junction and the preparation method thereof according to the embodiments of the present application are described below with reference to the accompanying drawings.
Ferroelectric tunneling junctions conduct by means of a tunneling current, and the operating current of the device is area-dependent — the operating current is proportional to its area. The working current of the current ferroelectric tunneling junction is too small, often several nanoamperes, and even less than 1 nA. In memory applications, a read circuit usually integrates a current through a capacitor to obtain a voltage signal to read the state of a memory cell, and an excessively small working current of the memory cell may result in an excessively large area of the capacitor or a long read delay. In memory computing application, an analog-to-digital converter reads and quantizes output current of a certain row (or column) of a ferroelectric tunneling junction array, and when the output current is too small, the problems of too large area of an integrating capacitor and too long read delay are caused, and the analog-to-digital converter is also easily subjected to noise interference, so that precision and resolution are reduced.
In the ferroelectric tunnel junctions reported in the literature at present, the smallest dimension is often a square with a side length of several hundred nanometers, and if the storage density is further improved, the area of the ferroelectric tunnel junction needs to be further reduced, and the working current of the device is also reduced, thereby further causing the above problems.
To this end, the embodiments of the present application provide a device structure to increase the operating current of the ferroelectric tunneling junction, so that the ferroelectric tunneling junction is matched with the read circuit in the memory application and the integrated memory application.
Fig. 1 is a schematic structural diagram of a device structure for increasing an operating current of a ferroelectric tunneling junction according to an embodiment of the present application, as shown in fig. 1, the device structure includes: an upper electrode 10, a ferroelectric layer 20 and a lower electrode 30.
The upper electrode 10 is cylindrical, the ferroelectric layer 20 wraps the outer side of the upper electrode 10, and the lower electrode 30 wraps the outer side of the ferroelectric layer 20. Referring to the cross section of fig. 1, the structure of the ferroelectric tunnel junction in the present embodiment is a three-dimensional ring structure.
In this embodiment, the material of the upper electrode 10 is at least one of a simple metal and a conductive metal compound. As an example, materials include, but are not limited to: pt, Pd, Au, Ag, Cu, Cr, Al, W, TiN, etc. The thickness of the upper electrode 10 is 50-500 nm.
In this embodiment, the material of the lower electrode 30 is at least one of a simple metal and a conductive metal compound. As an example, the material includes, but is not limited to, Pt, Pd, Au, Ag, Cu, Cr, Al, W, TiN, etc. The thickness of the lower electrode 30 is 50-500 nm.
In the present embodiment, the ferroelectric layer 20 is composed of a material having ferroelectric properties. As an example, materials include, but are not limited to: hf (hafnium)xZr1-xO2、HfO2、HfxSi1-xO2And the like. The ferroelectric layer 20 has a thickness of 2-10 nm.
According to the device structure for increasing the working current of the ferroelectric tunneling junction, the area of the ferroelectric tunneling junction is increased through the three-dimensional annular structure, so that the working current of the ferroelectric tunneling junction is increased, and the ferroelectric tunneling junction is matched with a reading circuit in memory application and storage and computation integrated application. Specifically, for the ferroelectric tunneling junction with the two-dimensional planar structure, the density of the memory unit is reduced due to the fact that the area of the device is directly increased, and for the ferroelectric tunneling junction with the three-dimensional annular structure, the area of the device can be increased on the premise that the density of the memory unit is not sacrificed, and meanwhile, the device has flexibility in the height direction of the device, so that the working current can be modulated by changing the height of the device and adjusting the area of the device.
In order to implement the above embodiments, the present application further provides a method for manufacturing a device structure that increases the operating current of the ferroelectric tunneling junction.
Fig. 2 is a schematic diagram of a method for manufacturing a device structure for increasing an operating current of a ferroelectric tunneling junction according to an embodiment of the present application, where the method includes:
step 201, a lower electrode is prepared on a substrate material.
Depositing a lower electrode material on an insulating substrate to form a lower electrode material layer; spin-coating photoresist on the lower electrode material layer, and exposing and developing; and performing reactive ion etching on the lower electrode material layer until the position without the photoresist is exposed out of the insulating substrate, and removing the photoresist to form the patterned lower electrode. The manner of depositing the lower electrode material on the insulating substrate includes: magnetron sputtering and electron beam evaporation.
Step 202, depositing an insulating material, forming an insulating dielectric layer and performing polishing treatment.
In this embodiment, after the lower electrode is prepared on the substrate material, an insulating dielectric layer is formed by depositing an insulating material, and then the surface is subjected to chemical mechanical polishing.
Wherein the insulating material is, for example, SiO2、SiNx、SiOxNyAnd the like. The method of depositing the insulating material includes: chemical vapor deposition and magnetron sputtering. The thickness of the deposited insulating medium layer is larger than that of the lower electrode, and after the chemical mechanical polishing is carried out, the insulating medium layer with the thickness larger than 20nm still exists on the patterned lower electrode.
In step 203, openings are formed in the lower electrode by means of photolithography and etching.
Wherein, spin-coating photoresist on the insulating medium layer and exposing and developing; and performing reactive ion etching on the basis of the insulating medium layer and the lower electrode until the substrate material is exposed at the position without the photoresist, and removing the photoresist, thereby realizing the purpose of forming holes at the preset position of the lower electrode.
Step 204, depositing a ferroelectric material and an upper electrode material, forming a ferroelectric layer and an upper electrode, and performing a polishing process.
In this embodiment, the method of depositing the ferroelectric material includes: atomic layer deposition and magnetron sputtering. The method for depositing the upper electrode comprises the following steps: magnetron sputtering and electron beam evaporation. And ensuring that the holes are fully filled when the upper electrode is deposited, and keeping the surface of the insulating medium layer to be still provided with an upper electrode material layer with the thickness of more than 20nm after the surface is subjected to chemical mechanical polishing.
Step 205, patterning the upper electrode by means of photolithography and etching to prepare a device structure.
Wherein, sputtering to grow an upper electrode lead material, spin-coating photoresist, and exposing and developing; and then carrying out reactive ion etching until the insulating medium layer is exposed at the position without the photoresist, removing the photoresist to obtain a patterned upper electrode, and realizing patterning of the lead by photoetching and etching.
Optionally, after photolithography and etching, annealing is performed to crystallize certain ferroelectric material layers to exhibit ferroelectric properties.
The explanation of the device structure in the foregoing embodiment is also applicable to this embodiment, and is not described herein again.
According to the preparation method of the embodiment of the application, the device structure of the previous embodiment can be prepared, so that the working current of the ferroelectric tunneling junction is increased through the device structure.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.
Claims (10)
1. A device structure for increasing operating current of a ferroelectric tunneling junction, comprising:
an upper electrode, a ferroelectric layer and a lower electrode;
the upper electrode is cylindrical, the ferroelectric layer wraps the outer side of the upper electrode, and the lower electrode wraps the outer side of the ferroelectric layer.
2. The device structure of claim 1, wherein the material of the upper electrode is at least one of a simple metal and a conductive metal compound.
3. The device structure of claim 1, wherein the material of the lower electrode is at least one of a simple metal and a conductive metal compound.
4. The device structure of claim 1, wherein the ferroelectric layer is comprised of a material having ferroelectric properties.
5. The device structure of claim 1, wherein the upper electrode has a thickness of 50-500 nm.
6. The device structure of claim 1, wherein the lower electrode has a thickness of 50-500 nm.
7. The device structure of claim 1, wherein the ferroelectric layer has a thickness of 2-10 nm.
8. A method for preparing a device structure for increasing the working current of a ferroelectric tunneling junction is characterized by comprising the following steps:
preparing a lower electrode on a substrate material;
depositing an insulating material to form an insulating medium layer and carrying out polishing treatment;
forming a hole on the lower electrode in a photoetching and etching mode;
depositing a ferroelectric material and an upper electrode material, forming a ferroelectric layer and an upper electrode, and polishing;
and patterning the upper electrode in a photoetching and etching mode to prepare the device structure.
9. The method of claim 8, wherein the fabricating the lower electrode on the substrate material comprises:
depositing a lower electrode material on the insulating substrate to form a lower electrode material layer;
spin-coating photoresist on the lower electrode material layer, and exposing and developing;
and performing reactive ion etching on the lower electrode material layer until the position without the photoresist is exposed out of the insulating substrate, and removing the photoresist to form the patterned lower electrode.
10. The method according to claim 8, wherein the opening of the lower electrode by photolithography and etching comprises:
spin-coating photoresist on the insulating medium layer, and exposing and developing;
and performing reactive ion etching on the basis of the insulating medium layer and the lower electrode until the substrate material is exposed at the position without the photoresist, and removing the photoresist.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4092749A1 (en) * | 2021-05-20 | 2022-11-23 | Intel Corporation | Cross array ferroelectric tunnel junction devices for artificial intelligence and machine learning accelerators |
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| CN103346256A (en) * | 2013-07-03 | 2013-10-09 | 南京大学 | Memristor based on ferroelectric tunnel junction |
| US20160181259A1 (en) * | 2014-12-23 | 2016-06-23 | Imec Vzw | Vertical ferroelectric memory device and a method for manufacturing thereof |
| KR101924733B1 (en) * | 2017-08-29 | 2018-12-03 | 포항공과대학교 산학협력단 | Vertical cross-point weighting device and method of operation thereof |
| US20190088664A1 (en) * | 2017-09-21 | 2019-03-21 | Toshiba Memory Corporation | Memory device |
| CN110867492A (en) * | 2019-10-15 | 2020-03-06 | 华中科技大学 | Ferroelectric two-terminal device, three-dimensional ferroelectric memory device and preparation method |
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- 2020-10-10 CN CN202011080259.3A patent/CN112382720A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103346256A (en) * | 2013-07-03 | 2013-10-09 | 南京大学 | Memristor based on ferroelectric tunnel junction |
| US20160181259A1 (en) * | 2014-12-23 | 2016-06-23 | Imec Vzw | Vertical ferroelectric memory device and a method for manufacturing thereof |
| KR101924733B1 (en) * | 2017-08-29 | 2018-12-03 | 포항공과대학교 산학협력단 | Vertical cross-point weighting device and method of operation thereof |
| US20190088664A1 (en) * | 2017-09-21 | 2019-03-21 | Toshiba Memory Corporation | Memory device |
| CN110867492A (en) * | 2019-10-15 | 2020-03-06 | 华中科技大学 | Ferroelectric two-terminal device, three-dimensional ferroelectric memory device and preparation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP4092749A1 (en) * | 2021-05-20 | 2022-11-23 | Intel Corporation | Cross array ferroelectric tunnel junction devices for artificial intelligence and machine learning accelerators |
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Application publication date: 20210219 |