WO2021237730A1

WO2021237730A1 - Three-dimensional ferroelectric memory and method for manufacturing same, and electronic device

Info

Publication number: WO2021237730A1
Application number: PCT/CN2020/093504
Authority: WO
Inventors: 张岩; 杨喜超; 魏侠; 秦健鹰
Original assignee: 华为技术有限公司
Priority date: 2020-05-29
Filing date: 2020-05-29
Publication date: 2021-12-02
Also published as: CN114930530A

Abstract

Provided is a method for manufacturing a three-dimensional ferroelectric memory. The method can ensure the good endurance of a three-dimensional ferroelectric memory and can also reduce etching difficulty during the manufacturing of the three-dimensional ferroelectric memory. The method comprises: forming a stacked layer on a substrate, wherein the stacked layer comprises isolation layers and sacrificial layers, which are stacked and alternately arranged; arranging a plurality of columns of first voltage lines in the stacked layer, and providing an isolation groove between any two adjacent columns of first voltage lines from among the plurality of columns of first voltage lines; and etching the sacrificial layers in the stacked layer, and forming metal layers, wherein the metal layers and the isolation layers are stacked and alternately arranged, so that a storage layer is obtained. Each metal layer comprises a ferroelectric layer and a plurality of second voltage lines, wherein the ferroelectric layer surrounds portions of the plurality of second voltage lines and portions of the plurality of columns of first voltage lines, which portions are positioned in the metal layers, so that an MFM structure is formed in the metal layer, and the endurance of a three-dimensional ferroelectric memory is ensured. Furthermore, the sacrificial layers are made of a material which easily corrodes, and thus, the etching difficulty during manufacturing can be reduced.

Description

Three-dimensional ferroelectric memory, manufacturing method and electronic equipment

Technical field

This application relates to the field of data storage technology, and in particular to a three-dimensional ferroelectric memory, a manufacturing method and electronic equipment.

Background technique

With the development of electronic technology, data storage technology has been rapidly improved. Among them, the memory produced by using ferroelectric materials to change the polarization direction under the action of an electric field is called Ferroelectric Random Access Memory (Ferroelectric Random Access Memory), or also called "ferroelectric memory". The memory cell in the ferroelectric memory may include a ferroelectric field-effect transistor (FeFET) based on a metal-ferroelectrics-insulator-semiconductor (MFIS) structure, and based on A ferroelectric capacitor with a metal-ferroelectrics-metal (MFM) structure. Compared with the memory cell of the MFIS structure, the MFM structure has better endurance, so it is widely used in 1T-1C (onetransistor-onecapacitor) FRAM.

In the related art, a method for manufacturing a three-dimensional ferroelectric memory based on the working principle of a ferroelectric diode (Fe-diode) of an MFM structure is provided. The specific method is: preparing _{a multilayer stack structure of SiO x} /TiN, and a metal layer TiN is used as a word line (WL), deep hole etching process is used to vertically etch the array deep holes through the stack structure, exposing the sidewalls of the WL, and depositing a ferroelectric layer on the sidewalls of the deep holes as a storage medium and deposition The TiN/W double-layer metal is used as a bit line (BL) to form a memory cell with an MFM structure. However, in this technology, as the number of stacked layers in the three-dimensional ferroelectric memory increases, the deep hole etching of the multilayer metal becomes more difficult. Therefore, the method of manufacturing a three-dimensional ferroelectric memory with this technology has high process requirements.

Summary of the invention

The present application provides a three-dimensional ferroelectric memory, a manufacturing method, and an electronic device, which are used to reduce the etching difficulty in the manufacturing process of the three-dimensional ferroelectric memory while ensuring the durability of the three-dimensional ferroelectric memory.

In order to achieve the above objectives, this application adopts the following technical solutions:

In a first aspect, a method for manufacturing a three-dimensional ferroelectric memory is provided. The method includes: forming a stacked layer on a substrate, where the substrate may be a silicon wafer, a die, or a silicon integrated circuit Etc., the stacked layer includes an isolation layer and a sacrificial layer that are stacked and alternately arranged. The isolation layer may be an electrically insulating material and used to isolate two adjacent sacrificial layers. The sacrificial layer may be removed or sacrificed later. The sacrificial layer is made of easily corrosive material, for example, the sacrificial layer is silicon nitride (SiN _x ); a plurality of columns of first voltage lines are arranged in the stacked layer, and the plurality of columns of first voltage lines are along the depth of the stacked layer Direction extension (for example, one end of the first voltage line of the plurality of columns is located on the surface of the stacked layer away from the substrate, and the other end is located on the surface of the stacked layer close to the substrate), the first voltage line may be a bit line; An isolation groove penetrating the stacked layer is formed between any two adjacent columns of the first voltage line in the voltage line, that is, the isolation groove physically separates the two adjacent columns of the first voltage line; the stacked layer is etched away The sacrificial layer to obtain the first frame, that is, the first frame includes a multi-layer spaced isolation layer and a plurality of columns of first voltage lines, and the plurality of columns of first voltage lines are fixed on the isolation layer; The metal layers are stacked and alternately arranged to obtain a storage layer. The metal layer includes a ferroelectric layer (also called a ferroelectric thin film) and a plurality of second voltage lines. The ferroelectric layer surrounds the plurality of second voltage lines and the plurality of second voltage lines. The column first voltage line is located at the part of the metal layer, so that the first voltage line, the ferroelectric layer and the second voltage line form a metal-ferroelectric layer-metal MFM structure in the metal layer, and the second voltage line may be a word line.

In the above technical solution, the stacked layer includes a stacked and alternately arranged isolation layer and a sacrificial layer. Since the sacrificial layer is a material that is easy to corrode, a plurality of columns of first voltage lines and isolation grooves are arranged on the stacked layer, and in the etching When the sacrificial layer is removed, the etching difficulty of the first voltage line and the isolation groove can be greatly reduced; in addition, in the finally obtained memory layer, the metal layer and the isolation layer are stacked and alternately arranged, and the metal layer The first voltage line, the ferroelectric layer and the second voltage line form the memory cell of the MFM structure. Because the memory cell of the MFM structure can be equivalent to a ferroelectric diode, compared with the equivalent ferroelectric field effect tube of the MFIS structure memory cell , The structure is simple, and there is no interface between the ferroelectric layer and the insulating layer that is easy to trap charges, so that the interface defects are small, and the three-dimensional ferroelectric memory has better durability.

In a possible implementation of the first aspect, arranging multiple columns of first voltage lines in the stacked layer includes: arranging multiple columns of through holes in the stacked layer, for example, arranging in the stacked layer using a deep etching process Multiple columns of through holes, the multiple columns of through holes extend along the depth direction of the stacked layer, for example, one end of the multiple columns of through holes is located on the surface of the storage layer away from the substrate, and the other end of the multiple columns of through holes is along the stacked layer Extend in the depth direction; fill the first voltage lines in the multiple columns of through holes to obtain multiple columns of first voltage lines, for example, use a deposition method to grow conductive material on the sidewalls of the multiple columns of through holes until the conductive material is completely Fill up the multiple columns of through holes. In the foregoing possible implementation manners, since the sacrificial layer is made of easily corroded SiN _x and other materials, compared with the metal etching in the prior art, the difficulty of etching multiple columns of through holes is reduced; in addition, as the stacked layers The increase in the number will further reduce the difficulty of etching.

In a possible implementation of the first aspect, forming a metal layer stacked and alternately arranged with the isolation layer in the first frame to obtain the storage layer includes: growing a ferroelectric material on the surface of the first frame, the The thickness of the ferroelectric material is less than the first distance, the first distance is the distance between two adjacent isolation layers in the first frame; the conductive material is grown on the surface of the ferroelectric material, and the thickness of the conductive material and the ferroelectric The sum of the thickness of the material is greater than or equal to the distance between two adjacent isolation layers to obtain a storage layer matrix. The ferroelectric material between two adjacent isolation layers in the storage layer matrix forms a ferroelectric layer. The conductive material between two adjacent isolation layers forms a plurality of second voltage lines, and the ferroelectric layer and the plurality of second voltage lines form a metal layer; the ferroelectric material and conductive material on the surface of the storage layer substrate are removed, such as , Remove the ferroelectric material and conductive material on the side surface of the storage layer base (for example, a circle around the storage layer base) and the surface away from the substrate (for example, the upper surface of the storage layer base and in the isolation groove) to obtain The storage layer includes an isolation layer and a metal layer that are stacked and alternately arranged. In the foregoing possible implementation manners, since the sacrificial layer is a material that is easily corroded, when the sacrificial layer is etched away and the metal layer is formed, the etching difficulty can be greatly reduced.

In a possible implementation of the first aspect, any two adjacent columns of first voltage lines in the plurality of columns of first voltage lines are arranged at intervals. In the foregoing possible implementation manner, when any two adjacent columns of first voltage lines are arranged at intervals, multiple first voltage lines belonging to the same column can be located in the same area, and first voltage lines belonging to different columns are located in different areas. Therefore, it is convenient to provide isolation grooves between two adjacent columns of first voltage lines.

In a possible implementation of the first aspect, the method further includes: filling an electrically insulating material in the isolation groove; optionally, the electrically insulating material includes silicon oxide (SiO _x ). In the above possible implementation manners, by filling the isolation groove with an electrical insulating material, two adjacent columns of first voltage lines can be separated by the electrical insulating material, thereby avoiding interference between two adjacent columns of first voltage lines .

In a possible implementation of the first aspect, the wheel distance of the part of the first voltage line located in the metal layer is greater than the wheel distance of the part of the first voltage line located in the isolation layer, for example, the part of the first voltage line If the cross section is circular, the radius of the portion of the first voltage line located on the metal layer is larger than the radius of the portion of the first voltage line located on the isolation layer. In the foregoing possible implementation manners, the memory cell of the MFM structure formed by the first voltage line, the ferroelectric layer, and the second voltage line in the metal layer can have better performance, thereby further enabling the three-dimensional ferroelectric memory to have better performance. Performance.

In a possible implementation of the first aspect, the first voltage line or the second voltage line includes at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt) ), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO _x ), iridium (Ir), iridium oxide (IrO _x ), TaN (tantalum nitride), cobalt (Co), Aluminum (Al), copper (Cu), polysilicon (Si), a compound of silicon and metal. In the foregoing possible implementation manners, the flexibility and diversity of the first voltage line or the second voltage line can be improved.

In a possible implementation of the first aspect, the ferroelectric layer includes at least one of the following materials: hafnium dioxide (HfO ₂ ), doped HfO ₂ , lead zirconium titanate (PbZrTiO ₃ ), Doped PbZrTiO ₃ , strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ ), doped SrBi ₂ Ta ₂ O ₉ , lithium niobate (LiNbO ₃ ), doped LiNbO ₃ , tantalate Lithium (LiTaO ₃ ), doped LiTaO ₃ , bismuth ferrite (BiFeO ₃ ), doped BiFeO ₃ , barium titanate (BaTiO ₃ ), doped BaTiO ₃ ; optional, The above-mentioned dopant is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La); for example, doped HfO ₂ may be doped with Si, Zr, Y, Al, Gd, S , and at least one of La HfO ₂ thereof. In the above possible implementation manners, the flexibility and diversity of the ferroelectric layer can be improved.

In a possible implementation of the first aspect, the first voltage line is a bit line, and the second voltage line is a word line. The foregoing possible implementation manners can reduce the etching difficulty during the formation of the bit line and the word line.

In a possible implementation of the first aspect, the first voltage line is perpendicular to the second voltage line.

In a possible implementation of the first aspect, each of the plurality of columns of first voltage lines includes a plurality of first voltage lines, and the method further includes: forming an electrical connection layer on the storage layer, the The electrical connection layer is located on a side of the storage layer away from the substrate, and a plurality of first voltage lines are electrically connected in the electrical connection layer.

In a second aspect, a three-dimensional ferroelectric memory is provided. The three-dimensional ferroelectric memory includes: a substrate, where the substrate may refer to a silicon wafer, a die, or a silicon integrated circuit; located on the substrate The upper storage layer is provided with multiple columns of first voltage lines and isolation grooves located between any two adjacent columns of first voltage lines in the multiple columns of first voltage lines. Extend in the depth direction of the storage layer (for example, one end of the first voltage lines of the plurality of columns is located on the surface of the storage layer away from the substrate, and the other end of the multiple columns of first voltage lines is located on the surface of the storage layer close to the substrate), the isolation recess The groove penetrates the storage layer; wherein, the storage layer includes an isolation layer and a metal layer that are stacked and alternately arranged. The isolation layer may be an electrically insulating material and is used to isolate two adjacent metal layers. The electric layer and the plurality of second voltage lines, the ferroelectric layer surrounds the plurality of second voltage lines and the part of the plurality of columns of the first voltage lines located in the metal layer, so that the first voltage line, the ferroelectric layer and the second metal line are in the A metal-ferroelectric layer-metal MFM structure is formed in the metal layer, that is, the first voltage line, the ferroelectric layer, and the second voltage line form a memory cell of the MFM structure.

In the above technical solution, in the storage layer of the three-dimensional ferroelectric memory, the metal layer and the isolation layer are stacked and alternately arranged, and the first voltage line, the ferroelectric layer, and the second voltage line in the metal layer form a memory cell with an MFM structure, Since the memory cell of the MFM structure can be equivalent to a ferroelectric diode, compared with the equivalent ferroelectric field effect tube of the memory cell of the MFIS structure, the structure is simple, and there is no interface between the ferroelectric layer and the insulating layer that is easy to trap charges. The interface defect is small, thereby ensuring that the three-dimensional ferroelectric memory has better durability. In addition, the metal layer in the three-dimensional ferroelectric memory includes a ferroelectric layer and a plurality of second voltage lines, and the ferroelectric layer surrounds the plurality of second voltage lines and parts of the plurality of columns of the first voltage lines located in the metal layer. The reason is that the ferroelectric layer is formed in the process of forming the metal layer after the sacrificial layer in the isolation layer and the sacrificial layer stack structure is etched, which can greatly reduce the etching of the first voltage line and the isolation groove Difficulty, and at the same time, it can ensure the quality of ferroelectric layer growth, thereby ensuring the good performance of the memory cell and the three-dimensional ferroelectric memory.

In a possible implementation of the second aspect, any two adjacent first voltage lines in the multiple columns of first voltage lines are arranged at intervals, that is, the multiple first voltage lines belonging to the same column are located in the same area and belong to different The first voltage lines of the columns are located in different areas, so that it is convenient to provide isolation grooves between the first voltage lines of two adjacent columns.

In a possible implementation of the second aspect, the isolation groove is filled with an electrically insulating material; optionally, the electrically insulating material includes silicon oxide (SiO _x ). In the above possible implementation manners, by filling the isolation groove with an electrical insulating material, two adjacent columns of first voltage lines can be separated by the electrical insulating material, thereby avoiding interference between two adjacent columns of first voltage lines

In a possible implementation of the second aspect, the wheel distance of the part of the first voltage line located in the metal layer is larger than the wheel distance of the part of the first voltage line located in the isolation layer, for example, the part of the first voltage line If the cross section is circular, the radius of the portion of the first voltage line located on the metal layer is larger than the radius of the portion of the first voltage line located on the isolation layer.

In a possible implementation of the second aspect, the first voltage line or the second voltage line includes at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt) ), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO _x ), iridium (Ir), iridium oxide (IrO _x ), TaN (tantalum nitride), cobalt (Co), Aluminum (Al), copper (Cu), polysilicon (Si), a compound of silicon and metal.

In a possible implementation of the second aspect, the ferroelectric layer includes at least one of the following materials: hafnium dioxide (HfO ₂ ), doped HfO ₂ , lead zirconium titanate (PbZrTiO ₃ ), Doped PbZrTiO ₃ , strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ ), doped SrBi ₂ Ta ₂ O ₉ , lithium niobate (LiNbO ₃ ), doped LiNbO ₃ , tantalate Lithium (LiTaO ₃ ), doped LiTaO ₃ , bismuth ferrite (BiFeO ₃ ), doped BiFeO ₃ , barium titanate (BaTiO ₃ ), doped BaTiO ₃ ; optional, The above-mentioned dopant is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La); for example, doped HfO ₂ may be doped with Si, Zr, Y, Al, Gd, S , and at least one of La HfO ₂ thereof.

In a possible implementation of the second aspect, the first voltage line is a bit line, and the second voltage line is a word line.

In a possible implementation of the second aspect, the first voltage line is perpendicular to the second voltage line.

In a possible implementation manner of the second aspect, in a possible implementation manner of the second aspect, each of the plurality of columns of first voltage lines includes a plurality of first voltage lines, and the three-dimensional iron The electrical storage device further includes: an electrical connection layer on the storage layer, and a plurality of first voltage lines are electrically connected in the electrical connection layer.

In a third aspect, an electronic device is provided. The electronic device includes a circuit board and a three-dimensional ferroelectric memory connected to the circuit board. The three-dimensional ferroelectric memory is the foregoing second aspect or any possible implementation manner of the second aspect The provided three-dimensional ferroelectric memory.

In a fourth aspect, a method for manufacturing a three-dimensional ferroelectric memory is provided. The method includes: forming a storage layer on a substrate, where the substrate may be a silicon wafer, a die, or a silicon integrated circuit Etc., the storage layer includes a stacked and alternately arranged isolation layer and a polysilicon layer, the isolation layer may be an electrical insulating material and used to isolate two adjacent polysilicon layers, the polysilicon layer is a poly-Si layer, which is easy to corrode; The storage layer is provided with a ferroelectric layer and multiple columns of first voltage lines, the ferroelectric layer surrounds multiple columns of first voltage lines, and the multiple columns of first voltage lines extend along the depth direction of the storage layer (for example, multiple columns of first voltage lines One end is located on the surface of the storage layer away from the substrate, and the other end is located on the surface of the storage layer close to the substrate); an isolation groove penetrating the storage layer is formed between any two adjacent columns of first voltage lines in the plurality of columns of first voltage lines , Obtain multiple second voltage lines in the polysilicon layer, the first voltage line, the ferroelectric layer and the second voltage line form an MFM structure in the polysilicon layer, that is, the first voltage line, the ferroelectric layer and the second voltage line form the MFM Structure of the storage unit.

In the above technical solution, the storage layer includes stacked and alternately arranged isolation layers and polysilicon layers. Since the polysilicon layer is a material that is easily corroded, when multiple columns of first voltage lines and isolation grooves are arranged on the storage layer, the Reduce the difficulty of etching the first voltage line and the isolation groove by the etching process. In addition, the first voltage line, the ferroelectric layer, and the second voltage line in the polysilicon layer form the memory cell of the MFM structure. Since the memory cell of the MFM structure can be equivalent to a ferroelectric diode, it is equivalent to the memory cell of the MFIS structure. Compared with the electric field effect tube, the structure is simple, and there is no interface between the ferroelectric layer and the insulating layer that is easy to trap charges, so that the interface defects are small, and the three-dimensional ferroelectric memory has better durability.

In a possible implementation manner of the fourth aspect, arranging the ferroelectric layer and multiple columns of first voltage lines in the storage layer includes: arranging multiple columns of through holes in the storage layer, and the multiple columns of through holes are along the storage layer. For example, a deep etching process is used to provide multiple columns of through holes in the storage layer. One end of the multiple columns of through holes is located on the surface of the storage layer away from the substrate, and the other end of the multiple columns of through holes is located on the storage layer near the liner. The surface of the bottom; a ferroelectric layer is formed in the multiple columns of through holes, for example, a ferroelectric layer is grown on the sidewall of each through hole of the multiple columns of through holes; in the multiple columns of through holes after the ferroelectric layer is grown Fill the first voltage lines separately to obtain multiple columns of first voltage lines. For example, use a deposition method to grow conductive material on the surface of the ferroelectric layer until the conductive material completely fills the multiple columns of through holes, that is, multiple columns of first voltage lines are obtained. Voltage line. In the foregoing possible implementation manners, since the polysilicon layer is an easily corroded material, compared with the metal etching in the prior art, the difficulty of etching multiple columns of through holes is reduced; in addition, as the number of stacked layers increases , It will further reduce the difficulty of etching.

In a possible implementation of the fourth aspect, any two adjacent first voltage lines in the multiple columns of first voltage lines are arranged at intervals, that is, the multiple first voltage lines belonging to the same column are located in the same area and belong to different The first voltage lines of the columns are located in different areas, so that it is convenient to provide isolation grooves between the first voltage lines of two adjacent columns.

In a possible implementation of the fourth aspect, the isolation groove is filled with an electrically insulating material; optionally, the electrically insulating material includes silicon oxide (SiO _x ). In the above possible implementation manners, by filling the isolation groove with an electrical insulating material, two adjacent columns of first voltage lines can be separated by the electrical insulating material, thereby avoiding interference between two adjacent columns of first voltage lines .

In a possible implementation of the fourth aspect, the wheel distance of the part of the first voltage line located in the metal layer is greater than the wheel distance of the part of the first voltage line located in the isolation layer, for example, the part of the first voltage line If the cross section is circular, the radius of the portion of the first voltage line located on the metal layer is larger than the radius of the portion of the first voltage line located on the isolation layer. In the foregoing possible implementation manners, the memory cell of the MFM structure formed by the first voltage line, the ferroelectric layer, and the second voltage line in the metal layer can have better performance, thereby further enabling the three-dimensional ferroelectric memory to have better performance. Performance.

In a possible implementation of the fourth aspect, the first voltage line or the second voltage line includes at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt ), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO _x ), iridium (Ir), iridium oxide (IrO _x ), TaN (tantalum nitride), cobalt (Co), Aluminum (Al), copper (Cu), polysilicon (Si), a compound of silicon and metal. In the foregoing possible implementation manners, the flexibility and diversity of the first voltage line or the second voltage line can be improved.

In a possible implementation of the fourth aspect, the ferroelectric layer includes at least one of the following materials: hafnium dioxide (HfO ₂ ), doped HfO ₂ , lead zirconium titanate (PbZrTiO ₃ ), Doped PbZrTiO ₃ , strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ ), doped SrBi ₂ Ta ₂ O ₉ , lithium niobate (LiNbO ₃ ), doped LiNbO ₃ , tantalate Lithium (LiTaO ₃ ), doped LiTaO ₃ , bismuth ferrite (BiFeO ₃ ), doped BiFeO ₃ , barium titanate (BaTiO ₃ ), doped BaTiO ₃ ; optional, The above-mentioned dopant is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La); for example, doped HfO ₂ may be doped with Si, Zr, Y, Al, Gd, S , and at least one of La HfO ₂ thereof. In the above possible implementation manners, the flexibility and diversity of the ferroelectric layer can be improved.

In a possible implementation of the fourth aspect, the first voltage line is a bit line, and the second voltage line is a word line. The foregoing possible implementation manners can reduce the etching difficulty during the formation of the bit line and the word line.

In a possible implementation manner of the fourth aspect, the first voltage line is perpendicular to the second voltage line.

In a possible implementation manner of the fourth aspect, each of the plurality of columns of first voltage lines includes a plurality of first voltage lines, and the method further includes: forming an electrical connection layer on the storage layer, the electrical The connection layer is located on a side of the storage layer away from the substrate, and a plurality of first voltage lines are electrically connected in the electrical connection layer.

In a fifth aspect, a three-dimensional ferroelectric memory is provided. The three-dimensional ferroelectric memory includes: a substrate, where the substrate may refer to a silicon wafer, a die, or a silicon integrated circuit, etc., located on the substrate The storage layer of the storage layer is provided with a ferroelectric layer (also called a ferroelectric thin film) and multiple columns of first voltage lines. The ferroelectric layer surrounds multiple columns of first voltage lines, and the multiple columns of first voltage lines run along the storage The layer extends in the depth direction (for example, one end of the multiple columns of first voltage lines is located on the surface of the storage layer away from the substrate, and the other end of the multiple columns of first voltage lines is located on the surface of the storage layer close to the substrate); wherein the storage layer includes Stacked and alternately arranged isolation layers and polysilicon (poly-Si) layers, the isolation layer may be an electrical insulating material and used to isolate two adjacent polysilicon layers, the polysilicon layer is a poly-Si layer, which is easy to corrode; in addition, The storage layer is provided with isolation grooves located between any two adjacent columns of the first voltage lines in the plurality of columns of first voltage lines, the isolation grooves penetrate the storage layer, and the polysilicon layer is provided with a plurality of second voltage lines, And the first voltage line, the ferroelectric layer and the second metal line form a metal-ferroelectric layer-metal MFM structure in the polysilicon layer, that is, the first voltage line, the ferroelectric layer and the second voltage line form a memory cell of the MFM structure.

In a possible implementation manner of the fifth aspect, any two adjacent first voltage lines in the multiple columns of first voltage lines are arranged at intervals, that is, the multiple first voltage lines belonging to the same column are located in the same area and belong to different The first voltage lines of the columns are located in different areas, so that it is convenient to provide isolation grooves between the first voltage lines of two adjacent columns.

In a possible implementation of the fifth aspect, the isolation groove is filled with electrically insulating material, so that two adjacent columns of first voltage lines are separated by the electrically insulating material, thereby avoiding two adjacent columns of first voltage lines Interference occurs between them; optionally, the electrical insulating material includes silicon oxide (SiO _x ).

In a possible implementation manner of the fifth aspect, the part of the first voltage line located in the metal layer has a larger wheel distance than the part of the first voltage line located in the isolation layer, for example, the part of the first voltage line If the cross section is circular, the radius of the portion of the first voltage line located on the metal layer is larger than the radius of the portion of the first voltage line located on the isolation layer.

In a possible implementation of the fifth aspect, the first voltage line or the second voltage line includes at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt) ), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO _x ), iridium (Ir), iridium oxide (IrO _x ), TaN (tantalum nitride), cobalt (Co), Aluminum (Al), copper (Cu), polysilicon (Si), a compound of silicon and metal.

In a possible implementation of the fifth aspect, the ferroelectric layer includes at least one of the following materials: hafnium dioxide (HfO ₂ ), doped HfO ₂ , lead zirconium titanate (PbZrTiO ₃ ), Doped PbZrTiO ₃ , strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ ), doped SrBi ₂ Ta ₂ O ₉ , lithium niobate (LiNbO ₃ ), doped LiNbO ₃ , tantalate Lithium (LiTaO ₃ ), doped LiTaO ₃ , bismuth ferrite (BiFeO ₃ ), doped BiFeO ₃ , barium titanate (BaTiO ₃ ), doped BaTiO ₃ ; optional, The above-mentioned dopant is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La); for example, doped HfO ₂ may be doped with Si, Zr, Y, Al, Gd, S , and at least one of La HfO ₂ thereof.

In a possible implementation of the fifth aspect, the first voltage line is a bit line, and the second voltage line is a word line.

In a possible implementation of the fifth aspect, the first voltage line is perpendicular to the second voltage line.

In a possible implementation of the fifth aspect, each of the plurality of columns of first voltage lines includes a plurality of first voltage lines, and the three-dimensional ferroelectric memory further includes: an electrical connection layer located on the storage layer The electrical connection layer is located on the side of the storage layer away from the substrate, and the plurality of first voltage lines are electrically connected in the electrical connection layer.

In a sixth aspect, an electronic device is provided. The electronic device includes a circuit board and a three-dimensional ferroelectric memory connected to the circuit board, and the three-dimensional ferroelectric memory is any possible implementation manner of the above fifth aspect or the fifth aspect The provided three-dimensional ferroelectric memory.

It is understandable that any of the three-dimensional ferroelectric memory and electronic equipment provided above includes the same or corresponding features in the manufacturing method of the three-dimensional ferroelectric memory provided above, and therefore, the beneficial effects that can be achieved Reference may be made to the beneficial effects of the methods provided above, which will not be repeated here.

Description of the drawings

FIG. 1 is a schematic structural diagram of a storage system provided by an embodiment of the application;

2 is a schematic structural diagram of a three-dimensional ferroelectric memory provided by an embodiment of the application;

3 is a schematic structural diagram of another three-dimensional ferroelectric memory provided by an embodiment of the application;

FIG. 4 is a schematic structural diagram of a storage unit provided by an embodiment of the application;

5 is a schematic structural diagram of yet another three-dimensional ferroelectric memory provided by an embodiment of the application;

6 is a schematic structural diagram of another three-dimensional ferroelectric memory provided by an embodiment of the application;

FIG. 7 is a schematic structural diagram of yet another three-dimensional ferroelectric memory provided by an embodiment of the application;

FIG. 8 is an equivalent circuit diagram of a three-dimensional ferroelectric memory provided by an embodiment of the application;

FIG. 9 is a schematic diagram of the energy band of a ferroelectric layer provided by an embodiment of the application;

FIG. 10 is a schematic flowchart of a method for manufacturing a three-dimensional ferroelectric memory according to an embodiment of the application;

FIG. 11 is a schematic diagram of manufacturing a three-dimensional ferroelectric memory according to an embodiment of the application;

12 is a schematic structural diagram of another three-dimensional ferroelectric memory provided by an embodiment of the application;

FIG. 13 is a schematic structural diagram of yet another three-dimensional ferroelectric memory provided by an embodiment of this application;

14 is a schematic structural diagram of another three-dimensional ferroelectric memory provided by an embodiment of the application;

15 is a schematic structural diagram of yet another three-dimensional ferroelectric memory provided by an embodiment of the application;

16 is a schematic flowchart of another method for manufacturing a three-dimensional ferroelectric memory according to an embodiment of the application;

FIG. 17 is a schematic diagram of manufacturing another three-dimensional ferroelectric memory provided by an embodiment of the application.

Detailed ways

The production and use of each embodiment will be discussed in detail below. However, it should be understood that many applicable inventive concepts provided in this application can be implemented in a variety of specific environments. The specific embodiments discussed only illustrate specific ways to implement and use the description and the technology, and do not limit the scope of the application.

Unless otherwise defined, all scientific and technological terms used herein have the same meanings as those commonly known to those of ordinary skill in the art.

Each circuit or other component can be described or referred to as "used to" perform one or more tasks. In this context, "used to" is used to imply structure by indicating that the circuit/component includes a structure (such as a circuit system) that performs one or more tasks during operation. Therefore, even when the specified circuit/component is currently inoperable (e.g., not opened), the circuit/component can be said to be used to perform the task. Circuits/components used with the term "for" include hardware, such as circuits that perform operations, and the like.

The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In this application, "at least one" refers to one or more, and "multiple" refers to two or more. "And/or" describes the association relationship of the associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A alone exists, A and B exist at the same time, and B exists alone, where A, B can be singular or plural. The character "/" generally indicates that the associated objects before and after are in an "or" relationship. "The following at least one item (a)" or similar expressions refers to any combination of these items, including any combination of a single item (a) or a plurality of items (a). For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c or a, b and c, where a, b, and c can be It can be single or multiple. In addition, in the embodiments of the present application, words such as "first" and "second" do not limit the quantity and order.

It should be noted that in this application, words such as "exemplary" or "for example" are used to represent examples, illustrations, or illustrations. Any embodiment or design solution described as "exemplary" or "for example" in this application should not be construed as being more preferable or advantageous than other embodiments or design solutions. To be precise, words such as "exemplary" or "for example" are used to present related concepts in a specific manner.

The technical solution of this application can be applied to various storage systems using three-dimensional ferroelectric memory. For example, the technical solution of this application can be applied to a computer, and can also be applied to a storage system including a memory or a processor and a memory. The processor may be a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor (digital signal processor), a neural network processor, etc.

Figure 1 is a schematic structural diagram of a storage system provided by an embodiment of the application. The storage system may include a storage device, and the storage device may be a three-dimensional ferroelectric memory; optionally, the storage system may also include a CPU and a buffer ( cache) and controllers, etc.

In an embodiment, as shown in (a) of FIG. 1, the storage system may be an embedded memory, and the storage system includes an integrated CPU, a buffer, and a storage device. In another embodiment, as shown in FIG. 1(b), the storage system can be used as an independent memory. The storage system includes an integrated CPU, a buffer, a controller, and a storage device. The storage The device is coupled with the buffer and the CPU through the controller. In another embodiment, as shown in (c) in FIG. 1, the storage system includes a storage device, and an integrated CPU, a buffer, a controller, and a dynamic random access memory (DRAM). The storage device can be used as an external storage device to be coupled to the DRAM; wherein, the DRAM is coupled to the buffer and the CPU through the controller. The CPU in the various memories shown in Fig. 1 can also be replaced with a CPU core (core).

FIG. 2 is a schematic structural diagram of a three-dimensional ferroelectric memory provided by an embodiment of this application. (a) in FIG. 2 is a top view of the three-dimensional ferroelectric memory, and (b) in FIG. 2 is (a) in FIG. 2 The top view shown is a vertical downward cross-sectional view along the line HH'. Referring to FIG. 2, the three-dimensional ferroelectric memory includes: a substrate 1. The substrate 1 may generally refer to a silicon wafer, a die or a silicon integrated circuit with a logic circuit function, or a logic circuit. Functional semiconductors, etc.; the storage layer 2 on the substrate 1. The storage layer 2 includes a stacked and alternately arranged isolation layer 21 and a metal layer 22. The isolation layer 21 may be an electrically insulating material for isolating two adjacent metals Layer 22. Fig. 3(a) is a front view of the three-dimensional ferroelectric memory, and Fig. 3(b) is a side view of the three-dimensional ferroelectric memory.

Wherein, the storage layer 2 is provided with multiple columns of first voltage lines 23, and isolation grooves 24 located between any two adjacent columns of first voltage lines 23 in the multiple columns of first voltage lines 23, and multiple columns of first voltage lines 23 The line 23 extends along the depth direction of the storage layer 2 (for example, one end of the multiple columns of first voltage lines 23 is located on the surface of the storage layer 2 away from the substrate 1, and the other end of the multiple columns of first voltage lines 23 runs along the surface of the storage layer 2. Extending in the depth direction, for example, extending to the surface of the storage layer 2 close to the substrate 1 ), the isolation groove 24 penetrates the storage layer 2.

In addition, the metal layer 22 is provided with a ferroelectric layer 25 and a plurality of second voltage lines 26, and the ferroelectric layer 25 (also referred to as a ferroelectric thin film) surrounds the plurality of second voltage lines 26 and a plurality of columns of first voltage lines 23. It is located at the part of the metal layer 22, so that the first voltage line 23, the ferroelectric layer 25 and the second voltage line 26 form a metal-ferroelectrics-metal (MFM) structure in the metal layer 22. As shown in FIG. 4, it is a schematic diagram of the memory cell of the MFM structure. The memory cell of the MFM structure can be equivalent to a series connection of a ferroelectric diode D and a resistor R. For specific related descriptions of the read and write principle of the storage unit, please refer to the related description of FIG. 9 below, and details are not repeated here in the embodiment of the present application.

In one embodiment, the isolation groove 24 is filled with an electrical insulating material, and the electrical insulating material is used to achieve electrical insulation between any two adjacent columns of the first voltage lines 23 among the multiple columns of the first voltage lines 23.

In another embodiment, any two adjacent columns of first voltage lines 23 among the plurality of columns of first voltage lines 23 are arranged at intervals, and each column of first voltage lines 23 may include multiple first voltage lines 23. Optionally, the cross-section of the first voltage line 23 can be any of closed figures such as a circle, an ellipse, or a polygon. For example, the polygon can be a triangle, a quadrilateral, a pentagon, a hexagon, etc. The application embodiment does not impose specific restrictions on this.

Exemplarily, as shown in FIG. 5, the multiple columns of first voltage lines 23 may include two columns of first voltage lines 23, the two columns of first voltage lines 23 may be arranged in parallel, and the two columns of first voltage lines 23 are arranged between them. There is an isolation groove 24. (A) in FIG. 5 takes each column of the first voltage line 23 including three first voltage lines 23, and the cross section of the first voltage line 23 is circular as an example for illustration; (b) in FIG. The column first voltage line 23 includes three first voltage lines 23, and the cross section of the first voltage line 23 is quadrangular as an example; A voltage line 23, and the cross section of the first voltage line 23 is circular as an example for description.

Further, as shown in FIG. 6, the part of the first voltage line 23 located on the metal layer 22 has a larger wheel distance than the part of the first voltage line 23 located on the isolation layer 21. For example, if the cross section of the first voltage line 23 is circular, the radius of the portion of the first voltage line 23 located on the metal layer 22 is larger than the radius of the portion of the first voltage line 23 located on the isolation layer 21. Fig. 6(a) is a top view of the three-dimensional ferroelectric memory, and Fig. 6(b) is a cross-sectional view of the top view shown in Fig. 6(a) perpendicularly downward along the line HH'.

In an embodiment, the first voltage line 23 may include at least one of the following conductive materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), Tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO _x ), iridium (Ir), iridium oxide (IrO _x ), TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper ( Cu), polysilicon (Si). Exemplarily, the first voltage line 23 may be made of conductive materials with good conductivity, such as W, Al, and Cu, so as to reduce the voltage drop (IR drop) on the first voltage line 23 and reduce the first voltage line. The partial pressure of 23 improves the integration and storage density of the three-dimensional ferroelectric memory.

Wherein, when the first voltage line 23 includes at least two conductive materials among the above conductive materials, the at least two conductive materials may be separated, and each conductive material forms a part of the first voltage line 23, for example, the first A voltage line 23 can include multiple layers along the axial direction away from the axis, and each layer corresponds to a conductive material, so that different conductive materials can be distinguished in the cross section of the first voltage line 23, as shown in FIG. 5 As shown in (b); or, the at least two conductive materials may be mixed together to form the first voltage line 23, so that the at least two conductive materials cannot be distinguished in the cross section of the first voltage line 23, such as As shown in Figure 5 (a).

Similarly, the second voltage line 26 may also include at least one of the following conductive materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO _x ), iridium (Ir), iridium oxide (IrO _x ), TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper (Cu), Polysilicon (Si), a compound of silicon and metal. Exemplarily, the second voltage line 26 can also be made of conductive materials with good conductivity, such as W, Al, and Cu, so as to reduce the IR drop on the second voltage line 26 and reduce the second voltage. The voltage division of the line 26 improves the integration and storage density of the three-dimensional ferroelectric memory. Wherein, when the second voltage line 26 includes at least two conductive materials among the above conductive materials, the at least two conductive materials may be separated, and each conductive material forms a part of the second voltage line 26, for example, the first The second voltage line 26 may include multiple layers along the direction close to the ferroelectric layer 25 and away from the ferroelectric layer 25, and each layer corresponds to one conductive material; or, the at least two conductive materials may be mixed together to form the second voltage Line 26.

It should be noted that x in different materials herein can be different values, for example, _x in SiO x can be 2, and _x in RuO x can be 4, which is not specifically limited in the embodiment of the present application.

In another embodiment, the ferroelectric layer 25 may include at least one of the following materials: hafnium dioxide (HfO ₂ ), doped HfO ₂ , lead zirconium titanate (PbZrTiO ₃ ), doped PbZrTiO ₃ , strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ ), doped SrBi ₂ Ta ₂ O ₉ , lithium niobate (LiNbO ₃ ), doped LiNbO3, lithium tantalate (LiTaO ₃₎ with dopant of LiTaO _3, bismuth ferrate (BiFeO _3), has dopant BiFeO _3, barium titanate (BaTiO _3), there is BaTiO ₃ dopant. Wherein, the above-mentioned dopant is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La); for example, the dopant may be doped with Si, Zr, Y, Al, Gd, S , and at least one of La HfO ₂ of HfO _2.

Furthermore, as shown in FIG. 7, the three-dimensional ferroelectric memory further includes an electrical connection layer 3, and the electrical connection layer 3 is located on the storage layer 2 and away from the substrate 1. Wherein, each column of the first voltage lines 23 in the plurality of columns of first voltage lines 23 includes a plurality of first voltage lines 23, and the plurality of first voltage lines 23 are electrically connected in the electrical connection layer 3.

In practical applications, the first voltage line 23 may be a bit line (BL), and the second voltage line 26 may be a word line (WL), so that the multiple columns of first voltage lines 23 are multiple columns of BL, Each column BL may include a plurality of BLs, and the plurality of second voltage lines 26 are a plurality of WLs. Optionally, the first voltage line 23 and the second voltage line 26 are perpendicular, that is, BL and WL are perpendicular.

As shown in FIG. 8, an equivalent circuit diagram of a three-dimensional ferroelectric memory provided by an embodiment of this application. In the three-dimensional ferroelectric memory, the storage layer 2 includes three metal layers 22, and the multiple columns of BL include five columns of BL and each The column BL includes four BLs from B0 to B3, and the multiple WLs include 4 WLs and are respectively denoted as W0 to W3 as an example for description. In FIG. 7, each metal layer 22 in the storage layer 2 of the three-dimensional ferroelectric memory may include a plurality of memory cells of MFM structure (ie, a memory cell composed of WL-ferroelectric layer-BL), and each memory cell It can be equivalent to a series of a resistor R and a ferroelectric diode D. Further, the multiple columns of BL and multiple WLs in the three-dimensional ferroelectric memory can be gated or disconnected through transistor switches. For example, a transistor is connected in series to each BL of the multiple columns of BL for gate or disconnection. Turn on the BL, connect a transistor in series to each of the multiple WLs to gate or disconnect the WL, and control the read and write operations of a memory cell by controlling one BL and one WL. Optionally, a transistor is connected in series to each BL of the multi-column BL, which can also be replaced by: each column BL of the multi-column BL is connected together by a metal wire and then a transistor is connected in series, so that this transistor can be used for simultaneous selection. Turn on or off the column BL.

Wherein, the read and write operations of each memory cell in the three-dimensional ferroelectric memory can be implemented by applying voltage on the word line and the bit line of the memory cell. Specifically, as shown in Figure 9, when a "1" is written in the memory cell, the voltage applied across the memory cell is greater than the coercive voltage of the ferroelectric layer, and the direction is the first electric field direction (Figure 9 represents the direction from left to right), the polarization P of the ferroelectric layer is reversed, and the polarization direction is the same as the direction of the first electric field. At this time, holes are gathered near the negative ions on the left side of the ferroelectric layer to make the contact potential The barrier φ1 is increased to form a Schottky contact, and electrons are gathered near the positive ions on the right side, so that the contact barrier φ2 is reduced, forming an ohmic contact. At this time, the MFM structure formed by the ferroelectric layer, the word line and the bit line has a ferroelectric diode with conductivity in the first electric field direction. When "0" is written in the memory cell, the voltage value applied at both ends of the memory cell is greater than the coercive voltage of the ferroelectric layer, and the direction is the second electric field direction (that is, the opposite of the first electric field direction). Direction), the polarization intensity P of the ferroelectric layer is reversed, and the polarization direction is the same as the direction of the second electric field. At this time, electrons gather near the positive ions on the left side of the ferroelectric layer, which reduces the contact barrier φ1, forming an ohmic Contact, and holes gather near the negative ions on the right side to increase the contact barrier φ2, forming a Schottky contact. The MFM structure formed by the ferroelectric layer, the word line and the bit line becomes a ferroelectric diode with conductivity in the second electric field direction. When reading the data stored in the memory cell, the voltage value applied at both ends of the memory cell may be less than the coercive voltage of the ferroelectric layer and greater than the threshold voltage (Threshold Voltage, V _th ) that allows electrons to cross the barrier. The direction is the first electric field direction. At this time, read the current value of the ferroelectric diode and determine whether the ferroelectric diode is conductive or the conductive direction. If the conductive direction is the same as the first electric field direction, it is determined that the storage unit is stored The data of is "1", if the conduction direction is the same as the direction of the second electric field, it is determined that the data stored in the memory cell is "0". The above-mentioned coercive voltage of the ferroelectric layer refers to the critical voltage at which the polarization direction of the ferroelectric layer is reversed.

In the embodiment of the present application, the three-dimensional ferroelectric memory includes a storage layer 2 of stacked and alternately arranged isolation layers 21 and metal layers 22. The storage layer 2 is provided with multiple columns of first voltage lines 23, and the metal layer 22 is provided with The ferroelectric layer 25 and the plurality of second voltage lines 26, the ferroelectric layer 25 surrounds the plurality of second voltage lines 26 and the plurality of columns of the first voltage lines 23 in the part of the metal layer 22, thereby forming the MFM structure in the metal layer 22 The memory cell, because the memory cell of the MFM structure has better durability, the three-dimensional ferroelectric memory has better durability. In addition, the ferroelectric layer 25 is arranged in the metal layer 22, so that the thickness of the ferroelectric layer 25 is not affected by the surrounding environment during growth, and the consistency of the thickness of the ferroelectric layer is ensured, thereby ensuring the memory cell and the three-dimensional ferroelectric memory. The goodness of the performance.

FIG. 10 is a schematic flowchart of a method for manufacturing a three-dimensional ferroelectric memory according to an embodiment of the application. The three-dimensional ferroelectric memory may be the three-dimensional ferroelectric memory described in any of the above-mentioned FIGS. 2 to 8. As shown in Figure 10, the method may include the following steps. Fig. 11 is a cross-sectional view of the three-dimensional ferroelectric memory in the process of manufacturing the three-dimensional ferroelectric memory.

S31: A stacked layer 02 is formed on the substrate 1. The stacked layer 02 includes an isolation layer 21 and a sacrificial layer 022 stacked and alternately arranged. As shown in Figure 11 (a).

Among them, the substrate 1 may generally refer to a silicon wafer, a die or a silicon integrated circuit with a logic circuit function, or a semiconductor with a logic circuit function, or the like. The isolation layer 21 may be an electrically insulating material for isolating two adjacent sacrificial layers 022, for example, the isolation layer 21 may be SiO _x . The sacrificial layer 022 may refer to a layer that will be removed or sacrificed later, and the sacrificial layer 022 may be a material that is easily corroded. For example, the sacrificial layer 022 may be silicon nitride (SiN _x ).

Specifically, an isolation layer 21 is deposited on the substrate 1, and then a sacrificial layer 022 is deposited on the isolation layer 21, and then the isolation layer 21 and the sacrificial layer 022 are sequentially deposited in the above-mentioned manner until a multilayer stack is obtained. By setting the isolation layer 21 and the sacrificial layer 022, the stacked layer 02 is obtained. The number of layers of the isolation layer 21 can be one more layer than the number of layers of the sacrificial layer 022, and the specific number of layers of the isolation layer 21 and the sacrificial layer 022 can be set according to actual conditions, which is not specifically limited in the embodiment of the present application. For example, (a) in FIG. 11 takes the example that the number of isolation layers 21 included in the stacked layer 02 is 4 and the number of sacrificial layers 022 is 3 as an example.

S32: A plurality of columns of first voltage lines 23 are provided in the stacked layer 02, and the columns of first voltage lines 23 extend along the depth direction of the stacked layer 02. For example, one end of the multiple columns of first voltage lines 23 is located on the surface of the stacked layer 02 away from the substrate 1, and the other ends of the multiple columns of first voltage lines 23 are located on the surface of the stacked layer 02 close to the substrate 1. As shown in Figure 11 (b) and (c).

Wherein, any two adjacent columns of first voltage lines 23 among the plurality of columns of first voltage lines 23 may be arranged at intervals, and each column of first voltage lines 23 may include multiple first voltage lines 23. Optionally, the cross-section of the first voltage line 23 can be any of closed figures such as a circle, an ellipse, or a polygon. For example, the polygon can be a triangle, a quadrilateral, a pentagon, a hexagon, etc. The application embodiment does not impose specific restrictions on this.

Specifically, multiple columns of through holes are provided in the stacked layer 02. For example, a deep etching process is used to provide multiple columns of through holes in the stacked layer 02. One end of the multiple columns of through holes is located on the surface of the stacked layer 02 away from the substrate 1. The other ends of the multiple columns of through holes extend along the depth direction of the stacked layer 02, for example, the other ends of the multiple columns of first voltage lines 23 are located on the surface of the stacked layer 02 close to the substrate 1, as shown in (b) in FIG. 11 ; Fill the first voltage lines in the multiple columns of through holes respectively to obtain multiple columns of first voltage lines 23, for example, using a deposition method to grow conductive material on the sidewalls of the multiple columns of through holes until the conductive material is completely filled These multiple columns of through holes obtain multiple columns of first voltage lines 23, as shown in (c) in FIG. 11. Since the sacrificial layer 022 is a SiO _x corrosive like, as compared with the prior art metal etch, reduce the difficulty of etching a plurality of rows of through holes.

Optionally, the first voltage line 23 may include at least one of the following conductive materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO _x ), iridium (Ir), iridium oxide (IrO _x ), TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper (Cu), Polysilicon (Si). Wherein, when the first voltage line 23 includes at least two conductive materials among the above conductive materials, the at least two conductive materials may be separated, and each conductive material forms a part of the first voltage line 23, for example, the first A voltage line 23 includes two conductive materials. When the conductive materials are filled in the multiple through holes, the first conductive material can be grown on the sidewalls of the multiple through holes, and then the conductive material of the first conductive material can be grown on the sidewalls of the multiple through holes. The second conductive material is grown on the surface; or, the at least two conductive materials can be mixed together to form the first voltage line 23. For example, if the first voltage line 23 includes two conductive materials, then the plurality of through holes When the conductive materials are filled separately, the two conductive materials can be mixed, and the mixed conductive material can be grown on the sidewalls of the multiple through holes.

In one embodiment, the part of the first voltage line 23 that is located on the sacrificial layer 022 has an axial distance greater than that of the part of the first voltage line that is located on the isolation layer 21. Specifically, when multiple rows of through holes are provided in the stacked layer 02, after the deep etching process is used to form the multiple rows of through holes in the stacked layer 02, the lateral wet etching technique is used to place the multiple rows of through holes in the isolation layer. The position of 21 is etched laterally, so that the part of the through-holes in the plurality of rows of through-holes located on the sacrificial layer 022 has a greater wheel distance than the part of the through-holes of the multiple rows of through-holes on the isolation layer 21. Afterwards, conductive material can be grown in the multiple columns of through holes after the lateral etching to obtain multiple columns of first voltage lines 23, and the part of the first voltage lines 23 located in the sacrificial layer 022 has a larger wheel distance than the first voltage lines. The wheel distance of the part located in the isolation layer 21.

S33: forming an isolation groove 24 penetrating the stacked layer 02 between any two adjacent first voltage lines 23 among the plurality of columns of first voltage lines 23. As shown in Figure 11 (d).

Specifically, the deep etching process is used to provide isolation grooves 24 penetrating through the stack 02 between any two adjacent columns of the first voltage lines 23 among the multiple columns of first voltage lines 23, so as to connect any two adjacent columns of first voltage lines 23. The voltage lines 23 are physically separated; wherein, one end of the isolation groove 24 may be located on the surface of the stacked layer 02 away from the substrate 1, and the other end of the isolation groove 24 may be located on the surface of the stacked layer 02 close to the substrate 1. Since the sacrificial layer 022 is corrosive such as SiN _x, metal etching as compared with the prior art, reducing the difficulty of etching the isolation recess.

S34: The sacrificial layer 022 in the stacked layer 02 is etched away to obtain the first frame 03. As shown in Figure 11 (e).

Specifically, when the sacrificial layer 022 in the stacked layer 02 is etched away, the sacrificial layer 022 in the stacked layer 02 can be removed by a lateral wet etching technique. After the sacrificial layer 022 is removed, the first frame 03 obtained includes the above-mentioned multiple layers. The isolation layer 21 and multiple columns of first voltage lines 23 are separated by layers. The multiple columns of first voltage lines 23 are fixed on the isolation layer 21. The surfaces of the portions of the multiple columns of first voltage lines 23 that were originally located on the sacrificial layer 022 are exposed to the outside. , Can provide a growth surface or substrate for the subsequent growth of the ferroelectric layer.

S35: forming a metal layer 22 stacked and alternately arranged with the isolation layer 21 in the first frame 03 to obtain the storage layer 2. As shown in Fig. 11 (f) to (h).

Specifically, a ferroelectric material is formed on the surface of the first frame 03, for example, the ferroelectric material is grown on the surface of the first frame 03 by a deposition method, the thickness of the ferroelectric material is smaller than the first distance, and the first distance is the first distance. The distance between two adjacent isolation layers 21 in the frame 03 is as shown in (f) in FIG. 11. Specifically, the ferroelectric material can not only cover the surface corresponding to the etched sacrificial layer 022 in the first frame 03, that is, the surface of the recessed part in the first frame 03, but also cover the peripheral surface of the first frame 03, so that The exposed surface of the first frame 03 is covered with ferroelectric material. After the ferroelectric material is grown, a conductive material is formed on the surface of the ferroelectric material. For example, a conductive material is grown on the surface of the ferroelectric material by a deposition method. The thickness of the conductive material and the thickness of the ferroelectric material are greater than or It is equal to the first distance to obtain the storage layer substrate 04. Specifically, the conductive material may cover the above-mentioned ferroelectric material to wrap the surface of the first frame 03 after the ferroelectric material is grown, except for the surface in contact with the substrate 1. The ferroelectric material between two adjacent isolation layers 21 in the storage layer base 04 forms a ferroelectric layer 25, and the conductive material between two adjacent isolation layers forms a plurality of second voltage lines 26, and the ferroelectric layer 25 A metal layer 22 is formed with a plurality of second voltage lines 26, as shown in (g) in FIG. 11; the ferroelectric and conductive materials on the surface of the storage layer base 04 are removed to obtain the storage layer 2, for example, by dry etching The etching process removes the ferroelectric material on the side surface of the storage layer base 04 (for example, a circle around the storage layer base 04) and the surface away from the substrate 1 (for example, the upper surface of the storage layer base 04 and the isolation groove 24). And the conductive material is removed to obtain the storage layer 2. The storage layer 2 includes an isolation layer 21 and a metal layer 22 stacked and alternately arranged, as shown in (h) in FIG. 11.

Optionally, the second voltage line 26 may include at least one of the following conductive materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO _x ), iridium (Ir), iridium oxide (IrO _x ), TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper (Cu), Polysilicon (Si), a compound of silicon and metal. Wherein, when the second voltage line 26 includes at least two conductive materials among the above conductive materials, the at least two conductive materials may be separated, and each conductive material forms a part of the second voltage line 26, for example, the first The second voltage line 26 may include multiple layers along the direction from being close to the ferroelectric layer 25 to away from the ferroelectric layer 25, each layer corresponding to one conductive material, so that different conductive materials can be used in sequence when forming the second voltage line 26. The second voltage line 26 is formed by growing; or, the at least two conductive materials may be mixed together to form the second voltage line 26, that is, the second voltage line 26 is formed by growing the mixed conductive material.

Further, the method may further include: filling the isolation groove 24 with an electrically insulating material, and the electrically insulating material may be used to realize the connection between any two adjacent columns of the first voltage lines 23 among the plurality of columns of first voltage lines 23. Electrical insulation. Exemplarily, the electrically insulating material may be silicon oxide (SiO _x ).

In another embodiment, each of the plurality of columns of first voltage lines 23 includes a plurality of first voltage lines 23, and the method further includes: forming an electrical connection layer 3 on the storage layer 2 to electrically connect The layer 3 is located on the side of the storage layer 2 away from the substrate 1, and a plurality of first voltage lines 23 are electrically connected in the electrical connection layer 3.

It should be noted that the relevant descriptions of the three-dimensional ferroelectric memory provided in FIGS. 2 to 9 above can be cited in the manufacturing method of the three-dimensional ferroelectric memory, and the details are not repeated here in the embodiments of the present application.

In the method for manufacturing a three-dimensional ferroelectric memory provided by the embodiment of the present application, the stacked layer 02 formed on the substrate 1 includes the isolation layer 21 and the sacrificial layer 022 stacked and alternately arranged. Since the sacrificial layer 022 is an easily corroded material, When multiple columns of first voltage lines 23 and isolation grooves 24 are arranged in the stack layer 02, and the metal layer including the ferroelectric layer 25 and the multiple second voltage lines 26 is formed after the sacrificial layer 022 is etched away, it can greatly Reduce the difficulty of etching through holes and isolation grooves by etching processes. At the same time, the ferroelectric layer 25 in the metal layer 22 surrounds the plurality of second voltage lines 26 and the plurality of columns of the first voltage lines 23 at the portion of the metal layer 22 to form a memory cell of the MFM structure in the metal layer 22. Due to the MFM structure The memory cell has better durability, so that the three-dimensional ferroelectric memory has better durability. In addition, the ferroelectric layer 25 is formed on the surface of the first frame 03 obtained after the sacrificial layer 022 is removed, that is, the first frame 03 provides the first voltage line 23 required for the subsequent growth of the ferroelectric layer and is exposed in the metal layer 22 In order to ensure the quality of the growth of the ferroelectric layer, the performance of the memory cell and the three-dimensional ferroelectric memory is ensured.

FIG. 12 is a schematic structural diagram of another three-dimensional ferroelectric memory provided by an embodiment of the application. (a) in FIG. 12 is a top view of the three-dimensional ferroelectric memory, and (b) in FIG. 12 is (a) in FIG. The top view shown in) is a vertical downward cross-sectional view along the direction of the line HH'. 12, the three-dimensional ferroelectric memory includes: a substrate 10, where the substrate 10 may generally refer to a silicon wafer (wafer), a die or a silicon integrated circuit with logic circuit functions, or A semiconductor with logic circuit functions, etc.; a storage layer 20 located on the substrate 10, the storage layer 20 includes a stacked and alternately arranged isolation layer 201 and a poly-Si (poly-Si) layer 202. The isolation layer 201 may be an electrically insulating material for Two adjacent polysilicon layers 202 are isolated. (A) in FIG. 13 is a front view of the three-dimensional ferroelectric memory, and (b) in FIG. 13 is a side view of the three-dimensional ferroelectric memory.

Wherein, the storage layer 20 is provided with a ferroelectric layer 203 (also called a ferroelectric thin film) and a plurality of columns of first voltage lines 204, the ferroelectric layer 203 surrounds a plurality of columns of first voltage lines 204, and a plurality of columns of first voltage lines 204 Extend along the depth direction of the storage layer 20. For example, one end of the multiple columns of first voltage lines 204 is located on the surface of the storage layer 20 away from the substrate 1, and the other end of the multiple columns of first voltage lines 204 is along the depth direction of the storage layer 20 Extend, for example, extend to the surface of the storage layer 20 close to the substrate 10; the storage layer 20 is provided with an isolation groove 205 located between any two adjacent columns of the first voltage lines 204 among the plurality of columns of first voltage lines 204 to isolate The groove 205 penetrates the storage layer 20.

In addition, a plurality of second voltage lines 206 are provided in the polysilicon layer 202, and the first voltage lines 204, the ferroelectric layer 203 and the second voltage lines 206 form an MFM structure in the polysilicon layer 202. Optionally, the first voltage line 204 is perpendicular to the second voltage line 206.

In an embodiment, the isolation groove 205 is filled with an electrical insulating material, and the electrical insulating material is used to achieve electrical insulation between any two adjacent columns of the first voltage lines 204 in the plurality of columns of the first voltage lines 204. Optionally, the electrically insulating material may be silicon oxide (SiO _x ).

In another embodiment, any two adjacent columns of first voltage lines 204 in the plurality of columns of first voltage lines 204 are arranged at intervals, and each column of first voltage lines 204 may include multiple first voltage lines 204. Optionally, the cross-section of the first voltage line 204 may be any of closed figures such as a circle, an ellipse, or a polygon. For example, the polygon may be a triangle, a quadrilateral, a pentagon, a hexagon, etc. The application embodiment does not impose specific restrictions on this.

Further, as shown in FIG. 14, the part of the first voltage line 204 located in the polysilicon layer 202 has a larger wheel distance than the part of the first voltage line 204 located in the isolation layer 201. For example, if the cross section of the first voltage line 204 is circular, the radius of the portion of the first voltage line 204 located on the polysilicon layer 202 is larger than the radius of the portion of the first voltage line 204 located on the isolation layer 201. Fig. 14(a) is a plan view of the three-dimensional ferroelectric memory, and Fig. 14(b) is a cross-sectional view of the plan view shown in Fig. 14(a) perpendicularly downward along the line HH'.

In an embodiment, the first voltage line 204 may include at least one of the following conductive materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), Tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO _x ), iridium (Ir), iridium oxide (IrO _x ), TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper ( Cu), polysilicon (Si). Exemplarily, the first voltage line 204 may be made of conductive materials with good conductivity, such as W, Al, and Cu, so as to reduce the IR drop on the first voltage line 204 and reduce the first voltage line. The partial pressure of 204 improves the integration and storage density of the three-dimensional ferroelectric memory.

Wherein, when the first voltage line 204 includes at least two conductive materials among the above conductive materials, the at least two conductive materials may be separated, and each conductive material forms a part of the first voltage line 204, for example, the first voltage line 204 A voltage line 204 may include multiple layers along the axis direction away from the axis, and each layer corresponds to a conductive material, so that different conductive materials can be distinguished in the cross section of the first voltage line 204; or, at least this The two conductive materials may be mixed together to form the first voltage line 204 so that the at least two conductive materials cannot be distinguished in the cross section of the first voltage line 204.

In another embodiment, the ferroelectric layer 203 may include at least one of the following materials: hafnium dioxide (HfO ₂ ), doped HfO ₂ , lead zirconium titanate (PbZrTiO ₃ ), doped PbZrTiO ₃ , strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ ), doped SrBi ₂ Ta ₂ O ₉ , lithium niobate (LiNbO ₃ ), doped LiNbO ₃ , lithium tantalate ( LiTaO ₃ ), doped LiTaO ₃ , bismuth ferrite (BiFeO ₃ ), doped BiFeO ₃ , barium titanate (BaTiO ₃ ), doped BaTiO ₃ . Wherein, the dopant mentioned above is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La).

Further, as shown in FIG. 15, the three-dimensional ferroelectric memory further includes an electrical connection layer 30, and the electrical connection layer 30 is located on the storage layer 20 and away from the substrate 1. Among them, each column of the first voltage lines 204 in the plurality of columns of first voltage lines 204 includes a plurality of first voltage lines 204, and the plurality of first voltage lines 204 are electrically connected in the electrical connection layer 30.

In practical applications, the first voltage line 204 may be a bit line (BL), and the second voltage line 206 may be a word line (WL), so the multiple columns of first voltage lines 204 are multiple columns of BL, Each column BL may include multiple BLs, and the multiple second voltage lines 206 are multiple WLs. Optionally, the first voltage line 204 and the second voltage line 206 are perpendicular, that is, BL and WL are perpendicular. It should be noted that the equivalent circuit diagram of the three-dimensional ferroelectric memory and the read and write operations of each memory cell are consistent with the related content described in FIGS. 8 and 9 above. For details, please refer to the above description. The embodiments of the present application are here No longer.

In the embodiment of the present application, the three-dimensional ferroelectric memory includes a storage layer 2 of stacked and alternately arranged isolation layers 201 and polysilicon layers 202. The storage layer 2 is provided with a ferroelectric layer 203 and a plurality of columns passing through the storage layer 2. A voltage line 204 and an isolation groove 205. The ferroelectric layer 203 surrounds a plurality of columns of first voltage lines 204. The isolation groove 205 is used to isolate two adjacent columns of first voltage lines 204. A plurality of first voltage lines 204 are provided in the polysilicon layer 202. Two voltage lines 206, so that a plurality of second voltage lines 206, a ferroelectric layer 203, and a plurality of columns of first voltage lines 204 form a memory cell of MFM structure in the polysilicon layer 202, because the memory cell of the MFM structure has better durability , So that the three-dimensional ferroelectric memory has better durability. In addition, since the polysilicon layer 202 is easier to etch with respect to metal, the etching difficulty of disposing multiple columns of first voltage lines 204 and isolation grooves 205 on the polysilicon layer 202 is reduced.

FIG. 16 is a schematic flowchart of a method for manufacturing a three-dimensional ferroelectric memory according to an embodiment of the application. The three-dimensional ferroelectric memory may be the three-dimensional ferroelectric memory described in any of the above-mentioned FIGS. 12 to 15. As shown in Figure 16, the method may include the following steps. FIG. 17 is a cross-sectional view of the three-dimensional ferroelectric memory in the process of manufacturing the three-dimensional ferroelectric memory.

S41: A storage layer 20 is formed on the substrate 10, and the storage layer 20 includes an isolation layer 201 and a polysilicon layer 202 that are stacked and alternately arranged. As shown in Figure 17 (a).

Among them, the substrate 10 may generally refer to a silicon wafer, a die or a silicon integrated circuit with a logic circuit function, or a semiconductor with a logic circuit function, or the like. The isolation layer 201 may be an electrically insulating material for isolating two adjacent polysilicon layers 202. For example, the isolation layer 201 may be SiO _x . The material of the polysilicon layer 202 may be silicon or silicon germanium.

Specifically, an isolation layer 201 is deposited on the substrate 10, and then a polysilicon layer 202 is deposited on the isolation layer 201, and then the isolation layer 201 and the polysilicon layer 202 are sequentially deposited in the above manner until a multilayer stack is obtained. The isolation layer 201 and the sacrificial polysilicon layer 202 are provided to obtain the storage layer 20. The number of layers of the isolation layer 201 can be one more layer than the number of layers of the polysilicon layer 202. The specific number of layers of the isolation layer 201 and the polysilicon layer 202 can be set according to actual conditions, which is not specifically limited in the embodiment of the present application. For example, (a) in FIG. 17 takes an example in which the number of isolation layers 201 included in the storage layer 20 is 4 and the number of polysilicon layers 202 is 3 as an example.

S42: A ferroelectric layer 203 and a plurality of columns of first voltage lines 204 are arranged in the storage layer 20, the ferroelectric layer 203 surrounds the columns of first voltage lines 204, and one end of the columns of first voltage lines 204 is located in the storage layer 20 away from the substrate On the surface of 10, the other ends of the columns of first voltage lines 204 extend along the depth direction of the storage layer 20 (for example, the other ends of the columns of first voltage lines 204 are located on the surface of the storage layer 20 close to the substrate 10). As shown in Figure 17 (b) to (d).

Wherein, any two adjacent columns of first voltage lines 204 among the plurality of columns of first voltage lines 204 may be arranged at intervals, and each column of first voltage lines 204 may include multiple first voltage lines 204. Optionally, the cross-section of the first voltage line 204 may be any of closed figures such as a circle, an ellipse, or a polygon. For example, the polygon may be a triangle, a quadrilateral, a pentagon, a hexagon, etc. The application embodiment does not impose specific restrictions on this.

Specifically, multiple columns of through holes are provided in the storage layer 20. For example, a deep etching process is used to provide multiple columns of through holes in the storage layer 20. One end of the multiple columns of through holes is located on the surface of the storage layer 20 away from the substrate 10. The other end of the multiple columns of through holes is located on the surface of the storage layer 20 close to the substrate 10, as shown in (b) in FIG. 17; the ferroelectric layer 203 is formed in the multiple columns of through holes, for example, in the multiple columns of through holes A ferroelectric layer 203 is grown on the sidewalls of each via hole, as shown in (c) in FIG. For the first voltage line 204, for example, a conductive material is grown on the surface of the ferroelectric layer 203 by a deposition method until the conductive material completely fills the multiple columns of through holes, and then multiple columns of first voltage lines 204 are obtained, as shown in FIG. (d) Shown. Since the polysilicon layer 202 is easily corroded, compared with the metal etching in the prior art, the difficulty of etching the multi-row through holes is reduced.

Optionally, the first voltage line 204 may include at least one of the following conductive materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO _x ), iridium (Ir), iridium oxide (IrO _x ), TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper (Cu), Polysilicon (Si). Wherein, when the first voltage line 204 includes at least two conductive materials among the above conductive materials, the at least two conductive materials may be separated, and each conductive material forms a part of the first voltage line 204, for example, the first voltage line 204 A voltage line 204 includes two conductive materials. When the conductive materials are respectively filled in the multiple through holes, the first conductive material can be grown on the sidewalls of the multiple through holes, and then the first conductive material can be grown on the sidewalls of the multiple through holes. The second conductive material is grown on the surface; or, the at least two conductive materials can be mixed together to form the first voltage line 204. For example, if the first voltage line 204 includes two conductive materials, then the plurality of through holes When the conductive materials are filled separately, the two conductive materials can be mixed, and the mixed conductive material can be grown on the sidewalls of the multiple through holes.

In one embodiment, the part of the first voltage line 204 that is located in the polysilicon layer 202 has an axle distance greater than that of the part of the first voltage line that is located in the isolation layer 201. Specifically, when multiple columns of through holes are provided in the storage layer 20 as described above, after a deep etching process is used to form multiple columns of through holes in the storage layer 20, a lateral wet etching technique is used to place the multiple columns of through holes in the isolation layer. The position of 201 is etched laterally, so that the part of the multi-row through holes located in the polysilicon layer 202 has a larger wheel distance than the part of the multiple rows of through holes located in the isolation layer 201. Afterwards, the ferroelectric layer and conductive material can be grown in the multiple columns of through holes after the lateral etching to obtain the ferroelectric layer 203 and the multiple columns of first voltage lines 204, and the first voltage line 204 is located in the polysilicon layer 202. The wheel distance of is greater than the wheel distance of the part of the first voltage line located in the isolation layer 201.

S43: forming an isolation groove 205 penetrating the storage layer 20 between any two adjacent columns of the first voltage lines 204 in the plurality of columns of first voltage lines 204 to obtain a plurality of second voltage lines 206 in the polysilicon layer 202. As shown in Figure 17 (e).

Specifically, a deep etching process is used to provide isolation grooves 205 penetrating through the storage layer 20 between any two adjacent columns of the first voltage lines 204 among the multiple columns of first voltage lines 204, so as to connect any two adjacent columns of first voltage lines 204. The voltage lines 204 are physically separated to obtain a plurality of second voltage lines 206 in the polysilicon layer 202; wherein, one end of the isolation groove 205 may be located on the surface of the storage layer 20 away from the substrate 10, and the isolation groove 205 The other end may be located on the surface of the storage layer 20 close to the substrate 10. Since the polysilicon layer 202 is easily corroded, compared with the metal etching in the prior art, the etching difficulty of the isolation groove is reduced.

Further, the method may further include: filling the isolation groove 205 with an electrically insulating material, and the electrically insulating material may be used to realize the connection between any two adjacent columns of first voltage lines 204 among the plurality of columns of first voltage lines 204 Electrical insulation. Exemplarily, the electrically insulating material may be silicon oxide (SiO _x ).

In another embodiment, each of the plurality of columns of first voltage lines 204 includes a plurality of first voltage lines 204, and the method further includes: forming an electrical connection layer 30 on the storage layer 20 to electrically connect The layer 30 is located on the side of the storage layer 20 away from the substrate 10, and a plurality of first voltage lines 204 are electrically connected in the electrical connection layer 30, as shown in (f) of FIG. 14.

It should be noted that the relevant description of the three-dimensional ferroelectric memory provided in any of the above figures 12 to 15 can be cited in the manufacturing method of the three-dimensional ferroelectric memory, and the embodiments of the present application will not be omitted here. Go into details.

In the manufacturing method of the three-dimensional ferroelectric memory provided by the embodiment of the present application, the storage layer 20 formed on the substrate 10 includes an isolation layer 201 and a polysilicon layer 202 that are stacked and alternately arranged. Because the polysilicon layer 202 is easily corroded, the storage layer When multiple columns of first voltage lines 204 and isolation grooves 204 penetrating through the storage layer 20 are provided in 20, the difficulty of etching through holes, isolation grooves, and the like using an etching process can be greatly reduced. At the same time, the ferroelectric layer 203 provided in the storage layer 20 surrounds multiple columns of first voltage lines 204, so that the multiple columns of first voltage lines 204, the ferroelectric layer 203, and the multiple second voltage lines 206 in the polysilicon layer 202 are in the polysilicon The memory cell of the MFM structure is formed in the layer 202. Since the memory cell of the MFM structure has better durability, the three-dimensional ferroelectric memory has better durability.

Based on this, an embodiment of the present application further provides an electronic device that includes a circuit board and a three-dimensional ferroelectric memory connected to the circuit board. The three-dimensional ferroelectric memory can be any of the three-dimensional ferroelectrics provided above. Memory. Wherein, the circuit board may be a printed circuit board (PCB), of course, the circuit board may also be a flexible circuit board (FPC), etc., and the circuit board is not limited in this embodiment. Optionally, the electronic device is different types of user equipment or terminal devices such as computers, mobile phones, tablet computers, wearable devices, and in-vehicle devices; the electronic devices may also be network devices such as base stations.

Optionally, the electronic device further includes a packaging substrate, the packaging substrate is fixed on the printed circuit board PCB by solder balls, and the three-dimensional ferroelectric memory is fixed on the packaging substrate by solder balls.

It should be noted that, for the relevant description of the three-dimensional ferroelectric memory in the electronic device, please refer to the description of the three-dimensional ferroelectric memory in the above-mentioned FIG. 2 to FIG.

In another aspect of this application, there is also provided a non-transitory computer-readable storage medium for use with a computer, the computer has software for creating integrated circuits, and the computer-readable storage medium stores one or more A computer-readable data structure. One or more computer-readable data structures have photomask data for manufacturing the integrated circuit provided in any of the illustrations provided above.

Finally, it should be noted that the above are only specific implementations of this application, but the scope of protection of this application is not limited to this. Any change or replacement within the technical scope disclosed in this application shall be covered by this application. Within the scope of protection applied for. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A method for manufacturing a three-dimensional ferroelectric memory, characterized in that the method includes:

Forming a stacked layer on the substrate, the stacked layer including an isolation layer and a sacrificial layer that are stacked and alternately arranged;

Multiple columns of first voltage lines are arranged in the stacked layer, and the multiple columns of first voltage lines extend along the depth direction of the stacked layer;

Forming an isolation groove penetrating the stacked layer between any two adjacent first voltage lines in the plurality of columns of first voltage lines;

Etching away the sacrificial layer in the stacked layer to obtain a first frame;

A metal layer stacked and alternately arranged with the isolation layer is formed in the first frame to obtain a storage layer; wherein, the metal layer includes a ferroelectric layer and a plurality of second voltage lines, and the ferroelectric layer surrounds The plurality of second voltage lines and the plurality of columns of first voltage lines are located in a portion of the metal layer, so that a metal-ferroelectric layer-metal MFM structure is formed in the metal layer.
The method according to claim 1, wherein the arranging multiple columns of first voltage lines in the stacked layer comprises:

Multiple rows of through holes are provided in the stacked layer, the multiple rows of through holes extend along the depth direction of the stacked layer;

The first voltage lines are respectively filled in the multiple columns of through holes to obtain multiple columns of first voltage lines.
The method according to claim 1 or 2, wherein the forming a metal layer stacked and alternately arranged with the isolation layer in the first frame to obtain a storage layer comprises:

A ferroelectric material is grown on the surface of the first frame, the thickness of the ferroelectric material is less than a first distance, and the first distance is the distance between two adjacent isolation layers in the first frame ；

A conductive material is grown on the surface of the ferroelectric material, and the sum of the thickness of the conductive material and the thickness of the ferroelectric material is greater than or equal to the first distance to obtain a storage layer matrix. The ferroelectric material between two adjacent isolation layers forms a ferroelectric layer, and the conductive material between two adjacent isolation layers forms a plurality of second voltage lines, and the ferroelectric layer Forming a metal layer with the plurality of second voltage lines;

The ferroelectric material and the conductive material on the surface of the storage layer base are removed to obtain a storage layer, and the storage layer includes the isolation layer and the metal layer that are stacked and alternately arranged.
The method according to any one of claims 1 to 3, wherein any two adjacent columns of first voltage lines in the plurality of columns of first voltage lines are arranged at intervals.
The method according to any one of claims 1-4, wherein the method further comprises:

An electrical insulating material is filled in the isolation groove.
The method according to claim 5, wherein the electrically insulating material comprises: a silicon oxide (SiO x).
The method according to any one of claims 1 to 6, wherein the part of the first voltage line that is located in the metal layer has an axle distance greater than that of the first voltage line that is located in the isolation layer. Part of the wheel margin.
The method according to any one of claims 1-7, wherein the first voltage line or the second voltage line comprises at least one of the following materials: titanium nitride (TiN), tungsten (W) , Nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), TaN (nitrogen) Tantalum), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), a compound of silicon and metal.
The method according to any one of claims 1-8, wherein the ferroelectric layer comprises at least one of the following materials: hafnium dioxide (HfO 2 ), doped HfO 2 , lead titanate Zirconium (PbZrTiO 3 ), doped PbZrTiO 3 , strontium bismuth tantalate (SrBi 2 Ta 2 O 9 ), doped SrBi 2 Ta 2 O 9 , lithium niobate (LiNbO 3 ), doped LiNbO 3 , lithium tantalate (LiTaO 3 ), doped LiTaO 3 , bismuth ferrite (BiFeO 3 ), doped BiFeO 3 , barium titanate (BaTiO 3 ), doped BaTiO 3 .
The method according to claim 9, wherein the dopant is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La).
The method according to any one of claims 1-10, wherein the first voltage line is a bit line, and the second voltage line is a word line.
The method according to any one of claims 1-11, wherein each column of the first voltage lines in the plurality of columns of first voltage lines includes a plurality of first voltage lines, and the method further comprises:

An electrical connection layer is formed on the storage layer, and the plurality of first voltage lines are electrically connected in the electrical connection layer.
A three-dimensional ferroelectric memory is characterized in that the three-dimensional ferroelectric memory includes:

Substrate

A storage layer located on the substrate, the storage layer including an isolation layer and a metal layer that are stacked and alternately arranged;

Wherein, the storage layer is provided with multiple columns of first voltage lines and isolation grooves located between any two adjacent columns of first voltage lines in the multiple columns of first voltage lines, and the multiple columns of first voltage lines The voltage line extends along the depth direction of the storage layer, and the isolation groove penetrates the storage layer;

The metal layer is provided with a ferroelectric layer and a plurality of second voltage lines, and the ferroelectric layer surrounds a portion of the plurality of second voltage lines and the plurality of columns of the first voltage lines located in the metal layer, So that a metal-ferroelectric layer-metal MFM structure is formed in the metal layer.
The three-dimensional ferroelectric memory according to claim 13, wherein any two adjacent columns of first voltage lines in the plurality of columns of first voltage lines are arranged at intervals.
The three-dimensional ferroelectric memory according to claim 13 or 14, wherein the isolation groove is filled with an electrically insulating material.
The three-dimensional ferroelectric memory according to claim 15, wherein the electrically insulating material comprises: a silicon oxide (SiO x).
The three-dimensional ferroelectric memory according to any one of claims 13-16, wherein the part of the first voltage line that is located in the metal layer has an axle distance greater than that of the first voltage line located in the The wheel distance of the part of the isolation layer.
The three-dimensional ferroelectric memory according to any one of claims 13-17, wherein the first voltage line or the second voltage line comprises at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), TaN (tantalum nitride), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), a compound of silicon and metal.
The three-dimensional ferroelectric memory according to any one of claims 13-18, wherein the ferroelectric layer comprises at least one of the following materials: hafnium dioxide (HfO 2 ), doped HfO 2 , Lead zirconium titanate (PbZrTiO 3 ), doped PbZrTiO 3 , strontium bismuth tantalate (SrBi 2 Ta 2 O 9 ), doped SrBi 2 Ta 2 O 9 , lithium niobate (LiNbO 3 ), Doped LiNbO 3 , lithium tantalate (LiTaO 3 ), doped LiTaO 3 , bismuth ferrite (BiFeO 3 ), doped BiFeO 3 , barium titanate (BaTiO 3 ), doped Impurities of BaTiO 3 .
The three-dimensional ferroelectric memory according to claim 19, wherein the dopant is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd) ), strontium (Sr), lanthanum (La).
The three-dimensional ferroelectric memory according to any one of claims 13-20, wherein the first voltage line is a bit line, and the second voltage line is a word line.
The three-dimensional ferroelectric memory according to any one of claims 13-21, wherein each column of the first voltage lines in the plurality of columns of first voltage lines includes a plurality of first voltage lines, and the three-dimensional ferroelectric memory It further includes: an electrical connection layer on the storage layer, and the plurality of first voltage lines are electrically connected in the electrical connection layer.
An electronic device comprising a circuit board and a three-dimensional ferroelectric memory connected to the circuit board, the three-dimensional ferroelectric memory being the three-dimensional ferroelectric memory according to any one of claims 13-22.