CN108550575A - The preparation method and channel bottom lithographic method of three-dimensional storage - Google Patents
The preparation method and channel bottom lithographic method of three-dimensional storage Download PDFInfo
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- CN108550575A CN108550575A CN201810552830.3A CN201810552830A CN108550575A CN 108550575 A CN108550575 A CN 108550575A CN 201810552830 A CN201810552830 A CN 201810552830A CN 108550575 A CN108550575 A CN 108550575A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
Abstract
A kind of preparation method of three-dimensional storage, including：Lamination；Form storage string；Form groove；Remove the first insulating layer in lamination；It is conformally formed barrier layer in the vacancy left after groove and the first insulating layer are removed；Conductor material is inserted in vacancy, conductive layer is formed；It is conformally formed wall in the trench；The first etching process is carried out, to remove the barrier layer and wall of channel bottom；Carry out the second etching process so that identical to the etch rate of barrier layer with wall.The preparation method of three-dimensional storage provided by the invention, due to identical with the etch rate of the silicon oxide layer with the second etching process and in the second etching process barrier layer, so can preferably inhibit the generation of step at groove opening, and then common source contact of good performance can be obtained.
Description
Technical field
The invention mainly relates to memory technology field more particularly to the preparation methods and trench bottom of a kind of three-dimensional storage
Portion's lithographic method.
Background technology
With the continuing emphasis to highly integrated electronic device, to higher speed and lower Power operation and having
There are lasting demands for the semiconductor storage unit of increased device density.To reach this purpose, have been developed with more
The device of small size and multilayer device with the transistor unit arranged with horizontal and vertical array.3D NAND are industry institutes
A kind of emerging flash type of research and development, 2D or plane nand flash memory are solved by vertical stacking multi-layer data storage unit
The limitation brought has remarkable precision, supports to receive higher memory capacity in smaller space content, can create storage
Capacity is up to the storage device of several times than similar NAND technology, and then effectively reduces cost and energy consumption, can meet numerous disappear comprehensively
Take class mobile device and requires the demand of most harsh enterprise's deployment.
Nand memory in the fabrication process, in order to make common source contact, needs to perform etching the channel bottom of formation,
Then tungsten wall filling is carried out into groove again, this etching technics is one of critical process of three-dimensional storage.However, due to carving
Rate difference is lost, after above-mentioned etching technics, it is (following to be easy to be formed the bulge-structure similar to step in the opening of groove
Abbreviation step), the effect that tungsten wall in road is filled after influencing.
Invention content
The technical problem to be solved in the present invention includes providing a kind of preparation method and channel bottom etching of three-dimensional storage
Method can preferably inhibit the generation of step at groove opening under the premise of being performed etching to channel bottom, and then can protect
It demonstrate,proves subsequent technique process and obtains good technological effect.
To solve at least part technical problem of the present invention, at least one embodiment of the present invention provides a kind of three-dimensional
The preparation method of memory, includes the following steps：It is formed on substrate and shape is alternately stacked by the first insulating layer and second insulating layer
At insulator lamination；
Form the storage string for extending vertically through the insulator lamination；
Form the groove for extending vertically through the insulator lamination up to the substrate；
Remove first insulating layer；
It is conformally formed barrier layer in the vacancy left after the groove and first insulating layer are removed；
Conductor material is inserted in the vacancy, conductive layer is formed；
It is conformally formed wall in the groove；
The first etching process is carried out, to remove the barrier layer and the wall of channel bottom；
The second etching process is carried out, in second etching process so as to the etching speed of the barrier layer and the wall
Rate is identical.
In at least one embodiment of the present invention, in first etching process, using first gas to barrier layer and/
Or wall is chemically etched；
Second etching process is carried out using the second gas different from the first gas, it, should in second etching process
Second gas does not occur chemically to etch to barrier layer and wall.
In at least one embodiment of the present invention, which is fluoro-gas, which is inert gas.
In at least one embodiment of the present invention, in first etching process and second etching process to this first
The lower limit for the bias that gas and the second gas apply is 600 volts or 800 volts；
The bias that the first gas and the second gas are applied in first etching process and second etching process
The upper limit be 1500 volts or 2000 volts；
The bias of second etching process is less than or equal to the bias of first etching process.
In at least one embodiment of the present invention, the upper limit of the duration of first etching process is 400 seconds or 480 seconds,
The lower limit of the duration of first etching process is 200 seconds or 240 seconds；
The upper limit of the duration of second etching process is 160 seconds or 200 seconds, and the lower limit of the duration of second etching process is
40 seconds or 80 seconds.
In at least one embodiment of the present invention, the material of barrier layer is aluminium oxide, hafnium oxide, lanthana, yttrium oxide
With one or more combinations in tantalum oxide.
In at least one embodiment of the present invention, the range of the thickness of the barrier layer of formation is 2-5 nanometers.
In at least one embodiment of the present invention, the material of wall is in silicon nitride, silica and silicon oxynitride
One or more combinations.
In at least one embodiment of the present invention, the range of the thickness of the wall of formation is 20 nanometers to 40 nanometers.
In at least one embodiment of the present invention, including multiple cycle etching processes, each cycle etching process packet
Include at least one first etching process and at least one second etching process.
In at least one embodiment of the present invention, the lower limit of the quantity of the cycle etching process is 2 times or 4 times, this is followed
The upper limit of the quantity of ring etching process is 10 times or 12 times；
In each cycle etching process, the upper limit of the duration of first etching process is 100 seconds or 120 seconds, this
The lower limit of the duration of one etching process is 50 seconds or 60 seconds；
In each cycle etching process, the upper limit of the duration of second etching process is 40 seconds or 50 seconds, this second
The lower limit of the duration of etching process is 10 seconds or 20 seconds.
In at least one embodiment of the present invention, the technique of multiple first etching processes of multiple cycle etching process
Parameter is identical, and the technological parameter of multiple second etching processes of multiple cycle etching process is identical.
In at least one embodiment of the present invention, the last one cycle etching process in multiple cycle etching process
In the second etching process equivalent etching depth be more than at least one cycle etching process before cycle etching process in
The second etching process equivalent etching depth.
At least part technical problem for not solving the present invention, the present invention also provides a kind of channel bottom lithographic method,
In at least one embodiment of the present invention, which includes the following steps：
First etching process is carried out to the groove being formed on semiconductor structure；The side wall of the groove be formed with first layer and
The second layer, the first layer are different with the material of the second layer；First etching process be used for remove channel bottom first layer and
The second layer；
Second etching process, in second etching process, the etch rate of first layer and the second layer are carried out to the groove
It is identical.
In at least one embodiment of the present invention, which further includes substrate, formed on substrate by leading
Body layer and insulating layer are alternately stacked the lamination to be formed, and extend vertically through the storage string of the lamination；
For the groove vertical through the lamination until the substrate, which is conformally formed the inner wall in the groove, this
One layer is formed between the second layer and the substrate and the insulating layer, the first layer be also formed in the conductor layer and the insulating layer and
Between the storage string.
In at least one embodiment of the present invention, the first etching process is carried out to the semiconductor structure with first gas,
In first etching process, a generation in the first layer and the second layer is chemically etched；
The second etching process is carried out to the semiconductor structure with the second gas different from the first gas, at second quarter
During erosion, the first layer and the second layer are not occurred chemically to etch.
In at least one embodiment of the present invention, which is the gas suitable for etching opening in the channel bottom
Body, the second gas are inert gas.
In at least one embodiment of the present invention, including multiple cycle etching processes, each cycle etching process packet
Include at least one first etching process and at least one second etching process.
In at least one embodiment of the present invention, the lower limit of the quantity of the cycle etching process is 2 times or 4 times, this is followed
The upper limit of the quantity of ring etching process is 10 times or 12 times；
In each cycle etching process, the upper limit of the duration of first etching process is 100 seconds or 120 seconds, this
The lower limit of the duration of one etching process is 50 seconds or 60 seconds；
In each cycle etching process, the upper limit of the duration of second etching process is 40 seconds or 50 seconds, this second
The lower limit of the duration of etching process is 10 seconds or 20 seconds.
The preparation method and channel bottom lithographic method of three-dimensional storage provided by the invention, in the base of the first etching process
Increase by the second etching process on plinth, in second etching process, makes the etch rate phase of the barrier layer and wall in groove
Together, it is etched with eliminating the step generated in the first etching process, and then ensures that subsequent technique process obtains good technique effect
Fruit.Therefore, the present invention can preferably inhibit the generation of step at groove opening, for three-dimensional storage, after capable of making
The effect of road tungsten wall fill process is preferable, and finally obtains common source contact of good performance.
Description of the drawings
Fig. 1 is the flow chart of the preparation method of three-dimensional storage in one embodiment of the invention；
Fig. 2 is the preparation process schematic diagram for forming barrier layer and wall in one embodiment of the invention in the trench；
Fig. 3 is the preparation process schematic diagram that the first etching process is carried out in one embodiment of the invention；
Fig. 4 is the preparation process schematic diagram that the second etching process is carried out in one embodiment of the invention.
Specific implementation mode
In order to which the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to the present invention's
Specific implementation mode elaborates.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still the present invention can be with
Implemented different from other manner described here using other, therefore the present invention do not limited by following public specific embodiment
System.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " comprising " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or equipment
The step of may also including other or element.
Referring initially to Fig. 1-4, to a unrestricted example of the preparation method of three-dimensional storage provided by the invention
It illustrates.In current non-limitative example, the preparation method of three-dimensional storage provided by the invention, including following step
Suddenly：
Step 100, as shown in Figure 1, making groove.In the ongoing illustrated embodiment, groove is to be fabricated on a semiconductor
In structure.As shown in Fig. 2, the semiconductor structure is formed by forming lamination 9 on substrate 1.The lamination 9 includes multiple leads
Body layer 7/ and insulating layer 6.Definition first direction is the direction vertical with the surface of substrate 1.In the ongoing illustrated embodiment, the lamination
The specific set-up mode of conductor layer 7/ and insulating layer 6 is in 9, along first direction be alternately stacked multiple conductor layers 7 and it is multiple absolutely
Edge layer 6.In addition, semiconductor structure can also have the other structures such as separation layer 2, in the ongoing illustrated embodiment, separation layer 2 is arranged
In the top of lamination 9 and cover the lamination 9.
In the ongoing illustrated embodiment, substrate 1 is made of monocrystalline silicon.But in other examples, substrate 1 also can be by it
He is made suitable material, for example, in some embodiments, the material of substrate 1 is silicon, germanium, silicon on insulator
(Silicon on insulator, SOI) etc..In this step, the thickness of separation layer 2 can be set according to actual conditions
It is fixed.Generally in order to obtain preferable isolation effect, but it is unlikely to make the depth of groove 3 excessive, it generally can be by separation layer
Thickness be arranged between 50 nanometers to 250 nanometers.
Optionally, in the ongoing illustrated embodiment, three-dimensional storage also has storage string 8.The storage string 8 is passed through along first direction
Wear lamination 9.One end (i.e. lower end in Fig. 2) of the storage string 8 is contacted with substrate 1, in current example, due to being equipped with isolation
Layer, so the other end (i.e. upper end in Fig. 2) of the storage string 8 then extends into separation layer 2.In other words, separation layer 2 also covers institute
State storage string 8.
Optionally, storage string 8 is separated with conductor layer 7 with barrier layer 4.In the present embodiment, the groove 3 that current procedures make
Along first direction perpendicularly through lamination 9 (optionally also extending through separation layer 2), until the substrate 1.Wall 5 is conformally formed
In the inner wall of groove 3.Between wall 5 and substrate 1, insulating layer 6 and separation layer 2 and conductor layer 7 and insulating layer 6 and storage
It is each formed with barrier layer 4 between string 8.
In some embodiments, structure shown in Fig. 2 is formed in the following way：
The insulator lamination for being alternately stacked and being formed by the first insulating layer and second insulating layer is formed on substrate 1 (in figure not
Show), the first insulating layer material is different from second insulating layer.
In some embodiments, the first insulating layer and second insulating layer material include but not limited to silica, silicon nitride or
The combination of silicon oxynitride or a variety of above materials.In some embodiments, existing in insulator lamination has different-thickness first
Insulating layer.In some embodiments, existing in insulator lamination has different-thickness second insulating layer.In some embodiments,
Insulator lamination further includes one or more layers insulating layer except the first insulating layer and second insulating layer, and the insulating layer and first is absolutely
Edge layer and second insulating layer are made from a variety of materials and/or with different thickness.
Formed and run through the storage string 8 that contact with substrate 1 of insulator lamination along first direction, formed cover insulator lamination with
The separation layer 2 of storage string 8.Storage string 8 includes semiconductor channel layer and dielectric layer (not shown).
In some embodiments, semiconductor channel layer is made of non-crystalline silicon, polysilicon or monocrystalline silicon.In some embodiments
In, dielectric layer includes tunnel layer, memory cell layers and barrier layer.In some embodiments, the tunnel layer includes insulating materials,
The including but not limited to combination of silica, silicon nitride or silicon oxynitride or above-mentioned material.In some embodiments, tunnel layer
Thickness be 5-15nm, the electronics or hole in channel semiconductor can be by this layer of tunnel layer tunnellings to memory cell layers.
In some embodiments, memory cell layers can be used for storing operation charge, the storage or shifting of the charge in memory cell layers
Except the on off state for determining channel semiconductor.The material of memory cell layers includes but not limited to silicon nitride, silicon oxynitride or silicon,
Or the combination of the above material.In some embodiments, the thickness of memory cell layers is 3-15nm.In some embodiments, it hinders
Barrier material is the combination of silica, silicon nitride or high dielectric constant insulating material or a variety of above materials.A such as oxygen
The composite layer that SiClx layer or the thickness comprising three layers of silicon oxide/silicon nitride/silicon oxide (ONO) are 4-15nm.In some realities
It applies in example, barrier layer may further include a high k dielectric layer (such as aluminium oxide that thickness is 1-5nm).
Formed along first direction through insulator lamination until substrate 1 groove 3, remove insulator lamination in first absolutely
Edge layer (due to the first insulating layer herein and second insulating layer by named in this way merely to distinguished to this two kinds of insulating layers,
Therefore second insulating layer can also be removed), retaining second insulating layer, (i.e. insulating layer 6 can also be similarly to retain first absolutely
Edge layer), it is conformally formed barrier layer 4 in the vacancy that groove 3 and the first insulating layer leave, by the first insulation of conductor material filling
In the vacancy that layer leaves, conductive layer 7 is formed, wall 5 is conformally formed in groove 3.
In some embodiments, groove 3 is formed by dry/wet etching technics.In some embodiments, by dry
Method/wet etching selective etch removes the first insulating layer.In some embodiments, barrier layer 4, conductive layer 7 and interval are formed
Layer 5 can use film deposition art, including but not limited to chemical vapour deposition technique (CVD), physical vaporous deposition (PVD),
Or atomic layer deposition method (ALD).In some embodiments, barrier layer 4 is made of high-k dielectric material, including but not limited to aoxidizes
Aluminium, hafnium oxide, lanthana, yttrium oxide and/or tantalum oxide can effectively prevent electric leakage and generate.In some embodiments, conductive layer 7
It is made of an electrically conducting material, including but not limited to tungsten, cobalt, copper, aluminium and/or metal silicide, is used to form wordline and selection door.
In some embodiments, wall 5 is made of insulating materials, including but not limited to silica, silicon nitride, silicon oxynitride, Yi Jiqian
State a variety of combinations in material.In some embodiments, in conductor/insulation body lamination 9 conductive layer 7 thickness be 5 nanometers extremely
Nanometer.In some embodiments, in conductor/insulation body lamination 9 insulating layer 6 of some positions thickness be 5 nanometers to nanometer, separately
The thickness of the insulating layer 6 of some positions is 50 nanometers to nanometer.In some embodiments, the thickness of barrier layer 4 is 2- nanometers.
In some embodiments, the thickness of wall 5 is 20 nanometers to 40 nanometers.
Step 200, the first etching process, the barrier layer 4 and wall 5 of 3 bottom of removal groove are carried out.In order to realize to ditch
The preferable etching effect in bottom of slot 3, in first etching process, the etch rate of barrier layer 4 and wall 5 is often not
Together.Such as it is shown in Fig. 3, after the first etching process, the wall 5 of 3 side wall of groove is relative to barrier layer 4 by more
Removal so that barrier layer 4 is relative to the height with bigger, and then rugged of formation in a first direction of wall 5
Rank 11.In addition, after the first etching process, the barrier layer 4 and wall 5 of 3 bottom of groove are removed, and form opening 10,
Substrate 1 is set to expose.In some embodiments, which extends in substrate 1.This bottom opening 10 is the etching ditch
The main purpose of slot method.However, as previously mentioned, in order to make the bottom opening 10, which must use special
The etching technics of door, such etching technics often have different etch rates to barrier layer 4 and wall 5.Different quarters
Erosion rate may result in the generation of step 11.
In some embodiments, the purpose performed etching to 3 bottom of groove is that conductive material is filled into groove to be formed
Common source contact (not shown).In some embodiments, the material for constituting common source contact include but not limited to tungsten, cobalt, copper,
The combination of aluminium, doped silicon, silicide or more material.In some embodiments, the technique for conductive material being filled into groove can
Think ALD, CVD, PVD and other suitable methods.In some embodiments, common source contact is electrically connected one by substrate 1
Or multiple NAND strings.
Step 300, the second etching process is carried out, the step 11 that barrier layer 4 and wall 5 are constituted is cut into circle, is formed as class
Arc structure 12.In second etching process, barrier layer 4 is identical with the etch rate of wall 5.Second etching process
Main function is removal step 11.As shown in figure 4, by the step 300, smoother similar arc structure 12 is formd.It should
Second etching process enables to the region at former step 11 to become smoother reason to be, in this step to barrier
Layer 4 and 5 etch rate having the same of wall, and the step 11 that previous stage generates is due to more prominent in structure, because
It is easier in this step by stronger etching, to be etched away in this step.Certainly, herein " right
" identical " in 5 etch rate having the same of barrier layer 4 and wall " obviously is understood not to that second quarter must be made
Erosion process to identical with the etching speed of wall 5 to barrier layer 4, but should with broadly understood.In other words, any
In embodiment, as long as so that roughly the same to the etching speed of barrier layer 4 and wall 5 in the etch step, rather than
Intentionally the etching speed of barrier layer 4 and wall 5 is set as, with significant difference, just answering by the methods of selective etch
It is spirit according to the present invention so that " etch rate phase of second etching process to barrier layer and wall when being understood to
Together ".
It is worth noting that, above example is one to the preparation method of three-dimensional storage proposed by the invention
The explanation of optional example.The mass part of the preparation method of three-dimensional storage proposed by the invention may have a variety of more
The set-up mode of sample.For example, the first and second etching processes can both carry out in the same cavity of same equipment, so that whole
The process of a etching groove is more compact, can also be carried out in the even different equipment of different cavitys so that etching every time
Effect it is preferable.Below with some unrestricted examples in the variation of the preparation method of three-dimensional storage provided by the invention
At least part illustrate.
In the preparation method of three-dimensional storage proposed by the invention, realizes two different etching processes and realize the
The specific method identical with the etch rate of separation layer 2 of barrier layer 4 can be various in two etching processes.According to a non-limit
The example of property processed, can be by realizing above-mentioned purpose in two etching processes using the method for different etching gas.Specifically
, it could be provided as in the first etching process, semiconductor structure performed etching using first gas, and it is etched second
Cheng Zhong then performs etching semiconductor structure using the second gas different from first gas.
Specifically, the selection to first gas and second gas can be passed through so that first gas is in the first etching process
In, carrying out chemically etching at least one of barrier layer 4 and separation layer 2, (first gas is in the first etching process to barrier
Physical etching can occur for layer 4 and separation layer 2, and physical etching can not also occur).And second gas is etched second
Cheng Zhong does not occur then chemically to etch to barrier layer 4 and separation layer 2.The reason of being arranged in this way is that chemistry can occur for use
Property etching first gas enable to have preferable effect when the first etching process performs etching the bottom of groove 3.And
Since second gas does not occur chemically to etch in the second etching process, so can preferably ensure to hinder using second gas
Interlayer 4 is identical with etch rate of the separation layer 2 in the second etching process.
As above, for second gas, although only needing to meet " second gas only generation in the second etching process
The requirement of physical etching ".If but in general, enable to the molecular weight of second gas larger, is enabled to
Two etching processes are more efficient.Therefore, molecular weight can generally be selected to be more than the 4, gas more than 8 or more than 20 as the second gas
Body.Theoretically, the molecular weight of second gas is the bigger the better, and certain prodigious material of molecular weight often has certain be not suitable as
The unfavorable factor (higher price, toxic etc.) of etching gas but theoretically, these gases are can be used as the second etching gas
, it does not use actually the prodigious material of molecular weight to be not due to these materials and cannot function as the second etching gas.
Although in addition, disclosure satisfy that the gas of " physical etching only occurs in etching process " be it is diversified,
If better effect is will receive if second gas using inert gas.Inert gas is preferably the reason is that, it is chemical
Nature comparison is stablized, it can be ensured that physical etching only occurs in the second etching process.
Similarly, first gas only needs the requirement for meeting " occurring chemically to etch in the first etching process "
(physical etching, which can occur, can not also occur physical etching), but in general, selection has preferably the bottom of groove 3
Etching effect first gas to make bottom opening 9 (main purpose for completing the etching groove method) more have
Profit.So fluoro-gas can be selected as first gas.
Since in the preparation method of the three-dimensional storage of the present invention, bottom opening 10 is mainly by first gas first
It is etched in etching process, and the second etching process is then primarily to eliminate step 11.So can be by the second etching
Bias (Bias RF Voltage, that is, the voltage being applied on etching gas) in the process is set smaller than or is equal to first
The bias of etching process.Both settings respectively have quality, and the bias of the second etching process is set smaller than the first etching process
Bias the influence of formation of second etching process to bottom opening 10 can be made smaller, and by the bias of the second etching process
Be equal to the first etching process bias can then make switching between the first etching process and the second etching process compared with
It is easy.Therefore the specific setting method of the bias of the first etching process and the second etching process can according to actual conditions into
Row selection.
Similar with the setting of bias, the duration of the second etching process can also be set to less than the first etching process
Duration.And the setting of duration and bias can be combined with each other.I.e. so that the duration of the second etching process was less than for the first quarter
The technical solution that the duration of erosion process and the bias of the second etching process are less than or equal to the bias of the first etching process is also
It is feasible.
Hereinbefore the case where bias of the first etching process and the second etching process, is described.Further
, the bias applied in first gas and second gas in first etching process and the second etching process can be set to
Between 600 volts to 2000 volts.For example, in order to forming process and step 11 to bottom opening 10 elimination process into
Row is more accurately controlled, and can will be applied in first gas and second gas in the first etching process and the second etching process
Bias is set as lower 800 volts.In another example in order to accelerate the etching efficiency of the first etching process and the second etching process,
The bias applied in first gas and second gas in first etching process and the second etching process can be set as larger
1500 volts.Certainly, the bias of the first etching process and the second etching process can be the same or different.
Hereinbefore the case where duration of the first etching process and the second etching process, is described.Further
The duration on ground, first etching process can be selected in the range between 200 seconds to 480 seconds.Shorter first is etched
The duration of journey, such as 240 seconds, enable to whole process efficiency higher.The duration of longer first etching process, such as
400 seconds, then the profile of bottom opening 10 is enabled to be damaged preferably and to the top of chip smaller.Similar, second is etched
The duration of journey can be selected in the range within 40 seconds to 200 seconds.The duration of the second shorter etching process, such as by
Two etching processes are set as 40 seconds, and the second etching process is enabled to use and same or similar inclined of the first etching process
Pressure, to keep the setting of technique easier.The duration of longer second etching process, such as set the second etching process to
160 seconds, then enable to influence of the process for eliminating step 11 to the top of bottom opening 10 and chip all relatively low.
Although it is worth noting that, hereinbefore by the preparation method of three-dimensional storage on semiconductor structure of the present invention
Be described as including the steps that step 100-300, but it is such description simply to illustrate that the present invention semiconductor structure etching
Method can be implemented with the sequence of step 100-300.In fact, the lithographic method of the semiconductor structure of the present invention can also be with other
Sequence implement.It, can also be by step in the lithographic method of semiconductor structure of the invention according to a unrestricted example
200 and step 300 as a cycle etching process, and in same primary etching, carry out multiple cycle etching processes.
The second etching process in previous cycle etching process (i.e. after step 300), carries out this cycle to chip again
The first etching (i.e. step 200) process in etching process.
Multiple cycle etching processes can be carried out in the lithographic method of the semiconductor structure of the present invention.Preferably, it follows
The quantity of ring etching process can be selected between 2 times and 12 times.The quantity of smaller cycle etching process, such as 4 times,
The number that switching can be allowed to carry out is less so that overall cost it is relatively low and whole etching efficiency it is higher.Larger follows
The quantity of ring etching process, such as 10 times, it can make when carrying out the second etching process every time, the ruler of the step to be eliminated
It is very little smaller, thus lower second etching process intensity may be used, to reduce by the second etching process at the top of chip and bottom
The influence of the form of portion's opening 10.But the final product obtained when the quantity for recycling etching process is set greater than 12 times,
The final product obtained when compared to 12 cycle etching processes, without the improvement for being enough to be observed.
The duration of first etching process and the second etching process can be adjusted in a certain range.It is more in progress
Under the premise of a cycle etching process, the duration of the first etching process in single loop etching process can be at 50 seconds to 120
It is adjusted in the range of second.The duration of the first shorter etching process, such as 60 seconds, enable to whole process efficiency compared with
It is high.The duration of longer first etching process, such as 100 seconds, then enable to the profile of bottom opening 10 preferably and to chip
Top damage it is smaller.Correspondingly, the range of the duration of the second etching process in single loop etching process is 10 seconds to 50
Second.The duration of the second shorter etching process, such as 20 seconds, enable to the second etching process use and the first etching process phase
Same or similar bias.And the duration of longer second etching process, such as 40 seconds, then enable to the mistake for eliminating step 11
Influence of the journey to the top of bottom opening 10 and chip is all relatively low.
A unrestricted example according to the present invention, it is multiple to follow in the case where carrying out multiple cycle etching processes
The technological parameter setting of multiple first etching processes in ring etching process is all identical and multiple cycle etching processes multiple the
The technological parameter of two etching processes is also identical.The advantages of this arrangement are as follows technological process be easier to setting and every time it is etched
The etching effect of journey is more controllable.
According to some embodiments of the present invention, the technological parameter of multiple second etching processes of multiple cycle etching processes can
To be different.Specifically, in one embodiment of the invention, second in the last one cycle etching process is etched
The equivalent etching depth of journey is more than the second etching process in the cycle etching process before at least one cycle etching process
Equivalent etching depth.
The reason of being arranged in this way is, is necessary to ensure that in the second etching process of last time and thoroughly removes step 11
It goes, thus the equivalent etching depth of the second etching process in the last one cycle etching process is larger.And at each
It is all unnecessary using the second etching process of larger equivalent etching depth having the same to recycle in etching process, therefore can
So that at least one of multiple cycle etching processes before have the second etching process of smaller equivalent etching depth.
Optionally, in current non-limitative example, multiple cycles etching before the last one cycle etching process
In the process, it is set smaller than by the way that at least one of the cycle etching process to be recycled to the duration of the second etching of etching process
The method of the duration of the second etching process in the last one cycle etching process so that in multiple cycle etching processes before
At least one the second etching process with smaller equivalent etching depth.
It is worth noting that, the preparation method of the three-dimensional storage of foregoing teachings description is only to the spiritual three of the present invention
Tie up some embodiments of the application of memory preparation field.In fact, the present invention can also have more embodiments, and these
Embodiment is also not necessarily limited to prepare this technical field in three-dimensional storage, below to the present invention at least one of other field
Point embodiment illustrates.
For convenience, still following embodiment illustrated with Fig. 2 to 4.But this repeats to make merely to reducing
The workload of figure, any structure silent in the examples below that, even if being not construed as if indicating in the accompanying drawings
It is necessary structure in embodiment, more should not be construed as the essential features of the present invention.
Current embodiment is a kind of method performed etching to channel bottom.In the ongoing illustrated embodiment, this method packet
Include following steps：
First etching process is carried out to the groove 3 being formed on semiconductor structure, the side wall of wherein groove 3 is formed with first
Layer 4 and the second layer 5.The first layer 4 is different with the material of the second layer 5, and the purpose of first etching process is, removes groove
First layer 4 and the second layer 5 of 3 bottom.
Second etching process is carried out to the groove 3.In second etching process, the etching speed of first layer 4 and the second layer 5
Rate is identical.
Since in second etching process, first layer 4 is identical with the etch rate of the second layer 5, so no matter first
In etching process, whether the etch rate of first layer 4 and the second layer 5 is identical, after the second etching process, 4 He of first layer
While step will not all be formed between the second layer 5, therefore the bottom in groove 3 can be made to etch opening, ensure groove 3
Open top have preferable form.(such as with round and smooth opening) is just not necessarily to examine correspondingly, in the first etching process
Consider whether first layer 4 and the second layer 5 can form step, it can be by the first etching process only for " being etched in the bottom of groove 3
10 " this purpose of opening optimize, to obtain to the preferable etching effect in the bottom of groove 3.
Optionally, which can also have more structures.For example, in one embodiment of the invention, it should
Semiconductor structure further includes substrate 1, and be formed in that being alternately stacked by conductor layer 7 and insulating layer 6 on the substrate 1 formed it is folded
Layer 9, and extend vertically through the storage string 8 of the lamination 9.Groove 3 extends vertically through lamination 9 and reaches the surface or inside of substrate 1,
The second layer 5 be conformally formed 5 the groove inner wall, first layer 4 be then formed in the second layer 5 and substrate 1 and insulating layer 6 it
Between.The first layer 4 is also formed between conductor layer 7 and insulating layer 6 and storage string 8.
It may be used and be separately implemented at " in groove using the method that gas with various performs etching during different etching
3 bottom etches opening 10 " and " in the second etching process keep first layer 4 identical with the etch rate of the second layer 5 ".One
In a little embodiments, the first etching process is carried out to semiconductor structure with first gas, in the first etching process, to first layer with
A generation in the second layer chemically etches；With the second gas different from first gas is carried out to semiconductor structure the second quarter
Erosion process does not occur chemically to etch in the second etching process to first layer and the second layer.
Since in the second etching process, second gas does not occur chemically to etch to first layer 4 and the second layer 5.Institute
With in the second etching process second gas physical etching is all only occurred to first layer 4 and the second layer 5, it can be ensured that
First layer 4 is identical with the etch rate of the second layer 5 in two etching processes.It is alternatively possible to using inert gas as the second gas
Body.Correspondingly, it can select to be suitable for etching the gas of opening 10 as first gas in the bottom of groove 3.
Similarly with the embodiment of the aforementioned application in three-dimensional storage preparation field, in some embodiments, in groove
Bottom lithographic method can also include multiple cycle etching processes, and so that each cycle etching process includes at least one
First etching process and at least one second etching process, the interface preferably to eliminate first layer 4 and the second layer 5 may
The step of formation.
Similarly with the embodiment of the aforementioned application in three-dimensional storage preparation field, in some embodiments, cycle is carved
The quantity of erosion process can be selected between 2 times and 12 times.For example, can be 4 by the quantity set for recycling etching process
It is secondary or 10 times.
When to the embodiment that channel bottom performs etching includes multiple cycle etching processes, since this is to channel bottom
It performs etching including multiple first etching processes and the second etching process, so in each cycle etching process, first
Etching process and the second etching process can be arranged shorter.For example, first can be selected in the range of 50 seconds to 120 seconds
The duration (such as being set as 60 seconds or 100 seconds) of etching process.The second etching process is selected in the range of 10 seconds to 50 seconds
Duration.(such as being set as 20 seconds or 40 seconds)
Although the present invention is described with reference to current specific embodiment, those of ordinary skill in the art
It should be appreciated that above embodiment is intended merely to illustrate the present invention, can also be done in the case of no disengaging spirit of that invention
Go out various equivalent change or replacement, therefore, as long as to the variation of above-described embodiment, change in the spirit of the present invention
Type will all be fallen in the range of following claims.
Claims (19)
1. a kind of preparation method of three-dimensional storage, which is characterized in that include the following steps：
The insulator lamination for being alternately stacked and being formed by the first insulating layer and second insulating layer is formed on substrate；
Form the storage string for extending vertically through the insulator lamination；
Form the groove for extending vertically through the insulator lamination up to the substrate；
Remove first insulating layer；
It is conformally formed barrier layer in the vacancy left after the groove and first insulating layer are removed；
Conductor material is inserted in the vacancy, conductive layer is formed；
It is conformally formed wall in the trench；
The first etching process is carried out, with the barrier layer for removing channel bottom and the wall；
The second etching process is carried out, in second etching process so as to the etching of the barrier layer and the wall
Rate is identical.
2. the preparation method of three-dimensional storage according to claim 1, it is characterised in that：In first etching process
In, barrier layer and/or wall are chemically etched using first gas；
Second etching process, in second etching process, institute are carried out using the second gas different from the first gas
It states second gas barrier layer and wall are not occurred chemically to etch.
3. the preparation method of three-dimensional storage according to claim 2, it is characterised in that：The first gas is to contain fluorine gas
Body, the second gas are inert gases.
4. the preparation method of three-dimensional storage according to claim 2 or 3, it is characterised in that：It is etched described first
The lower limit for the bias that the first gas and the second gas are applied in journey and second etching process be 600 volts or
800 volts；
The first gas and the second gas are applied in first etching process and second etching process
The upper limit of bias is 1500 volts or 2000 volts；
The bias of second etching process is less than or equal to the bias of first etching process.
5. the preparation method of three-dimensional storage according to claim 4, it is characterised in that：First etching process when
The long upper limit is 400 seconds or 480 seconds, and the lower limit of the duration of first etching process is 200 seconds or 240 seconds；
The upper limit of the duration of second etching process is 160 seconds or 200 seconds, and the lower limit of the duration of second etching process is
40 seconds or 80 seconds.
6. the preparation method of three-dimensional storage according to claim 1, it is characterised in that：The material of barrier layer is oxidation
One or more combinations in aluminium, hafnium oxide, lanthana, yttrium oxide and tantalum oxide.
7. the preparation method of three-dimensional storage according to claim 6, it is characterised in that：The thickness of the barrier layer of formation
Range is 2-5 nanometers.
8. the preparation method of three-dimensional storage according to claim 1, it is characterised in that：The material of wall is nitridation
One or more combinations in silicon, silica and silicon oxynitride.
9. the preparation method of three-dimensional storage according to claim 8, it is characterised in that：The thickness of the wall of formation
Range is 20 nanometers to 40 nanometers.
10. the preparation method of three-dimensional storage according to any one of claim 1-3, it is characterised in that：Including multiple
Recycle etching process, each cycle etching process includes at least one first etching process and at least one second etched
Journey.
11. the preparation method of three-dimensional storage according to claim 10, it is characterised in that：The cycle etching process
The lower limit of quantity is 2 times or 4 times, and the upper limit of the quantity of the cycle etching process is 10 times or 12 times；
In each cycle etching process, the upper limit of the duration of first etching process is 100 seconds or 120 seconds, described
The lower limit of the duration of first etching process is 50 seconds or 60 seconds；
In each cycle etching process, the upper limit of the duration of second etching process is 40 seconds or 50 seconds, described
The lower limit of the duration of two etching processes is 10 seconds or 20 seconds.
12. the preparation method of three-dimensional storage according to claim 10, it is characterised in that：The multiple cycle is etched
The technological parameter of multiple first etching processes of journey is identical, the work of multiple second etching processes of the multiple cycle etching process
Skill parameter is identical.
13. the preparation method of three-dimensional storage according to claim 10, it is characterised in that：The multiple cycle is etched
The equivalent etching depth of the second etching process in the last one cycle etching process in journey is carved more than at least one cycle
The equivalent etching depth of the second etching process in cycle etching process before erosion process.
14. a kind of channel bottom lithographic method, which is characterized in that include the following steps：
First etching process is carried out to the groove being formed on semiconductor structure；The side wall of the groove is formed with first layer and
Two layers, the first layer is different with the material of the second layer；First etching process is for removing the first of channel bottom
Layer and the second layer；
Second etching process, in second etching process, the etch rate of first layer and the second layer are carried out to the groove
It is identical.
15. channel bottom lithographic method according to claim 14, it is characterised in that：The semiconductor structure further includes lining
Bottom, formed on substrate the lamination formed is alternately stacked by conductor layer and insulating layer, and extend vertically through depositing for the lamination
Storage string；
The groove vertical is through the lamination until the substrate, the second layer are conformally formed in the groove
Wall, the first layer are formed between the second layer and the substrate and the insulating layer, and the first layer is also formed in institute
It states between conductor layer and the insulating layer and the storage string.
16. the channel bottom lithographic method according to claims 14 or 15, it is characterised in that：With first gas to described half
Conductor structure carries out the first etching process, in first etching process, to a hair in the first layer and the second layer
Biochemical property etching；
The second etching process is carried out to the semiconductor structure with the second gas different from the first gas, described second
In etching process, the first layer and the second layer are not occurred chemically to etch.
17. channel bottom lithographic method according to claim 16, it is characterised in that：The first gas is suitable in institute
The gas that channel bottom etches opening is stated, the second gas is inert gas.
18. the channel bottom lithographic method according to claims 14 or 15, it is characterised in that：It is etched including multiple cycles
Journey, each cycle etching process includes at least one first etching process and at least one second etching process.
19. channel bottom lithographic method according to claim 18, it is characterised in that：The quantity of the cycle etching process
Lower limit be 2 times or 4 times, the upper limit of quantity of the cycle etching process is 10 times or 12 times；
In each cycle etching process, the upper limit of the duration of first etching process is 100 seconds or 120 seconds, described
The lower limit of the duration of first etching process is 50 seconds or 60 seconds；
In each cycle etching process, the upper limit of the duration of second etching process is 40 seconds or 50 seconds, described
The lower limit of the duration of two etching processes is 10 seconds or 20 seconds.
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