CN112069016A

CN112069016A - Test tool for SIP chip

Info

Publication number: CN112069016A
Application number: CN202010786770.9A
Authority: CN
Inventors: 袁坤
Original assignee: Tianjin Embedtec Co Ltd
Current assignee: Tianjin Embedtec Co Ltd
Priority date: 2020-08-07
Filing date: 2020-08-07
Publication date: 2020-12-11

Abstract

The invention discloses a test tool for an SiP chip, which comprises an interface conversion plate, an SIP chip test bottom plate and an SIP chip test adapter plate, wherein the SIP chip test bottom plate comprises an FPGA module and a power supply module; the SIP chip testing adapter plate comprises a minimum system unit including an SIP chip, a connector and a power supply module, wherein a standard connector is used for connecting a power supply to the SIP chip testing base plate, the power supply module is used for converting the power supply required by the SIP chip, and a SIP testing seat is used for connecting a pin of the SIP chip to the standard connector. The invention has the advantages that: only the SIP chip test adapter plate in the whole set of test tool needs to be customized according to different SIP chips, so that the development cost and the period can be greatly reduced, and the test efficiency of the SIP chips is improved.

Description

Test tool for SIP chip

Technical Field

The invention relates to the field of intelligent testing, in particular to a test tool for an SIP chip.

Background

SIP packaging (System On a Package) is a Package In which a plurality of functional wafers, including functional wafers such as processors and memories, are integrated, thereby implementing a substantially complete function, corresponding to an SOC (System On a Chip) Chip. The difference of SIP is that system-in-package is a side-by-side or stacked package with different wafers, and SOC is a highly integrated chip product. SIP encapsulates a plurality of semiconductor chips and passive devices in the same chip to form a system-level chip, and a PCB is not used as a carrier for bearing the connection of the chips, so that the problem that the system performance is bottleneck due to the inherent deficiency of the PCB can be solved. For example, the processor and the memory chip are used, because the density of the internal traces of the system-in-package can be much higher than that of the traces of the PCB, the system bottleneck caused by the line width of the PCB is solved. For example, because the memory chip and the processor chip can be connected together by means of punching, the limitation of the line width of the PCB is eliminated, and the increase of the data bandwidth on the interface bandwidth can be realized.

Just because of the flexibility of SIP, the differences between SIP chips are large, and there are large differences from package to pin definition. Every SIP chip of design all needs a corresponding design test fixture rather than the adaptation, and at present, there is not a general test fixture that can once only test many kinds of SIP chips in the test field. Therefore, in order to save development cost and improve the testing efficiency of the chip, the invention provides a testing tool of the SIP chip.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provides a test tool for a SiP chip.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a test tool for a SiP chip comprises an interface conversion plate, an SIP chip test bottom plate and an SIP chip test adapter plate, wherein the SIP chip test bottom plate comprises an FPGA module and a power supply module; the SIP chip testing adapter plate comprises a minimum system unit including an SIP chip, a connector and a power supply module, wherein a standard connector is used for connecting a power supply to the SIP chip testing base plate, the power supply module is used for converting the power supply required by the SIP chip, and a SIP testing seat is used for connecting a pin of the SIP chip to the standard connector.

The SIP chip testing bottom plate comprises an FPGA module and a power supply module, wherein the FPGA module consists of an FPGA chip of an Altera company and a serial configuration device as a program memory of the FPGA module; the FPGA module accesses all leading-out pins of the SIP chip into pins of the FPGA module through a standard connector, and the functions of the pins are transferred and tested through the logic of the FPGA module; the power supply module converts the input voltage into 5V and 3.3V and is connected into the SIP chip test adapter board through the standard connector.

The interface conversion board is also connected with the SIP chip testing bottom board by using a standard connector, and the connector is connected with the converter and is used for converting TTL signals introduced by the FPGA through the connector into various bus signals including CAN bus signals, RS232 signals, RS485 bus signals, RS422 bus signals and the like.

The invention has the advantages that: the SIP chip test adopts a flexible modular measurement method, wherein an SIP chip test bottom plate and an interface conversion plate are standard board cards, the interface conversion plate CAN be made into various types, similar TTL signal to RS232 signal plates, TTL signal to CAN bus plates, TTL signal to RS422 bus plates and the like are all standard board cards, and different interface conversion plates CAN be used according to different SIP chips; only the SIP chip test adapter plate in the whole set of test tool needs to be customized according to different SIP chips, so that the development cost and the period can be greatly reduced, and the test efficiency of the SIP chips is improved.

Drawings

Fig. 1 is a connection diagram of an overall structure of a test fixture for an SIP chip according to the present invention.

Fig. 2 is a schematic block diagram of an automatic switching circuit of a bottom board program memory of an SIP chip according to the present invention.

Detailed Description

The invention is described in further detail below with reference to the figures and the detailed description.

As shown in fig. 1, a test tool for SiP chips includes an interface conversion board 1, an SiP chip test board 2, and an SiP chip test adapter board 3, where the SiP chip test board 2 includes an FPGA module 21 and a power supply module 22; the SIP chip testing adapter plate 3 comprises a minimum system unit including a SIP chip 31, a connector 32 and a power module 33, wherein a power supply is connected to the SIP chip testing bottom plate 2 through a standard connector, the power module 33 is used for converting the power supply required by the SIP chip, and a pin of the SIP chip is connected to the standard connector through a SIP testing seat.

The SIP chip testing bottom plate 2 comprises an FPGA module 21 and a power supply module 22, wherein the FPGA module consists of an FPGA chip EP4CE30 of Altera company and eight EPCS16 as a program memory 23 of the FPGA module, when each SIP chip is tested, only one program memory 23 can be accessed to the FPGA module 21, and according to the access of the SIP chip testing adapter plate, the SIP chip testing bottom plate 2 can automatically select (the principle of the program memory automatic switching circuit is shown in figure 2) the corresponding program memory to be accessed to the FPGA module; the FPGA module 21 accesses all leading-out pins of the SIP chip into pins of the FPGA module through a standard connector, and the functions of the pins are switched and tested through the logic of the FPGA module 21; the power supply module 22 converts the input voltage to 5V and 3.3V using the ADI LTM4644 to be plugged into the SIP chip test patch board through standard connectors.

The interface conversion board 1 is also connected with the SIP chip testing bottom board 2 by using a standard connector 11, and the connector 11 is connected with a converter 12 and used for converting TTL signals introduced by the FPGA module through the connector into various bus signals including CAN bus signals, RS232 signals, RS485 bus signals and RS422 bus signals.

The SIP chip test adopts a flexible modular measurement method, wherein an SIP chip test bottom plate and an interface conversion plate are standard board cards, the interface conversion plate CAN be made into various types, similar TTL signal to RS232 signal plates, TTL signal to CAN bus plates, TTL signal to RS422 bus plates and the like are all standard board cards, and different interface conversion plates CAN be used according to different SIP chips; only the SIP chip test adapter plate in the whole set of test tool needs to be customized according to different SIP chips, so that the development cost and the period can be greatly reduced, and the test efficiency of the SIP chips is improved.

The above examples are merely for illustrative clarity and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.

Claims

1. A test tool for a SiP chip is characterized by comprising an interface conversion plate, an SIP chip test bottom plate and an SIP chip test conversion plate which are sequentially connected, wherein the SIP chip test bottom plate comprises an FPGA module and a power supply module; the SIP chip testing adapter plate comprises a minimum system unit comprising an SIP chip, a connector and a power module, wherein the SIP chip testing adapter plate adopts a standard connector to connect a power supply from the SIP chip testing bottom plate, and the power module is used for converting the power supply required by the SIP chip.

2. The test tool of the SiP chip of claim 1, wherein the FPGA module of the SiP chip test board is provided with a serial configuration device as a program memory of the FPGA module, only one program memory can be accessed to the FPGA module when one SiP chip is tested, and the SiP chip test board selects the corresponding program memory to be accessed to the FPGA module according to the access of the SiP chip test adapter board; and the FPGA module accesses all leading-out pins of the SIP chip into pins of the FPGA module through a standard connector, and the functions of the pins are switched and tested through the logic of the FPGA module.

3. The test fixture of SiP chip of claim 1, wherein the power supply module converts input voltage to 5V and 3.3V for connection to an SiP chip test adapter board via standard connectors.

4. The SiP chip testing tool of claim 1, wherein the interface conversion board is connected to the SiP chip testing backplane by using a standard connector, and the connector is connected to the converter and is configured to convert TTL signals introduced by the FPGA module through the connector into various bus signals, including CAN bus signals, RS232 signals, RS485 bus signals, and RS422 bus signals.