CN112053822A - Manufacturing process of negative temperature coefficient resistor - Google Patents
Manufacturing process of negative temperature coefficient resistor Download PDFInfo
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- CN112053822A CN112053822A CN202010923962.XA CN202010923962A CN112053822A CN 112053822 A CN112053822 A CN 112053822A CN 202010923962 A CN202010923962 A CN 202010923962A CN 112053822 A CN112053822 A CN 112053822A
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- ceramic substrate
- temperature coefficient
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/06—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
- H01C17/065—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thick film techniques, e.g. serigraphy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/006—Apparatus or processes specially adapted for manufacturing resistors adapted for manufacturing resistor chips
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/28—Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals
- H01C17/281—Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals by thick film techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/30—Apparatus or processes specially adapted for manufacturing resistors adapted for baking
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
- H01C7/04—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material having negative temperature coefficient
- H01C7/049—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material having negative temperature coefficient mainly consisting of organic or organo-metal substances
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Abstract
The invention provides a manufacturing process of a negative temperature coefficient resistor, and relates to the technical field of negative temperature coefficient resistors. The manufacturing process of the negative temperature coefficient resistor comprises the steps of back electrode printing, front surface printing, resistance layer printing and sintering, protection layer printing and sintering, heat treatment, strip folding, side electrode printing, grain folding, electroplating, package sorting and inspection and the like. The negative temperature coefficient resistor can be suitable for a patch and a small-size negative temperature coefficient resistor, and can better meet the requirement that the size of the conventional electronic equipment is smaller and smaller.
Description
Technical Field
The invention relates to the field of negative temperature coefficient resistors, in particular to a manufacturing process of a negative temperature coefficient resistor.
Background
Negative temperature coefficient resistor (NTC), a type of sensor resistance whose resistance value decreases with increasing temperature.
Currently, negative temperature coefficient resistors include monolithic types and multilayer ceramic laminate types. The monolithic NTC is made of NTC ceramic with brick size by the existing ceramic manufacturing process, and then the ceramic brick is cut into the required packaging size by a precise linear cutting process. The main manufacturing technology of the multi-layer ceramic laminated NTC is to prepare ceramic sheets, then to stack them and press them into plate blanks to be sintered, and finally to precisely cut the sintered NTC ceramic plate. Since the monolithic type NTC and the multi-layer ceramic laminated type NTC are more suitable for manufacturing NTC products with pins and assembled structures, but are not suitable for manufacturing patch type NTC products. Due to the development of electronic device technology, the monolithic NTC and the multi-layer ceramic laminated NTC of the prior art have failed to meet the demand of smaller and smaller electronic devices.
In view of the above, the inventors of the present invention have made a study of the prior art and then have made the present application.
Disclosure of Invention
The invention provides a manufacturing process of a negative temperature coefficient resistor, which aims to improve the negative temperature coefficient resistor in the prior art and cannot meet the requirement that the volume of the traditional electronic equipment is smaller and smaller.
In order to solve the above technical problem, the present invention provides a manufacturing process of a negative temperature coefficient resistor, comprising the following steps:
s1: preparing a paste product, printing the paste product on a ceramic substrate, and sintering the ceramic substrate;
s2: printing the back surface of the ceramic substrate to form a plurality of back electrodes which are not connected with each other;
s3: printing the front surface of the ceramic substrate to form a plurality of front electrodes which are not connected with each other, and sintering the ceramic substrate;
s4: printing a layer of semiconductor ceramic on the front surface of the ceramic substrate to form a first resistance layer, and sintering the first resistance layer; the first resistance layer comprises a plurality of mutually independent first resistance areas, and two ends of each first resistance area are respectively lapped on two adjacent back electrodes;
s5: printing a layer of semiconductor ceramic on the first resistance layer to form a second resistance layer, and sintering the second resistance layer, wherein the second resistance layer covers the first resistance layer;
s6: printing a protective layer on the front surface of the ceramic substrate, and sintering the protective layer, wherein the protective layer covers the second resistance layer;
s7: performing heat treatment on the ceramic substrate;
s8: folding the ceramic substrate to split the ceramic substrate into a plurality of strip-shaped ceramic bodies;
s9: forming side electrodes on the side surfaces of the ceramic substrate after the folding, wherein the side electrodes are electrically connected with the corresponding back electrodes and the front electrodes;
s10: folding the ceramic substrate after folding the strips to form a plurality of ceramic particles;
s11: and electroplating the ceramic grains formed by the folded grains to form the negative temperature coefficient resistor.
Preferably, in step S3, the front electrodes are cut by violet light so that the two ends of the front electrodes extend toward each other, and the front electrodes are engaged with each other and are not connected to each other.
3. The manufacturing process of negative temperature coefficient resistor as claimed in claim 1, wherein the sintering temperature in the steps S1, S3, S4 and S5 is 700-850 ℃.
As a further optimization, the step S6 further includes the following steps:
s61: printing a first protective layer on the surface of the second resistance layer, and drying at 150-180 ℃, wherein the first protective layer covers the second resistance layer;
s62: printing a second protective layer on the surface of the first protective layer, and sintering at the temperature of 220-280 ℃.
As a further optimization, the step S7 further includes the following steps:
s71: cooling the ceramic substrate subjected to the S6 for 4-12H at normal temperature;
s72: sintering the ceramic substrate at 220-280 ℃.
As a further optimization, in the above steps S8 and S10, folding and grain folding are performed by using a rolling device, respectively.
As a further optimization, in the above step S9, the side electrodes are formed by vacuum sputtering.
As a further optimization, step S11 includes performing nickel and tin electroplating.
As a further optimization, the method also comprises the following steps:
s12: and magnetizing the negative temperature coefficient resistor so as to remove defective products.
By adopting the technical scheme, the invention can obtain the following technical effects:
1. the manufacturing process for the negative temperature coefficient resistor can be suitable for a negative temperature coefficient resistor which is small in size and is attached to a patch, and can better meet the requirement that the size of the conventional electronic equipment is smaller and smaller.
2. In step S3, the manufacturing process for the negative temperature coefficient resistor of the present invention utilizes violet cutting to form a front electrode with precise dimensions, thereby greatly improving the resistance precision of the negative temperature coefficient resistor.
3. According to the manufacturing process for the negative temperature coefficient resistor, in step S6, the first protection layer and the second protection layer are formed through two different sintering temperatures, wherein the first protection layer can perform better bonding function, and the second protection layer can perform better protection function.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a schematic diagram of a back electrode according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a front electrode structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a resistive layer according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a passivation layer according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a front electrode according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of a negative temperature coefficient resistor according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a process for fabricating a negative temperature coefficient resistor according to an embodiment of the present invention;
the labels in the figure are: 1-a ceramic substrate; 2-a front electrode; 3-a back electrode; 4-a lateral electrode; 5-a resistive layer; 6-a protective layer; 7-a nickel layer; 8-tin layer; 9-first resistive region.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the equipment or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The invention is described in further detail below with reference to the following detailed description and accompanying drawings:
as shown in fig. 6 and 7, the present embodiment provides a manufacturing process of a negative temperature coefficient resistor, which is mainly used for a 47 Ω -2M chip resistor, and includes steps S1 to S12, and specifically includes: printing the back electrode 3, printing the front surface, printing and sintering the resistance layer 5, printing and sintering the protective layer 6, performing heat treatment, folding strips, printing the side electrode 4, folding particles, electroplating, and sorting and inspecting packets. The details are as follows:
as shown in FIGS. 6 and 7, in step S1, the paste is first prepared and printed on the ceramic substrate 1, and then the ceramic substrate 1 is fired. Specifically, according to the requirement of the B value, two semiconductor ceramics with the B values of 2750K and 4100K are mixed to obtain a required paste product, the paste product is printed on the ceramic substrate 1, and then the substrate is sent into a sintering furnace to be sintered at the high temperature of 700-850 ℃ so that the paste product layer can be sintered with the substrate. Then, the resistance values displayed at 25 ℃ and 85 ℃ of the same point can be measured in a constant-temperature oil groove, and the B value can be calculated to determine whether the requirement is met.
As shown in fig. 1 and 6, step S2: the back surface of the ceramic substrate 1 is printed to form a plurality of back electrodes 3 which are not connected to each other. As shown in fig. 1, the stripe-shaped back electrodes 3 are vertically arranged, and the adjacent stripe-shaped back electrodes 3 are not connected to each other.
As shown in fig. 2 and 6, step S3: printing the front surface of the ceramic substrate 1 to form a plurality of front electrodes 2 which are not connected with each other, and sintering the ceramic substrate 1. As shown in fig. 2, the strip-shaped front electrodes 2 are vertically arranged, and the adjacent strip-shaped front electrodes 2 are not connected to each other. After the front electrode 2 is formed by printing, the substrate is sent into a sintering furnace to be sintered at a high temperature of 700-850 ℃ so that the back electrode 3 and the front electrode 2 can be sintered with the substrate.
In the present embodiment, both ends of the front electrode 2 are extended toward each other by violet cutting, and a structure that is engaged with and disconnected from each other is formed. The front electrode 2 formed in this manner can greatly improve the resistance accuracy of the negative temperature coefficient resistor due to its high dimensional accuracy.
Of course, in another embodiment, as shown in fig. 5, the pattern of the front electrode 2 may be designed in advance and formed directly by printing. Specifically, the front electrode 2 may be designed with different patterns according to different resistance values, which is not described herein again.
As shown in fig. 3 and 6, step S4: printing a layer of semiconductor ceramic on the front surface of the ceramic substrate 1 to form a first resistance layer, and sintering the first resistance layer at a high temperature of 700-850 ℃ to enable the first resistance layer to be sintered with the ceramic substrate 1. The first resistance layer includes a plurality of mutually independent first resistance regions 9, and two ends of the first resistance regions 9 are respectively lapped on two adjacent back electrodes 3. In particular, these first resistive regions 9 may electrically connect adjacent strip-shaped front electrodes 2.
As shown in fig. 3 and 6, step S5: printing a layer of semiconductor ceramic on the first resistance layer to form a second resistance layer, and sintering the second resistance layer at the high temperature of 700-850 ℃ to enable the second resistance layer to be sintered with the first resistance layer and the ceramic substrate 1. Wherein the second resistive layer completely covers the first resistive layer.
As shown in fig. 4 and 6, step S6: a protective layer 6 is printed on the front surface of the ceramic substrate 1, and the protective layer 6 is sintered, so that the protective layer 6 covers the second resistance layer. Specifically, step S6 is divided into the following steps:
s61: printing a first protective layer on the surface of the second resistance layer, and drying at 150-180 ℃, wherein the first protective layer covers the second resistance layer;
s62: printing a second protective layer on the surface of the first protective layer, and sintering at 220-280 ℃.
Through the above operation, the negative temperature coefficient resistor of the present embodiment has two protective layers 6 of the first protective layer and the second protective layer. And two protective layers 6 are formed by two different sintering temperatures, so that the first protective layer can play a better bonding role, and the second protective layer can play a better protection role. It should be noted that the positions of the first protective layer and the second protective layer need to be completely consistent, and the second protective layer can completely cover the first resistive layer and the second resistive layer.
As shown in fig. 6 and 7, step S7: the ceramic substrate 1 is subjected to heat treatment. Specifically, step S7 includes the following steps:
s71: cooling the ceramic substrate 1 subjected to the S6 for 4-12H at normal temperature;
s72: sintering the ceramic substrate 1 at 220 to 280 ℃.
As shown in fig. 6 and 7, step S8: the ceramic substrate 1 is folded by a rolling device to split the ceramic substrate 1 into a plurality of strip-shaped ceramic bodies. Step S9: by vacuum sputtering, the side electrodes 4 are formed on the side surfaces of the ceramic substrate 1 after the folding, and the side electrodes 4 can be electrically connected to the corresponding back electrodes 3 and front electrodes 2. Step S10: and folding the ceramic substrate 1 by using a rolling device to form ceramic grains. Step S11: and electroplating the ceramic grains formed by the folded grains to form the negative temperature coefficient resistor. It should be noted that, as shown in fig. 6, step S11 includes performing nickel and tin electroplating, specifically, feeding the ceramic particles formed into particles into an electroplating bath to perform nickel and tin electroplating, forming the nickel layer 7 to protect the front electrode 2, and forming the tin layer 8 to solder the negative temperature coefficient resistor onto the PCB.
In addition, as shown in fig. 7, the manufacturing process of the negative temperature coefficient resistor of this embodiment further includes step S12: and sorting and detecting the negative temperature coefficient resistor. Specifically, step S12 includes magnetizing the negative temperature coefficient resistor to remove defective products. Meanwhile, a certain number of negative temperature coefficient resistors are taken and measured in the constant temperature oil groove, and the production is continued when the resistance value is within an expected range. If the resistance value is not in the expected range, the operation is repeated after the safety parameter is set until the yield of the spot inspection reaches 100 percent, and the production can be continued. Wherein, magnetizing and magnetic separation are carried out, which belongs to the prior art in the field and is not described herein again.
Through the above scheme of this embodiment, the manufacturing process of the negative temperature coefficient resistor of this embodiment is not only simple in process, but also the formed negative temperature coefficient resistor is small in size, can be suitable for a negative temperature coefficient resistor which is small in size and is mounted on a chip, and can better meet the demand that the size of the electronic equipment is smaller and smaller nowadays. Meanwhile, the negative temperature coefficient resistor of the embodiment has better structural strength and improves the reliability through the structures of the first protection layer, the second protection layer, the first resistance layer and the second resistance layer.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A manufacturing process of a negative temperature coefficient resistor is characterized by comprising the following steps:
s1: preparing a paste, printing the paste on a ceramic substrate (1), and sintering the ceramic substrate (1);
s2: printing the back surface of the ceramic substrate (1) to form a plurality of back electrodes (3) which are not connected with each other;
s3: printing the front surface of the ceramic substrate (1) to form a plurality of front electrodes (2) which are not connected with each other, and sintering the ceramic substrate (1);
s4: printing a layer of semiconductor ceramic on the front surface of the ceramic substrate (1) to form a first resistance layer, and sintering the first resistance layer; the first resistance layer comprises a plurality of mutually independent first resistance areas (9), and two ends of each first resistance area (9) are respectively lapped on two adjacent back electrodes (3);
s5: printing a layer of semiconductor ceramic on the first resistance layer to form a second resistance layer, and sintering the second resistance layer, wherein the second resistance layer covers the first resistance layer;
s6: printing a protective layer (6) on the front surface of the ceramic substrate (1), sintering the protective layer (6), and covering the protective layer (6) on the second resistance layer;
s7: heat-treating the ceramic substrate (1);
s8: folding the ceramic substrate (1) to split the ceramic substrate (1) into a plurality of strip-shaped ceramic bodies;
s9: forming a side electrode (4) on the side surface of the ceramic substrate (1) after the folding, wherein the side electrode (4) is electrically connected with the corresponding back electrode (3) and the front electrode (2);
s10: folding the ceramic substrate (1) after folding to form a plurality of ceramic particles;
s11: and electroplating the ceramic grains formed by the folded grains to form the negative temperature coefficient resistor.
2. The manufacturing process of a negative temperature coefficient resistor according to claim 1, wherein in step S3, the two ends of the front electrode (2) are extended oppositely by violet cutting to form a mutually engaged and unconnected structure.
3. The manufacturing process of negative temperature coefficient resistor as claimed in claim 1, wherein the sintering temperature in the steps S1, S3, S4 and S5 is 700-850 ℃.
4. The process of claim 1, wherein the step S6 further comprises the steps of:
s61: printing a first protective layer on the surface of the second resistance layer, and drying at 150-180 ℃, wherein the first protective layer covers the second resistance layer;
s62: printing a second protective layer on the surface of the first protective layer, and sintering at the temperature of 220-280 ℃.
5. The process of claim 1, wherein the step S7 further comprises the steps of:
s71: cooling the ceramic substrate (1) subjected to the S6 for 4-12H at normal temperature;
s72: sintering the ceramic substrate (1) at 220-280 ℃.
6. The manufacturing process of negative temperature coefficient resistor as claimed in claim 1, wherein in steps S8 and S10, the folding and the grain folding are performed by a rolling device, respectively.
7. The process of claim 1, wherein in step S9, the side electrode (4) is formed by vacuum sputtering.
8. The process of claim 1, wherein step S11 includes electroplating with nickel and tin.
9. The process of claim 1, further comprising the steps of:
s12: and magnetizing the negative temperature coefficient resistor so as to remove defective products.
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| CN202010923962.XA CN112053822A (en) | 2020-09-04 | 2020-09-04 | Manufacturing process of negative temperature coefficient resistor |
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| CN202010923962.XA CN112053822A (en) | 2020-09-04 | 2020-09-04 | Manufacturing process of negative temperature coefficient resistor |
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Application publication date: 20201208 |