CN112053724A - Memory control method, memory storage device and memory control circuit unit - Google Patents

Memory control method, memory storage device and memory control circuit unit Download PDF

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Publication number
CN112053724A
CN112053724A CN201910490689.3A CN201910490689A CN112053724A CN 112053724 A CN112053724 A CN 112053724A CN 201910490689 A CN201910490689 A CN 201910490689A CN 112053724 A CN112053724 A CN 112053724A
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Prior art keywords
memory
soft information
read
physical
cell
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CN201910490689.3A
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CN112053724B (en
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林纬
许祐诚
林晓宜
杨宇翔
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a memory control method, a memory storage device and a memory control circuit unit. The method comprises the following steps: reading a first physical unit of the plurality of physical units based on a first electrical setting to obtain first soft information; reading the first physical cell based on a second electrical setting different from the first electrical setting to obtain second soft information; classifying a plurality of storage units in the first entity unit according to the first soft information and the second soft information; and decoding the data read from the first physical unit according to the classification result of the plurality of memory cells.

Description

Memory control method, memory storage device and memory control circuit unit
Technical Field
The present invention relates to a memory control technology, and more particularly, to a memory control method, a memory storage device, and a memory control circuit unit.
Background
Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.
Memory storage devices store data in a manner that changes the threshold voltage of a memory cell. However, the threshold voltage of a memory cell may vary under different electrical and/or temperature conditions. In addition, the sensitivity of multiple memory cells in the same memory storage device to changes in electrical and/or temperature conditions may also vary due to process variations. Therefore, when the electrical condition and/or the temperature condition change, if the same decoding setting is continuously adopted to decode the data read from the memory cells, the data decoding efficiency and/or the data access efficiency of the memory storage device may be greatly reduced.
Disclosure of Invention
The invention provides a memory control method, a memory storage device and a memory control circuit unit, which can improve the problems.
An exemplary embodiment of the present invention provides a memory control method for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity units, and the memory control method comprises the following steps: reading a first physical cell of the plurality of physical cells based on a first electrical setting to obtain first soft information; reading the first physical cell based on a second electrical setting to obtain second soft information, wherein the first electrical setting is different from the second electrical setting; classifying a plurality of storage units in the first entity unit according to the first soft information and the second soft information; and decoding the data read from the first physical unit according to the classification results of the plurality of storage units.
In an exemplary embodiment of the present invention, the step of reading the first physical unit of the plurality of physical units to obtain the first soft information based on the first electrical setting includes: reading the first physical cell using a plurality of first read voltage levels corresponding to the first electrical setting to obtain the first soft information, and reading the first physical cell based on the second electrical setting to obtain the second soft information comprises: reading the first physical cell using a plurality of second read voltage levels corresponding to the second electrical setting to obtain the second soft information.
In an exemplary embodiment of the present invention, the step of classifying the plurality of storage units in the first physical unit according to the first soft information and the second soft information comprises: classifying a first memory cell of the plurality of memory cells as a first class of memory cells or a second class of memory cells according to the first soft information and the second soft information, wherein a sensitivity of the first class of memory cells to a change in an electrical parameter is different from a sensitivity of the second class of memory cells to a change in the electrical parameter.
In an exemplary embodiment of the present invention, the step of classifying the plurality of storage units in the first physical unit according to the first soft information and the second soft information comprises: obtaining a relative voltage position of a first memory cell in the plurality of memory cells in a plurality of critical voltage distributions according to the first soft information and the second soft information; and sorting the first memory cells according to the relative voltage locations of the first memory cells in the plurality of threshold voltage distributions.
In an exemplary embodiment of the present invention, the decoding the data read from the first physical unit according to the classification result of the plurality of memory cells includes: determining first reliability information corresponding to a first storage unit in the plurality of storage units according to a classification result of the first storage unit; and decoding data read from the first memory cell according to the first reliability information.
An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of entity units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is configured to send a first read command sequence instructing to read a first physical unit of the plurality of physical units based on a first electrical setting to obtain first soft information. The memory control circuit unit is also configured to send a second read command sequence instructing to read the first physical unit based on a second electrical setting to obtain second soft information, wherein the first electrical setting is different from the second electrical setting. The memory control circuit unit is further configured to classify a plurality of memory cells in the first physical unit according to the first soft information and the second soft information, and the memory control circuit unit is further configured to decode data read from the first physical unit according to classification results of the plurality of memory cells.
In an example embodiment of the present invention, the first read command sequence indicates to read the first physical cell using a plurality of first read voltage levels corresponding to the first electrical setting to obtain the first soft information, and the second read command sequence indicates to read the first physical cell using a plurality of second read voltage levels corresponding to the second electrical setting to obtain the second soft information.
In an exemplary embodiment of the invention, the operation of the memory control circuit unit classifying the plurality of memory cells in the first physical unit according to the first soft information and the second soft information includes: classifying a first memory cell of the plurality of memory cells as a first class of memory cells or a second class of memory cells based on the first soft information and the second soft information, wherein a sensitivity of the first class of memory cells to a change in an electrical parameter is different from a sensitivity of the second class of memory cells to a change in the electrical parameter.
In an exemplary embodiment of the invention, the operation of the memory control circuit unit classifying the plurality of memory cells in the first physical unit according to the first soft information and the second soft information includes: obtaining a relative voltage position of a first memory cell in the plurality of memory cells in a plurality of critical voltage distributions according to the first soft information and the second soft information; and sorting the first memory cells according to the relative voltage locations of the first memory cells in the plurality of threshold voltage distributions.
In an exemplary embodiment of the present invention, the operation of the memory control circuit unit decoding the data read from the first physical unit according to the classification result of the plurality of memory cells includes: determining first reliability information corresponding to a first storage unit in the plurality of storage units according to a classification result of the first storage unit; and decoding data read from the first memory cell according to the first reliability information.
An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity units. The memory control circuit unit comprises a host interface, a memory interface, an error checking and correcting circuit and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable nonvolatile memory module. The memory management circuitry is coupled to the host interface, the memory interface, and the error checking and correcting circuitry. The memory management circuit is configured to send a first read command sequence instructing to read a first physical unit of the plurality of physical units based on a first electrical setting to obtain first soft information. The memory management circuit is also configured to send a second sequence of read instructions that direct reading of the first physical unit for second soft information based on a second electrical setting, wherein the first electrical setting is different from the second electrical setting. The memory management circuit is further configured to classify a plurality of memory cells in the first physical cell according to the first soft information and the second soft information, and the error checking and correcting circuit is configured to decode data read from the first physical cell according to a classification result of the plurality of memory cells.
In an example embodiment of the present invention, the first read command sequence indicates to read the first physical cell using a plurality of first read voltage levels corresponding to the first electrical setting to obtain the first soft information, and the second read command sequence indicates to read the first physical cell using a plurality of second read voltage levels corresponding to the second electrical setting to obtain the second soft information.
In an example embodiment of the present invention, the operation of the memory management circuit classifying the plurality of memory cells in the first physical unit according to the first soft information and the second soft information includes: classifying a first memory cell of the plurality of memory cells as a first class of memory cells or a second class of memory cells according to the first soft information and the second soft information, wherein a sensitivity of the first class of memory cells to a change in an electrical parameter is different from a sensitivity of the second class of memory cells to a change in the electrical parameter.
In an example embodiment of the present invention, the operation of the memory management circuit classifying the plurality of memory cells in the first physical unit according to the first soft information and the second soft information includes: obtaining a relative voltage position of a first memory cell in the plurality of memory cells in a plurality of critical voltage distributions according to the first soft information and the second soft information; and sorting the first memory cells according to the relative voltage locations of the first memory cells in the plurality of threshold voltage distributions.
In an exemplary embodiment of the present invention, the operation of the error checking and correcting circuit decoding the data read from the first physical unit according to the classification result of the plurality of memory cells includes: determining first reliability information corresponding to a first storage unit in the plurality of storage units according to a classification result of the first storage unit; and decoding data read from the first memory cell according to the first reliability information.
In an exemplary embodiment of the present invention, a current value of a first read current used based on the first electrical setting is different from a current value of a second read current used based on the second electrical setting.
In an exemplary embodiment of the invention, the classification result of the plurality of memory cells reflects at least a sensitivity of a first memory cell of the plurality of memory cells to a change in an electrical parameter.
In an exemplary embodiment of the invention, the change in the electrical parameter comprises a change in a read current.
Based on the above, after the first entity unit is read through different electrical settings to obtain the first soft information and the second soft information, the memory cells in the first entity unit can be classified according to the first soft information and the second soft information. Then, the data read from the first entity unit may be decoded according to the classification result, thereby improving data decoding efficiency and/or data access efficiency of the memory storage device.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;
FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to another example embodiment of the present invention;
FIG. 3 is a diagram illustrating a host system and a memory storage device according to another exemplary embodiment of the invention.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic block diagram illustrating a memory control circuit unit according to an exemplary embodiment of the present invention;
FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating reading of a first physical cell based on a first electrical setting and a second electrical setting in accordance with an exemplary embodiment of the present invention;
FIG. 8 is a diagram illustrating table information according to an exemplary embodiment of the present invention;
FIG. 9 is a diagram illustrating table information according to an exemplary embodiment of the present invention;
FIG. 10 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention.
Description of the reference numerals
10. 30: memory storage device
11. 31: host system
110: system bus
111: processor with a memory having a plurality of memory cells
112: random access memory
113: read-only memory
114: data transmission interface
12: input/output (I/O) device
20: main machine board
201: u disk
202: memory card
203: solid state disk
204: wireless memory storage device
205: global positioning system module
206: network interface card
207: wireless transmission device
208: keyboard with a keyboard body
209: screen
210: horn type loudspeaker
32: SD card
33: CF card
34: embedded memory device
341: embedded multimedia card
342: embedded multi-chip packaging storage device
402: connection interface unit
404: memory control circuit unit
406: rewritable nonvolatile memory module
502: memory management circuit
504: host interface
506: memory interface
508: error checking and correcting circuit
510: buffer memory
512: power management circuit
601: storage area
602: replacement area
610(0) to 610 (B): entity unit
612(0) -612 (C): logic unit
71. 72: distribution of
701-710: read voltage level
A1-F1, A2-F2: voltage range
81. 91: form information
S1001: step (reading a first physical unit of the plurality of physical units to obtain first soft information based on the first electrical setting)
S1002: step (reading the first physical unit to obtain the second soft information based on the second electrical setting)
S1003: step (classifying a plurality of memory cells in the first physical cell based on the first soft information and the second soft information)
S1004: step (decoding data read from the first physical unit based on the classification result of the plurality of memory cells)
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all connected to a system bus (system bus) 110.
In the present exemplary embodiment, the host system 11 is connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. The host system 11 is connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.
In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 can be connected to the memory storage device 10 in a wired or wireless manner. The memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be a memory storage device based on various wireless Communication technologies, such as Near Field Communication (NFC) memory storage device, wireless facsimile (WiFi) memory storage device, Bluetooth (Bluetooth) memory storage device, or Bluetooth low energy memory storage device (e.g., iBeacon). In addition, the motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded memory device 34 includes various types of embedded memory devices such as an embedded multimedia Card (eMMC) 341 and/or an embedded Multi-Chip Package (eMCP) memory device 342, which directly connects the memory module to the substrate of the host system.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.
The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 402. In the exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI) standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed (UHS-I) interface standard, the Ultra High Speed (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Memory (Flash) interface standard, the CP interface standard, the CF interface standard, the Device interface (Electronic drive interface), IDE) standard or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.
The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.
The rewritable nonvolatile memory module 406 is connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.
In the present exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 may constitute a plurality of physical programming cells, and the physical programming cells may constitute a plurality of physical erasing cells. Specifically, the memory cells on the same word line may constitute one or more physical programming cells. If each memory cell can store more than 2 bits, the physical programming cells on the same word line can be classified into at least a lower physical programming cell and an upper physical programming cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.
In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit can be a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. For example, the physical erase unit is a physical block (block).
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to FIG. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506, and an error checking and correcting circuit 508.
The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.
In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In another example embodiment, the control instructions of the memory management circuit 502 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The cell management circuit is used to manage the cells or cell groups of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.
The host interface 504 is connected to the memory management circuitry 502. The memory management circuitry 502 may communicate with the host system 11 via a host interface 504. The host interface 504 is used for receiving and recognizing commands and data transmitted from the host system 11. For example, commands and data transmitted by the host system 11 may be transmitted to the memory management circuit 502 through the host interface 504. In addition, the memory management circuitry 502 may transfer data to the host system 11 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.
The memory interface 506 is connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.
The error checking and correcting circuit 508 is connected to the memory management circuit 502 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.
In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 510 and a power management circuit 512. The buffer memory 510 is connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is connected to the memory management circuit 502 and is used to control the power of the memory storage device 10.
In an example embodiment, the rewritable nonvolatile memory module 406 of fig. 4 is also referred to as a flash (flash) memory module, and the memory control circuit unit 404 is also referred to as a flash memory controller for controlling the flash memory module. In an example embodiment, the memory management circuit 502 of FIG. 5 is also referred to as a flash memory management circuit.
FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. Referring to FIG. 6, the memory management circuit 502 can logically group the physical units 610(0) -610 (B) of the rewritable nonvolatile memory module 406 into the storage area 601 and the replacement area 602. The physical units 610(0) - (610 a) in the storage area 601 are used for storing data, and the physical units 610(a +1) - (610B) in the replacement area 602 are used for replacing damaged physical units in the storage area 601. For example, if the data read from a physical unit contains too many errors to be corrected, the physical unit is considered as a damaged physical unit. It is noted that if there are no physical erase units available in the replacement area 602, the memory management circuit 502 may declare the entire memory storage device 10 to be in a write protect (write protect) state, and no more data can be written.
In an exemplary embodiment, each physical unit is referred to as a physical programming unit. However, in another exemplary embodiment, a physical unit may also refer to a physical address, a physical erase unit, or be composed of a plurality of consecutive or non-consecutive physical addresses. The memory management circuitry 502 may configure the logic units 612(0) - (612 (C) to map the physical units 610(0) - (610 (A) in the memory area 601. In the present exemplary embodiment, each logical unit refers to a logical address. However, in another exemplary embodiment, a logic cell may also refer to a logic program cell, a logic erase cell or be composed of a plurality of continuous or discontinuous logic addresses. In addition, each of logic cells 612(0) -612 (C) may be mapped to one or more physical cells.
In an example embodiment, the memory management circuit 502 may record a mapping relationship between logical units and physical units (also referred to as a logical-to-physical address mapping relationship) in at least one logical-to-physical address mapping table. When the host system 11 is going to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform data access operations with respect to the memory storage device 10 according to the logical-to-physical address mapping table.
In an example embodiment, the memory management circuit 502 may send a read command sequence (also referred to as a first read command sequence) to the rewritable nonvolatile memory module 406. The first read command sequence can instruct the rewritable nonvolatile memory module 406 to read a certain physical unit (also referred to as a first physical unit) based on a certain electrical setting (also referred to as a first electrical setting) to obtain soft information (also referred to as first soft information). In addition, the memory management circuit 502 can send another read command sequence (also referred to as a second read command sequence) to the rewritable nonvolatile memory module 406. The second read command sequence can instruct the rewritable nonvolatile memory module 406 to read the first physical unit based on another electrical setting (also referred to as a second electrical setting) to obtain corresponding soft information (also referred to as second soft information). The first electrical setting is different from the second electrical setting.
In an example embodiment, in response to the first read command sequence, the rewritable non-volatile memory module 406 can read the first physical unit using a plurality of read voltage levels (also referred to as first read voltage levels) corresponding to the first electrical setting to obtain the first soft information. Similarly, in response to the second read command sequence, the rewritable non-volatile memory module 406 can use a plurality of read voltage levels (also referred to as second read voltage levels) corresponding to the second electrical setting to read the first physical unit to obtain the second soft information.
In an example embodiment, the current value of the read current (also referred to as the first read current) used by the rewritable non-volatile memory module 406 based on the first electrical setting is different from the current value of the read current (also referred to as the second read current) used by the rewritable non-volatile memory module 406 based on the second electrical setting. The first read voltage level is also different from the second read voltage level in response to a change in the read current (e.g., from the first read current to the second read current). Alternatively, from another perspective, the electrical difference between the first electrical setting and the second electrical setting may include a difference between a current value of the first read current and a current value of the second read current. In an example embodiment, the first read current may be specified by a first electrical setting (and/or the memory management circuitry 502), and/or the second read current may be specified by a second electrical setting (and/or the memory management circuitry 502).
In an example embodiment, the memory management circuit 502 may classify a plurality of memory cells in the first physical cell according to the first soft information and the second soft information. The error checking and correcting circuit 508 can decode the data read from the first physical unit according to the classification result of the memory cells. For example, the error checking and correcting circuit 508 can determine reliability information (also referred to as first reliability information) corresponding to a first memory cell according to the classification result of the memory cell (also referred to as the first memory cell) in the first physical cell. The memory management circuit 502 may send a read command sequence (also referred to as a third read command sequence) to instruct reading data from a first physical unit including the first memory cell. The error checking and correcting circuit 508 may decode the data read from the first memory cell according to the first reliability information.
In an exemplary embodiment, the first reliability information is dynamically determined according to the classification result of the first memory cell. The first reliability information is different from preset reliability information corresponding to the first storage unit. For example, the predetermined reliability information corresponding to the first storage unit may be determined and/or provided by a vendor of the rewritable nonvolatile memory module 406 (e.g., recorded in a management table provided by the vendor and stored in the rewritable nonvolatile memory module 406), and the predetermined reliability information may not be obtained through dynamic operations. In an exemplary embodiment, the first reliability information may be obtained via a real-time calculation and/or may not be recorded in a management table provided by a supplier. In an example embodiment, decoding the data read from the first memory cell according to the first reliability information may improve decoding efficiency (e.g., decoding success rate) of the data read from the first memory cell, relative to decoding the data read from the first memory cell using the preset reliability information.
In an exemplary embodiment, the classification result of the first memory cell may reflect the sensitivity of the first memory cell to changes in the electrical parameter (or electrical setting). For example, the memory management circuit 502 may classify the first memory cell into a first class of memory cells or a second class of memory cells according to the first soft information and the second soft information. The sensitivity of the first type of memory cells to changes in the electrical parameter is different from the sensitivity of the second type of memory cells to changes in the electrical parameter. For example, the first type of memory cells may be more sensitive to changes in an electrical parameter than the second type of memory cells. Furthermore, the electrical parameter may be any parameter that is influenced by an electrical difference between the above-mentioned first electrical setting and the second electrical setting, such as a read current for reading the first memory cell.
In an example embodiment, the memory management circuit 502 may obtain the change of the threshold voltage of the first memory cell caused by the change of the electrical parameter (or the electrical setting) according to the first soft information and the second soft information. The change in threshold voltage reflects the sensitivity of the first memory cell to a change in an electrical parameter (or electrical setting). The memory management circuit 502 can determine the first reliability information according to the variation of the threshold voltage.
Fig. 7 is a diagram illustrating reading of a first physical cell based on a first electrical setting and a second electrical setting according to an example embodiment of the invention. Referring to fig. 7, it is assumed that the first electrical setting corresponds to a first read current, the second electrical setting corresponds to a second read current, and a difference between the first read current and the second read current is Δ I. In other words, Δ I may reflect a change in an electrical parameter (e.g., read current) between the first electrical setting and the second electrical setting.
When the first physical cell is read based on the first electrical setting, the distribution of the threshold voltages of the plurality of memory cells in the first physical cell may be as shown in distribution 71. According to the first read command sequence, the rewritable nonvolatile memory module 406 determines a plurality of read voltage levels 701-705 based on a first electrical setting. For example, the read voltage levels 701-705 can be determined according to a first read current corresponding to a first electrical setting. The rewritable non-volatile memory module 406 can sequentially use the read voltage levels 701-705 to read the memory cells in the first physical unit to obtain the first soft information.
Based on the read results (i.e., the first soft information) of the read voltage levels 701-705, the threshold voltages of the memory cells in the first physical cell can be grouped to belong to one of the voltage ranges A1-F1. For example, if the first soft information reflects that the threshold voltage of the first memory cell is below the read voltage level 704, the threshold voltage of the first memory cell may be grouped as belonging to voltage range A1. If the first soft information reflects that the threshold voltage of the first memory cell is between read voltage levels 704 and 702, the threshold voltage of the first memory cell may be grouped as belonging to voltage range B1. If the first soft information reflects that the threshold voltage of the first memory cell is between the read voltage levels 702 and 701, the threshold voltage of the first memory cell may be grouped as belonging to the voltage range C1. If the first soft information reflects that the threshold voltage of the first memory cell is between the read voltage levels 701 and 703, the threshold voltage of the first memory cell may be grouped as belonging to the voltage range D1. If the first soft information reflects that the threshold voltage of the first memory cell is between the read voltage levels 703 and 705, the threshold voltage of the first memory cell can be grouped as belonging to the voltage range E1. Furthermore, if the first soft information reflects that the threshold voltage of the first memory cell is above the read voltage level 705, the threshold voltage of the first memory cell may be grouped as belonging to voltage range F1.
On the other hand, when switching to reading the first physical cell based on the second electrical setting, the distribution of the threshold voltages of the plurality of memory cells in the first physical cell may change from distribution 71 to distribution 72 in response to a change (e.g., Δ I) in the electrical parameter between the first electrical setting and the second electrical setting. According to the second read command sequence, the rewritable nonvolatile memory module 406 can determine a plurality of read voltage levels 706-710 based on the second electrical setting. For example, the read voltage levels 706-710 can be determined according to a second read current corresponding to a second electrical setting. The rewritable non-volatile memory module 406 can sequentially use the read voltage levels 706-710 to read the memory cells in the first physical unit to obtain the second soft information. In addition, the threshold voltages of the first memory cells can be grouped to belong to one of the voltage ranges A2-F2 according to the read results (i.e., the second soft information) of the read voltage levels 706-710. For example, if the second soft information reflects that the threshold voltage of the first memory cell is between read voltage levels 706 and 708, the threshold voltage of the first memory cell may be grouped as belonging to voltage range D2, and so on.
It is noted that in the exemplary embodiment of FIG. 7, the read voltage levels 701-705 correspond to the read voltage levels 706-710 one-to-one. For example, in response to Δ I, the read voltage level 701 is automatically switched to the read voltage level 706, the read voltage level 702 is automatically switched to the read voltage level 707, and so on. The voltage ranges a1 to F1 correspond to the voltage ranges a2 to F2, respectively.
Ideally, the threshold voltage of a memory cell changes due to a change in an electrical parameter (e.g., Δ I), but the change should not change the relative position between the threshold voltage of a memory cell and the entire threshold voltage distribution (or a plurality of voltage ranges divided by a plurality of read voltage levels). For example, assuming that the threshold voltage of a memory cell in distribution 71 falls within voltage range B1, the threshold voltage of the memory cell in distribution 72 should fall within voltage range B2 after the read current is changed.
However, in practice, the sensitivity of different memory cells to variations in electrical parameters may vary due to process variations among the different memory cells, and so on. For example, if the threshold voltage of a memory cell in distribution 71 falls within voltage range B1, the threshold voltage of the memory cell may fall within voltage range a2 in distribution 72 after the read current is changed. Alternatively, if the threshold voltage of another memory cell in distribution 71 falls within voltage range B1, the threshold voltage of the memory cell may become in distribution 72 falling within voltage range F2 after the read current is changed.
In an exemplary embodiment, a greater change in the relative voltage locations of a memory cell in distributions 71 and 72 (e.g., from voltage range A1 to F2) indicates that the memory cell is more sensitive to a change in an electrical parameter. Conversely, if the relative voltage position of a memory cell in the distributions 71 and 72 changes less (e.g., from the voltage range a1 to B2) or even does not change (e.g., from the voltage range a1 to a2), it indicates that the memory cell is less sensitive to the change of the electrical parameter.
In an exemplary embodiment, the memory management circuit 502 can obtain a voltage change Δ V corresponding to the change of the relative voltage position of the first memory cell in the distributions 71 and 72. Then, the memory management circuit 502 can classify the first memory cell according to the voltage variation Δ V. For example, assuming that the relative voltage position of the first memory cell in the distributions 71 and 72 changes from the voltage range A1 to B2, the voltage change Δ V can be determined as the voltage difference corresponding to 1 voltage range. Alternatively, assuming that the relative voltage position of the first memory cell in the distributions 71 and 72 changes from the voltage range A1 to C2, the voltage change Δ V can be determined as the voltage difference corresponding to 2 voltage ranges. Alternatively, assuming that the relative voltage position of the first memory cell in the distributions 71 and 72 changes from the voltage range A1 to D2, the voltage change Δ V can be determined as the voltage difference corresponding to 3 voltage ranges. Alternatively, assuming that the relative voltage position of the first memory cell in the distributions 71 and 72 changes from the voltage range A1 to E2, the voltage change Δ V can be determined as the voltage difference corresponding to 4 voltage ranges. Alternatively, assuming that the relative voltage position of the first memory cell in the distributions 71 and 72 changes from the voltage range A1 to F2, the voltage change Δ V can be determined as the voltage difference corresponding to 5 voltage ranges. By analogy, the voltage ranges B1 to D2 (or E1 to C2) may be the voltage differences corresponding to 2 voltage ranges, and so on.
In an example embodiment, the memory management circuit 502 may compare the voltage variation Δ V with at least one threshold and classify the first memory cell according to the comparison result. For example, if the voltage variation Δ V is greater than a threshold, the memory management circuit 502 may classify the first memory cell as a first type of memory cell. In addition, if the voltage variation Δ V is not greater than the threshold value, the memory management circuit 502 may classify the first memory cell into a second type of memory cell.
In an example embodiment, if the voltage change Δ V is greater than a threshold, the memory management circuit 502 may determine the first memory cell as a memory cell that is more sensitive to the change in the electrical parameter. Alternatively, if the voltage change Δ V is not greater than the threshold value, the memory management circuit 502 may determine the first memory cell as a memory cell that is less sensitive to the change in the electrical parameter. Viewed from another perspective, in an exemplary embodiment, if the first memory cell is classified as a first type of memory cell, it can be considered that the first memory cell has a sensitivity to a change in the electrical parameter greater than a predetermined sensitivity. Alternatively, if the first memory cell is classified as the second type memory cell, it can be considered that the first memory cell has a sensitivity to a change in the electrical parameter that is not greater than the predetermined sensitivity.
It is noted that in the exemplary embodiment of FIG. 7, the voltage ranges are divided into 6 voltage ranges by 5 read voltage levels, so as to approximately identify the voltage value of the current threshold voltage of the first memory cell (e.g., within a specific voltage interval) through the voltage ranges. In another example embodiment, more or fewer read voltage levels may be used to read the first memory cell to identify the current threshold voltage level of the first memory cell based on different resolutions.
Fig. 8 is a diagram illustrating table information according to an exemplary embodiment of the invention. Referring to fig. 7 and 8, it is assumed that after reading memory Cell (1) based on the first electrical setting and the second electrical setting, the first soft information and the second soft information reflect a voltage change Δ V1 corresponding to a change in the relative voltage position of memory Cell (1) in distributions 71 and 72, corresponding to a current change Δ I. In response to Δ V1 being greater than threshold VT, Cell (1) may be classified as a first type of Cell. According to the classification result of the memory Cell (1), reliability information corresponding to the first type of memory Cell can be determined and used for decoding data subsequently read from the memory Cell (1).
Further, it is assumed that after reading memory Cell (2) based on the first electrical setting and the second electrical setting, the first soft information and the second soft information reflect a voltage change Δ V2 corresponding to a change in the relative voltage position of memory Cell (2) in distributions 71 and 72 corresponding to current change Δ I. In response to Δ V2 being less than threshold VT, Cell (2) may be classified as a second type of Cell. Depending on the classification result of the memory Cell (2), reliability information corresponding to the second type of memory Cell may be determined and used for decoding data subsequently read from the memory Cell (2).
The above-mentioned information and other useful information can be described in the table information 81. The table information 81 can be loaded into the buffer memory 510 of fig. 5 for updating and maintenance. When performing a decoding operation, the error checking and correcting circuit 508 of FIG. 5 can determine the reliability information corresponding to the first memory cell according to the table information 81 and decode the data read from the first memory cell according to the reliability information. In an exemplary embodiment, the reliability information corresponding to the first memory cell may also be determined directly according to the voltage ranges of the threshold voltages of the first memory cell in the distributions 71 and 72, respectively.
Fig. 9 is a diagram illustrating table information according to an exemplary embodiment of the invention. Referring to fig. 7 and 9, in the present exemplary embodiment, the table information 91 may record classification results and corresponding reliability information corresponding to various pairing manners between an original group (i.e., an original voltage range) and a new group (i.e., a new voltage range). In addition, in the present exemplary embodiment, the reliability information is exemplified by a log similarity ratio (LLR) in the LDPC decoding algorithm. In another exemplary embodiment, the reliability information may also be decoding parameters used in other types of decoding algorithms (e.g., BCH), and the invention is not limited thereto.
In the example embodiment of FIG. 7, assuming that the threshold voltage of the first memory cell in distributions 71 and 72 falls within voltage ranges B1 and C2, respectively, the classification result of the first memory cell can be R9 and the first reliability information corresponding to the first memory cell can be L9 (or further calculated based on L9) by looking up the table information 91. Alternatively, in another exemplary embodiment of FIG. 7, assuming that the threshold voltage of the first memory cell in distributions 71 and 72 falls within voltage ranges A1 and E2, respectively, the classification result of the first memory cell can be R5 and the first reliability information corresponding to the first memory cell can be L5 (or obtained by further calculation based on L5) by looking up the table information 91, and so on.
In an example embodiment, the error checking and correction circuitry 508 may decode data read from the first physical unit based on the first electrical setting. If the decoding is successful, the successfully decoded data may be output (e.g., transmitted to the host system 11 of FIG. 1). If the decoding fails, the memory management circuitry 502 may instead read data from the first physical unit based on the second electrical setting. The data read based on the second electrical setting may again be decoded by the error checking and correction circuitry 508.
In an exemplary embodiment, the first electrical setting is a predetermined or normal electrical setting, and the second electrical setting is a special or customized electrical setting. The predetermined or normal electrical setting refers to, for example, an electrical setting (e.g., a predetermined read current) that is not specifically adjusted. In an example embodiment, the memory management circuit 502 may read data from the first physical unit based on a preset or normal first electrical setting. If the data read from the first physical cell based on the preset or normal first electrical setting cannot be successfully decoded, the memory management circuit 502 may instead read the first physical cell again based on the special or customized second electrical setting. However, in another exemplary embodiment, the first electrical setting and the second electrical setting may both refer to specific or customized electrical settings, and the invention is not limited thereto.
In an example embodiment, the error checking and correcting circuit 508 may decode the read data based on a hard bit decoding mode or a soft bit decoding mode. In the hard bit decode mode, the memory management circuit 502 may first read data (e.g., hard bits) from the first physical cells based on the first electrical setting and decode the read data by the error checking and correction circuit 508. If the decoding fails, the memory management circuitry 502 may instead read data from the first physical cell based on the second electrical setting, and the error checking and correction circuitry 508 may decode the read data again. If the number of re-reads for the first physical unit in the hard bit decoding mode exceeds a threshold, the error checking and correcting circuit 508 can leave the hard bit decoding mode and enter the soft bit decoding mode. In the soft bit decoding mode, the memory management circuitry 502 may also read data (e.g., soft bits) from the first physical unit and the error checking and correction circuitry 508 may decode this data. It is noted that data (e.g., soft bits) read in soft bit decoding mode may carry more information available for auxiliary decoding than data (e.g., hard bits) read in hard bit decoding mode. Thus, for data with more erroneous bits, the decoding success rate for the soft bit decoding mode may be higher than the decoding success rate for the hard bit decoding mode. However, decoding in the soft bit decoding mode tends to take more time than decoding in the hard bit decoding mode.
In an example embodiment, the memory management circuit 502 may continuously read the first physical unit using the preset electrical settings and decode the read data by the error checking and correcting circuit 508 based on the hard bit decoding mode. If the number of re-reads for the first physical unit in the hard bit decoding mode exceeds a threshold, the memory management circuit 502 may read the first physical unit based on the first electrical setting and the second electrical setting in sequence and perform the aforementioned operation of obtaining the first reliability information before the error checking and correcting circuit 508 enters the soft bit decoding mode. Then, the error checking and correcting circuit 508 can decode the data read from the first physical unit according to the first reliability information, thereby effectively improving the decoding efficiency.
FIG. 10 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention. Referring to fig. 10, in step S1001, a first physical unit of the plurality of physical units is read based on a first electrical setting to obtain first soft information. In step S1002, the first physical unit is read to obtain second soft information based on a second electrical setting, wherein the first electrical setting is different from the second electrical setting. In step S1003, a plurality of storage units in the first entity unit are sorted according to the first soft information and the second soft information. In step S1004, the data read from the first physical unit is decoded according to the classification result of the plurality of memory units.
However, the steps in fig. 10 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 10 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 10 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.
In summary, after the first entity unit is respectively read through different electrical settings to obtain the first soft information and the second soft information, the memory cells in the first entity unit can be classified according to the first soft information and the second soft information. Then, the data read from the first entity unit may be decoded according to the classification result. Thereby, even if different memory cells have different sensitivities to variations in electrical parameters, appropriate reliability information can be dynamically determined and used in decoding operations, thereby improving the overall operational performance of the memory storage device.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (24)

1. A memory control method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of entity units, the memory control method comprising:
reading a first physical cell of the plurality of physical cells based on a first electrical setting to obtain first soft information;
reading the first physical cell based on a second electrical setting to obtain second soft information, wherein the first electrical setting is different from the second electrical setting;
classifying a plurality of storage units in the first entity unit according to the first soft information and the second soft information; and
decoding data read from the first physical unit according to the classification result of the plurality of memory cells.
2. The memory control method of claim 1, wherein reading the first physical cell of the plurality of physical cells to obtain the first soft information based on the first electrical setting comprises:
reading the first physical cell using a plurality of first read voltage levels corresponding to the first electrical setting to obtain the first soft information, and
the step of reading the first physical unit to obtain the second soft information based on the second electrical setting comprises:
reading the first physical cell using a plurality of second read voltage levels corresponding to the second electrical setting to obtain the second soft information.
3. The memory control method of claim 1, wherein the step of sorting the plurality of memory cells in the first physical unit according to the first soft information and the second soft information comprises:
classifying a first memory cell of the plurality of memory cells as a first class of memory cells or a second class of memory cells based on the first soft information and the second soft information,
wherein the first type of memory cells has a sensitivity to changes in an electrical parameter that is different from a sensitivity of the second type of memory cells to changes in the electrical parameter.
4. The memory control method of claim 1, wherein the step of sorting the plurality of memory cells in the first physical unit according to the first soft information and the second soft information comprises:
obtaining a relative voltage position of a first memory cell in the plurality of memory cells in a plurality of critical voltage distributions according to the first soft information and the second soft information; and
classifying the first memory cell according to the relative voltage location of the first memory cell in the plurality of threshold voltage distributions.
5. The memory control method of claim 1, wherein the step of decoding the data read from the first physical unit according to the classification result of the plurality of memory units comprises:
determining first reliability information corresponding to a first storage unit in the plurality of storage units according to a classification result of the first storage unit; and
decoding data read from the first memory cell according to the first reliability information.
6. The memory control method according to claim 1, wherein a current value of a first read current used based on the first electrical setting is different from a current value of a second read current used based on the second electrical setting.
7. The memory control method of claim 1, wherein the classification result of the plurality of memory cells reflects at least a sensitivity of a first memory cell of the plurality of memory cells to a change in an electrical parameter.
8. The memory control method of claim 7, wherein the change in the electrical parameter comprises a change in a read current.
9. A memory storage device, comprising:
a connection interface unit for connecting to a host system;
a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of entity units; and
a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuit unit is configured to send a first read command sequence instructing to read a first physical unit of the plurality of physical units based on a first electrical setting to obtain first soft information,
the memory control circuit unit is further configured to send a second read command sequence instructing to read the first physical unit based on a second electrical setting to obtain second soft information, wherein the first electrical setting is different from the second electrical setting,
the memory control circuit unit is further configured to classify a plurality of memory cells in the first physical unit according to the first soft information and the second soft information, and
the memory control circuit unit is further configured to decode data read from the first physical unit according to the classification result of the plurality of memory cells.
10. The memory storage device of claim 9, wherein the first read instruction sequence indicates to read the first physical cell using a plurality of first read voltage levels corresponding to the first electrical setting to obtain the first soft information, and
the second sequence of read instructions instructs reading of the first physical unit using a plurality of second read voltage levels corresponding to the second electrical setting to obtain the second soft information.
11. The memory storage device of claim 9, wherein the operation of the memory control circuitry unit to sort the plurality of memory cells in the first physical unit according to the first soft information and the second soft information comprises:
classifying a first memory cell of the plurality of memory cells as a first class of memory cells or a second class of memory cells based on the first soft information and the second soft information,
wherein the first type of memory cells is sensitive to changes in an electrical parameter differently than the second type of memory cells.
12. The memory storage device of claim 9, wherein the operation of the memory control circuitry unit to sort the plurality of memory cells in the first physical unit according to the first soft information and the second soft information comprises:
obtaining a relative voltage position of a first memory cell in the plurality of memory cells in a plurality of critical voltage distributions according to the first soft information and the second soft information; and
classifying the first memory cell according to the relative voltage location of the first memory cell in the plurality of threshold voltage distributions.
13. The memory storage device of claim 9, wherein the operation of the memory control circuitry unit to decode the data read from the first physical unit according to the classification result of the plurality of storage units comprises:
determining first reliability information corresponding to a first storage unit in the plurality of storage units according to a classification result of the first storage unit; and
decoding data read from the first memory cell according to the first reliability information.
14. The memory storage device of claim 9, wherein a current value of a first read current used based on the first electrical setting is different from a current value of a second read current used based on the second electrical setting.
15. The memory storage device of claim 9, wherein the classification result of the plurality of storage cells reflects at least a sensitivity of a first storage cell of the plurality of storage cells to a change in an electrical parameter.
16. The memory storage device of claim 15, wherein the change in the electrical parameter comprises a change in a read current.
17. A memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of entity units, and the memory control circuit unit includes:
a host interface for connecting to a host system;
a memory interface for connecting to the rewritable nonvolatile memory module;
an error checking and correcting circuit; and
memory management circuitry connected to the host interface, the memory interface, and the error checking and correcting circuitry,
wherein the memory management circuit is configured to send a first read command sequence instructing to read a first physical unit of the plurality of physical units based on a first electrical setting to obtain first soft information,
the memory management circuit is also to send a second sequence of read instructions that direct reading of the first physical unit for second soft information based on a second electrical setting, wherein the first electrical setting is different from the second electrical setting,
the memory management circuit is further configured to classify a plurality of memory cells in the first physical cell according to the first soft information and the second soft information, and
the error checking and correcting circuit is used for decoding the data read from the first entity unit according to the classification result of the plurality of storage units.
18. The memory control circuit cell of claim 17, wherein the first read instruction sequence indicates to read the first physical cell using a plurality of first read voltage levels corresponding to the first electrical setting to obtain the first soft information, and
the second sequence of read instructions instructs reading of the first physical unit using a plurality of second read voltage levels corresponding to the second electrical setting to obtain the second soft information.
19. The memory control circuitry unit of claim 17, wherein the operation of the memory management circuitry to sort the plurality of memory cells in the first physical unit according to the first soft information and the second soft information comprises:
classifying a first memory cell of the plurality of memory cells as a first type of memory cell or a second type of memory cell according to the first soft information and the second soft information,
wherein the first type of memory cells is sensitive to changes in an electrical parameter differently than the second type of memory cells.
20. The memory control circuitry unit of claim 17, wherein the operation of the memory management circuitry to sort the plurality of memory cells in the first physical unit according to the first soft information and the second soft information comprises:
obtaining a relative voltage position of a first memory cell in the plurality of memory cells in a plurality of critical voltage distributions according to the first soft information and the second soft information; and
classifying the first memory cell according to the relative voltage location of the first memory cell in the plurality of threshold voltage distributions.
21. The memory control circuitry unit of claim 17, wherein the operation of the error checking and correction circuitry to decode the data read from the first physical unit according to the classification result of the plurality of memory cells comprises:
determining first reliability information corresponding to a first storage unit in the plurality of storage units according to a classification result of the first storage unit; and
decoding data read from the first memory cell according to the first reliability information.
22. The memory control circuit unit according to claim 17, wherein a current value of a first read current used based on the first electrical setting is different from a current value of a second read current used based on the second electrical setting.
23. The memory control circuit unit of claim 17, wherein the classification result of the plurality of memory cells reflects at least a sensitivity of a first memory cell of the plurality of memory cells to a change in an electrical parameter.
24. The memory control circuit cell of claim 23, wherein the change in the electrical parameter comprises a change in a read current.
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110066902A1 (en) * 2009-01-30 2011-03-17 Sandisk Il Ltd. System and method of reading data using a reliability measure
US20120072805A1 (en) * 2010-09-17 2012-03-22 Phison Electronics Corp. Memory storage device, memory controller thereof, and method thereof for generating log likelihood ratio
CN102884585A (en) * 2010-05-12 2013-01-16 美光科技公司 Determining and using soft data in memory devices and systems
US20130094288A1 (en) * 2011-10-18 2013-04-18 Seagate Technology Llc Categorizing bit errors of solid-state, non-volatile memory
CN103208309A (en) * 2006-05-12 2013-07-17 苹果公司 Distortion estimation and cancellation in memory devices
US20140059398A1 (en) * 2012-08-27 2014-02-27 Jeffrey C. Cunningham Adaptive error correction for non-volatile memories
US20150095741A1 (en) * 2013-09-30 2015-04-02 Phison Electronics Corp. Decoding method, memory storage device and memory controlling circuit unit
US20170162268A1 (en) * 2013-11-01 2017-06-08 Seagate Technology Llc Reduction or Elimination of a Latency Penalty Associated With Adjusting Read Thresholds for Non-Volatile Memory

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103208309A (en) * 2006-05-12 2013-07-17 苹果公司 Distortion estimation and cancellation in memory devices
US20110066902A1 (en) * 2009-01-30 2011-03-17 Sandisk Il Ltd. System and method of reading data using a reliability measure
CN102884585A (en) * 2010-05-12 2013-01-16 美光科技公司 Determining and using soft data in memory devices and systems
US20120072805A1 (en) * 2010-09-17 2012-03-22 Phison Electronics Corp. Memory storage device, memory controller thereof, and method thereof for generating log likelihood ratio
US20130094288A1 (en) * 2011-10-18 2013-04-18 Seagate Technology Llc Categorizing bit errors of solid-state, non-volatile memory
US20140059398A1 (en) * 2012-08-27 2014-02-27 Jeffrey C. Cunningham Adaptive error correction for non-volatile memories
US20150095741A1 (en) * 2013-09-30 2015-04-02 Phison Electronics Corp. Decoding method, memory storage device and memory controlling circuit unit
US20170162268A1 (en) * 2013-11-01 2017-06-08 Seagate Technology Llc Reduction or Elimination of a Latency Penalty Associated With Adjusting Read Thresholds for Non-Volatile Memory

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