CN112039504B - PWM signal duty cycle regulating circuit - Google Patents
PWM signal duty cycle regulating circuit Download PDFInfo
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- CN112039504B CN112039504B CN202010976083.3A CN202010976083A CN112039504B CN 112039504 B CN112039504 B CN 112039504B CN 202010976083 A CN202010976083 A CN 202010976083A CN 112039504 B CN112039504 B CN 112039504B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
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- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
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Abstract
The invention relates to the field of control circuits, and provides a PWM signal duty cycle adjusting circuit, which comprises: a mirrored current source; a logic processing unit; the pulse time conversion unit is connected with the first current output end of the mirror current source, and the detection end of the pulse time conversion unit is connected with the first output end of the logic processing unit; the input end of the sampling and holding unit is connected with the output end of the pulse time conversion unit, and the sampling signal input end of the sampling and protecting unit is connected with the second output end of the logic processing unit; the pulse time adjusting unit is connected with the sampling and holding unit; the output synthesis unit is connected with the pulse time adjusting unit; and the pulse period conversion unit is connected among the logic processing unit, the mirror current source and the output synthesis unit.
Description
Technical Field
The invention relates to the field of control circuits, in particular to a PWM signal duty cycle adjusting circuit.
Background
In LED driving, there are cases where it is necessary to generate a double-speed duty ratio of an input PWM dimming signal or where a switching power supply is necessary to generate a 1/2 or other duty ratio of a PWM signal with an indefinite duty ratio, but in the conventional market, there are problems that a processing technique for scaling and outputting a duty ratio of an input PWM wave at an arbitrary ratio is not practical enough and is not easy to realize.
Disclosure of Invention
The invention aims to provide a PWM signal duty cycle adjusting circuit.
The invention aims to realize arbitrary scaling output of the duty ratio of an input PWM wave.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
A PWM signal duty cycle adjustment circuit, comprising: a mirror current source for providing a constant current; the logic processing unit is used for accessing an external PWM signal; the pulse time conversion unit is connected with the first current output end of the mirror current source, and the detection end of the pulse time conversion unit is connected with the first output end of the logic processing unit; the input end of the sampling and holding unit is connected with the output end of the pulse time conversion unit, and the sampling signal input end of the sampling and protecting unit is connected with the second output end of the logic processing unit; the pulse time adjusting unit is connected with the sampling and holding unit; the output synthesis unit is connected with the pulse time adjusting unit; and the pulse period conversion unit is connected among the logic processing unit, the mirror current source and the output synthesis unit.
As a further improvement, the mirror current source performs linear detection on the on time of the input PWM wave, the logic processing unit processes the input PWM wave, the sample-hold unit holds the peak voltage output by the pulse time conversion unit, the pulse time adjustment unit selects a target voltage value generated by the duty ratio, and the output synthesis unit outputs the target PWM wave according to the target voltage value.
As a further improvement, the sample-and-hold unit includes: a first operational amplifier and a sample-and-hold circuit; the first input end of the first operational amplifier is connected with the pulse time conversion unit, the second input end of the first operational amplifier is connected with the control end of the pulse time adjustment unit, the output end of the first operational amplifier is connected with the input end of the sample hold circuit, the control end of the sample hold circuit is connected with the output end of the logic processing unit, and the output end of the sample hold circuit is connected with the input end of the pulse time adjustment unit.
As a further improvement, the pulse time adjustment unit includes: the device comprises a resistor voltage division string, a data selector connected with the resistor voltage division string and a selection module connected with the data selector; the resistor voltage division string is respectively connected with the sampling hold circuit and the second input end of the first operational amplifier; the data selector is connected to the output synthesizing unit.
As a further improvement, the output synthesizing unit includes a second operational amplifier, a first input terminal of the second operational amplifier is connected to the output terminal of the data selector, and a second input terminal of the second operational amplifier is connected to the pulse period converting unit.
As a further improvement, a first input terminal of the pulse period conversion unit is connected to the reset signal terminal of the logic processing unit, and a second input terminal of the pulse period conversion unit is connected to the second output terminal of the mirror current source.
As a further improvement, the mirror current source includes: the MOS transistor comprises a first MOS transistor, a second MOS transistor and a third MOS transistor, wherein the source electrode of the first MOS transistor, the source electrode of the second MOS transistor and the source electrode of the third MOS transistor are connected to the VDD end, the grid electrode of the first MOS transistor is connected to the grid electrode of the second MOS transistor, the grid electrode of the third MOS transistor is connected to a switch node, the drain electrode of the first MOS transistor is connected to the switch node, and the switch node is grounded.
As a further improvement, the mirror current source further comprises an ammeter, one end of the ammeter is grounded, and the other end of the ammeter is connected to the switch node.
As a further improvement, the first MOS tube, the second MOS tube and the third MOS tube are PMOS tubes.
The beneficial effects of the invention are as follows: the full-analog method is adopted to realize the scaling output of the duty ratio of the input PWM wave in any proportion, the full-analog method has practicability for specific application of low-speed PWM, the circuit structure is simple and clear, and the regulating circuit is easy to realize.
Drawings
Fig. 1 is a circuit diagram of PWM signal duty cycle adjustment according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a sample-and-hold circuit according to an embodiment of the present invention.
Fig. 3 is a signal timing diagram of each device in the circuit diagram shown in fig. 1.
In the figure: 1. mirror current source 2, logic processing unit 3, pulse time conversion unit
4. Sample-and-hold unit 41, first operational amplifier 42, sample-and-hold circuit
5. Pulse time adjusting unit 51, resistor voltage dividing string 52, data selector
53. A selection module 6, an output synthesis unit 7, a pulse period conversion unit
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, based on the embodiments of the invention, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the invention. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, based on the embodiments of the invention, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the invention.
In the description of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Referring to fig. 1 to 3, a PWM signal duty cycle adjusting circuit includes: a mirror current source 1, the mirror current source 1 being configured to provide a constant current; the logic processing unit 2 is used for accessing an external PWM signal; the pulse time conversion unit 3 is connected with the first current output end of the mirror current source 1, and the detection end of the pulse time conversion unit 3 is connected with the first output end of the logic processing unit 2; the input end of the sampling and holding unit is connected with the output end of the pulse time conversion unit 3, and the sampling signal input end of the sampling and protecting unit is connected with the second output end of the logic processing unit 2; a pulse time adjustment unit 5, wherein the pulse time adjustment unit 5 is connected to the sample hold unit 4; an output synthesis unit 6, the output synthesis unit 6 being connected to the pulse time adjustment unit 5; and the pulse period conversion unit 7 is connected among the logic processing unit 2, the mirror current source 1 and the output synthesis unit 6. The full-analog method is adopted to realize the scaling output of the duty ratio of the input PWM wave in any proportion, the full-analog method has practicability for specific application of low-speed PWM, the circuit structure is simple and clear, and the regulating circuit is easy to realize.
Referring to fig. 1, the mirror current source 1 performs linear detection on the on-time of the input PWM wave, the logic processing unit 2 processes the input PWM wave, the sample-and-hold unit 4 holds the peak voltage output from the pulse time conversion unit 3, the pulse time adjustment unit 5 selects a target voltage value generated by the duty ratio, and the output synthesis unit 6 outputs the target PWM wave according to the target voltage value.
Referring to fig. 1, a first input terminal of the pulse time conversion unit 3 is connected to a first output terminal of the mirror current source 1, and a second input terminal of the pulse time conversion unit 3 is connected to an output terminal of the logic processing unit 2.
Referring to fig. 1, the sample-and-hold unit 4 includes: a first operational amplifier 41 and a sample-and-hold circuit 42; the first input end of the first operational amplifier 41 is connected to the pulse time conversion unit 3, the second input end of the first operational amplifier 41 is connected to the control end of the pulse time adjustment unit 5, the output end of the first operational amplifier 41 is connected to the input end of the sample and hold circuit 42, the control end of the sample and hold circuit 42 is connected to the output end of the logic processing unit 2, and the output end of the sample and hold circuit 42 is connected to the input end of the pulse time adjustment unit 5.
Referring to fig. 1, the pulse time adjusting unit 5 includes: a resistor voltage division string 51, a data selector 52 connected to the resistor voltage division string 51, and a selection module 53 connected to the data selector 52; the resistor voltage division string 51 is connected to the sample-and-hold circuit 42 and the second input terminal of the first operational amplifier 41, respectively; the data selector 52 is connected to the output synthesizing unit 6.
Referring to fig. 1, the output synthesizing unit 6 includes a second operational amplifier having a first input terminal connected to the output terminal of the data selector 52 and a second input terminal connected to the pulse period converting unit 7.
Referring to fig. 1, a first input terminal of the pulse period conversion unit 7 is connected to a reset signal terminal of the logic processing unit 2, and a second input terminal of the pulse period conversion unit 7 is connected to a second output terminal of the mirror current source 1.
Referring to fig. 1, the mirror current source 1 includes: the MOS transistor comprises a first MOS transistor Q1, a second MOS transistor Q2 and a third MOS transistor Q3, wherein the source electrode of the first MOS transistor Q1, the source electrode of the second MOS transistor Q2 and the source electrode of the third MOS transistor Q3 are connected to the VDD end, the grid electrode of the first MOS transistor Q1 is connected to the grid electrode of the second MOS transistor Q2, the grid electrode of the third MOS transistor Q3 is connected to a switch node, the drain electrode of the first MOS transistor Q1 is connected to the switch node, and the switch node is grounded. The switch node is located between the grid electrode of the first MOS tube Q1 and the grid electrode of the second MOS tube Q2.
Referring to fig. 1, the mirror current source 1 further includes an ammeter, one end of the ammeter is grounded, and the other end of the ammeter is connected to the switch node. The ammeter is used for measuring the current of the connection point of the drain electrode of the first MOS tube Q1 and the switch node.
Referring to fig. 1, the first MOS transistor Q1, the second MOS transistor Q2, and the third MOS transistor Q3 are PMOS transistors.
The working principle of the PWM signal duty ratio regulating circuit provided by the invention is as follows: the on-time of the input PWM is linearly detected by charging a capacitor by using the mirror current source 1, the voltage value of Vramp1 represents the on-time of the current PWM wave in real time, the peak voltage of Vramp1 in the current period is stored by using the first operational amplifier 41 and the sample hold circuit 42, the proportion of the feedback resistor string of the first operational amplifier 41 and the selector are utilized to select a desired Vfb value with any proportion, namely Vref, which represents the voltage value generated by any duty ratio, and the voltage value is compared with Vramp2 in the next period by using the second operational amplifier, so that the target PWM wave, namely PWM_out is output.
The working principle, working procedure and the like of the present embodiment can refer to the corresponding contents of the foregoing embodiment.
The same or similar parts of the embodiments described above in this specification may be referred to each other, and each embodiment focuses on the difference from the other embodiments, but it is not limited that the differences cannot be replaced or overlapped with each other.
The above examples are only for illustrating the technical scheme of the present invention and are not limiting. It will be understood by those skilled in the art that any modifications and equivalents that do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.
Claims (7)
1. A PWM signal duty cycle adjustment circuit, comprising:
A mirror current source for providing a constant current;
the logic processing unit is used for accessing an external PWM signal;
The pulse time conversion unit is connected with the first current output end of the mirror current source, and the detection end of the pulse time conversion unit is connected with the first output end of the logic processing unit;
The input end of the sampling and holding unit is connected with the output end of the pulse time conversion unit, and the sampling signal input end of the sampling and holding unit is connected with the second output end of the logic processing unit;
The pulse time adjusting unit is connected with the sampling and holding unit;
the output synthesis unit is connected with the pulse time adjusting unit;
the pulse period conversion unit is connected among the logic processing unit, the mirror current source and the output synthesis unit;
The first input end of the pulse period conversion unit is connected with the reset signal end of the logic processing unit, the second input end of the pulse period conversion unit is connected with the second output end of the mirror current source, and the output end of the pulse period conversion unit is connected with the input end of the output synthesis unit;
The mirror current source is used for linearly detecting the on time of an input PWM wave, the logic processing unit is used for processing the input PWM wave, the sample hold unit is used for holding the peak voltage output by the pulse time conversion unit, the pulse time adjustment unit is used for selecting a target voltage value generated by the duty ratio, and the output synthesis unit is used for outputting the target PWM wave according to the target voltage value.
2. The PWM signal duty cycle adjustment circuit of claim 1, wherein the sample-and-hold unit comprises: a first operational amplifier and a sample-and-hold circuit; the first input end of the first operational amplifier is connected with the pulse time conversion unit, the second input end of the first operational amplifier is connected with the control end of the pulse time adjustment unit, the output end of the first operational amplifier is connected with the input end of the sample hold circuit, the control end of the sample hold circuit is connected with the output end of the logic processing unit, and the output end of the sample hold circuit is connected with the input end of the pulse time adjustment unit.
3. A PWM signal duty cycle adjustment circuit according to claim 2, wherein the pulse time adjustment unit comprises: the device comprises a resistor voltage division string, a data selector connected with the resistor voltage division string and a selection module connected with the data selector; the resistor voltage division string is respectively connected with the sampling hold circuit and the second input end of the first operational amplifier; the data selector is connected to the output synthesizing unit.
4. A PWM signal duty cycle adjusting circuit according to claim 3, wherein the output synthesizing unit comprises a second operational amplifier, a first input terminal of the second operational amplifier being connected to the output terminal of the data selector, and a second input terminal of the second operational amplifier being connected to the pulse period converting unit.
5. A PWM signal duty cycle adjustment circuit according to claim 1, wherein the mirrored current source comprises: the MOS transistor comprises a first MOS transistor, a second MOS transistor and a third MOS transistor, wherein the source electrode of the first MOS transistor, the source electrode of the second MOS transistor and the source electrode of the third MOS transistor are connected to the VDD end, the grid electrode of the first MOS transistor is connected to the grid electrode of the second MOS transistor, the grid electrode of the third MOS transistor is connected to a switch node, the drain electrode of the first MOS transistor is connected to the switch node, and the switch node is grounded.
6. The PWM signal duty cycle adjustment circuit of claim 5, wherein the mirrored current source further comprises an ammeter, one end of the ammeter being grounded, the other end of the ammeter being connected to the switching node.
7. The PWM signal duty cycle adjustment circuit of claim 5, wherein the first MOS transistor, the second MOS transistor, and the third MOS transistor are PMOS transistors.
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| CN202010976083.3A CN112039504B (en) | 2020-09-16 | 2020-09-16 | PWM signal duty cycle regulating circuit |
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| CN202010976083.3A CN112039504B (en) | 2020-09-16 | 2020-09-16 | PWM signal duty cycle regulating circuit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102185499A (en) * | 2011-04-26 | 2011-09-14 | 西安英洛华微电子有限公司 | PWM (pulse width modulation) output-driven clamping circuit with low power consumption |
| CN202425103U (en) * | 2011-11-22 | 2012-09-05 | 四川华体照明科技股份有限公司 | LED (light-emitting diode) street lamp regulation device based on DC-DC PWM (pulse-width modulation) light adjustment driving |
| CN103476180A (en) * | 2013-09-12 | 2013-12-25 | 杭州士兰微电子股份有限公司 | Transconductance amplifier and LED constant current drive circuit |
| CN212935870U (en) * | 2020-09-16 | 2021-04-09 | 英麦科（厦门）微电子科技有限公司 | PWM signal duty ratio regulating circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104883780B (en) * | 2015-05-19 | 2017-06-23 | 深圳创维－Rgb电子有限公司 | Multichannel dual mode digital controls LED drive circuit and LED |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102185499A (en) * | 2011-04-26 | 2011-09-14 | 西安英洛华微电子有限公司 | PWM (pulse width modulation) output-driven clamping circuit with low power consumption |
| CN202425103U (en) * | 2011-11-22 | 2012-09-05 | 四川华体照明科技股份有限公司 | LED (light-emitting diode) street lamp regulation device based on DC-DC PWM (pulse-width modulation) light adjustment driving |
| CN103476180A (en) * | 2013-09-12 | 2013-12-25 | 杭州士兰微电子股份有限公司 | Transconductance amplifier and LED constant current drive circuit |
| CN212935870U (en) * | 2020-09-16 | 2021-04-09 | 英麦科（厦门）微电子科技有限公司 | PWM signal duty ratio regulating circuit |
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Effective date of registration: 20220401 Address after: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Applicant after: Tuoer Microelectronics Co.,Ltd. Address before: Unit 410, 1702 Gangzhong Road, Xiamen area, China (Fujian) pilot Free Trade Zone, Xiamen City, Fujian Province Applicant before: INMICRO (XIAMEN) MICROELECTRONIC TECHNOLOGY CO.,LTD. |
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