CN212935870U - PWM signal duty ratio regulating circuit - Google Patents
PWM signal duty ratio regulating circuit Download PDFInfo
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- CN212935870U CN212935870U CN202022034059.6U CN202022034059U CN212935870U CN 212935870 U CN212935870 U CN 212935870U CN 202022034059 U CN202022034059 U CN 202022034059U CN 212935870 U CN212935870 U CN 212935870U
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Abstract
The utility model provides a PWM signal duty cycle regulating circuit, include: a mirror current source; a logic processing unit; the pulse time conversion unit is connected with a first current output end of the mirror current source, and a detection end of the pulse time conversion unit is connected with a first output end of the logic processing unit; the input end of the sampling and holding unit is connected with the output end of the pulse time conversion unit, and the sampling signal input end of the sampling protection unit is connected with the second output end of the logic processing unit; a pulse time adjusting unit connected to the sample-and-hold unit; an output synthesis unit connected to the pulse time adjustment unit; and the pulse period conversion unit is connected among the logic processing unit, the mirror current source and the output synthesis unit.
Description
Technical Field
The utility model relates to a control circuit field, more specifically the saying so relates to a PWM signal duty cycle regulating circuit.
Background
In LED driving, it is sometimes necessary to generate a double-speed duty ratio of an input PWM dimming signal, or to generate 1/2 or other proportional duty ratios of a PWM signal having an indefinite duty ratio by a switching power supply, but in the existing market, a processing technique of performing scaling output of an arbitrary ratio with respect to the duty ratio of an input PWM wave has a problem that it is not practical enough and easy to implement.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a PWM signal duty cycle regulating circuit.
The utility model discloses it carries out arbitrary scaling output to the duty cycle of input PWM ripples to solve.
Compared with the prior art, the utility model discloses technical scheme and beneficial effect as follows:
a PWM signal duty cycle adjustment circuit, comprising: a mirror current source for providing a constant current; the logic processing unit is used for accessing an external PWM signal; the pulse time conversion unit is connected with a first current output end of the mirror current source, and a detection end of the pulse time conversion unit is connected with a first output end of the logic processing unit; the input end of the sampling and holding unit is connected with the output end of the pulse time conversion unit, and the sampling signal input end of the sampling protection unit is connected with the second output end of the logic processing unit; a pulse time adjusting unit connected to the sample-and-hold unit; an output synthesis unit connected to the pulse time adjustment unit; the pulse period conversion unit is connected among the logic processing unit, the mirror current source and the output synthesis unit; the first input end of the pulse period conversion unit is connected to the reset signal end of the logic processing unit, and the second input end of the pulse period conversion unit is connected to the second output end of the mirror current source.
As a further improvement, the mirror current source linearly detects the on-time of an input PWM wave, the logic processing unit processes the input PWM wave, the sample and hold unit holds the peak voltage output by the pulse time conversion unit, the pulse time adjustment unit selects a target voltage value generated by a duty ratio, and the output synthesis unit outputs the target PWM wave according to the target voltage value.
As a further improvement, a first input terminal of the pulse time conversion unit is connected to a first output terminal of the mirror current source, and a second input terminal of the pulse time conversion unit is connected to an output terminal of the logic processing unit.
As a further improvement, the sample-and-hold unit includes: a first operational amplifier and a sample-and-hold circuit; the first input end of the first operational amplifier is connected to the pulse time conversion unit, the second input end of the first operational amplifier is connected to the control end of the pulse time adjustment unit, the output end of the first operational amplifier is connected to the input end of the sample-and-hold circuit, the control end of the sample-and-hold circuit is connected to the output end of the logic processing unit, and the output end of the sample-and-hold circuit is connected to the input end of the pulse time adjustment unit.
As a further improvement, the pulse time adjusting unit includes: the device comprises a resistance voltage division string, a data selector connected with the resistance voltage division string and a selection module connected with the data selector; the resistance voltage division string is respectively connected with the sampling hold circuit and the second input end of the first operational amplifier; the data selector is connected to the output combining unit.
As a further improvement, the output combining unit includes a second operational amplifier, a first input terminal of the second operational amplifier is connected to the output terminal of the data selector, and a second input terminal of the second operational amplifier is connected to the pulse period converting unit.
As a further improvement, the mirror current source includes: the switch comprises a first MOS tube, a second MOS tube and a third MOS tube, wherein the source electrode of the first MOS tube, the source electrode of the second MOS tube and the source electrode of the third MOS tube are connected to a VDD end, the grid electrode of the first MOS tube is connected to the grid electrode of the second MOS tube, the grid electrode of the third MOS tube is connected to a switch node, the drain electrode of the first MOS tube is connected to the switch node, and the switch node is grounded.
As a further improvement, the mirror current source further includes an ammeter, one end of the ammeter is grounded, and the other end of the ammeter is connected to the switch node.
As a further improvement, the first MOS transistor, the second MOS transistor and the third MOS transistor are PMOS transistors.
The utility model has the advantages that: the method adopts a full-simulation method to realize the scaling output of any proportion of the duty ratio of the input PWM wave, has practicability to the specific application of low-speed PWM, has simple and clear circuit structure, and is easy to realize.
Drawings
Fig. 1 is a circuit diagram for adjusting the duty ratio of a PWM signal according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a sample-and-hold circuit according to an embodiment of the present invention.
Fig. 3 is a signal timing diagram of each device in the circuit diagram shown in fig. 1.
In the figure: 1. mirror current source 2, logic processing unit 3, pulse time conversion unit 4, sample hold unit 41, first operational amplifier 42, sample hold circuit 5, pulse time adjustment unit 51, resistor voltage division string 52, data selector 53, selection module 6, output synthesis unit 7, pulse period conversion unit
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the drawings of the embodiments of the present invention are combined to clearly and completely describe the technical solutions of the embodiments of the present invention, and obviously, the described embodiments are some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
Referring to fig. 1 to 3, a PWM signal duty ratio adjusting circuit includes: a mirror current source 1, the mirror current source 1 being for providing a constant current; the logic processing unit 2 is used for accessing an external PWM signal; the pulse time conversion unit 3 is connected with the first current output end of the mirror current source 1, and the detection end of the pulse time conversion unit 3 is connected with the first output end of the logic processing unit 2; the input end of the sampling and holding unit 4 is connected to the output end of the pulse time conversion unit 3, and the sampling signal input end of the sampling protection unit is connected to the second output end of the logic processing unit 2; a pulse time adjusting unit 5, wherein the pulse time adjusting unit 5 is connected to the sample holding unit 4; an output synthesis unit 6, wherein the output synthesis unit 6 is connected to the pulse time adjusting unit 5; a pulse period conversion unit 7, wherein the pulse period conversion unit 7 is connected among the logic processing unit 2, the mirror current source 1 and the output synthesis unit 6. The method adopts a full-simulation method to realize the scaling output of any proportion of the duty ratio of the input PWM wave, has practicability to the specific application of low-speed PWM, has simple and clear circuit structure, and is easy to realize.
Referring to fig. 1, the mirror current source 1 linearly detects an on-time of the input PWM wave, the logic processing unit 2 processes the input PWM wave, the sample-and-hold unit 4 holds a peak voltage output by the pulse time conversion unit 3, the pulse time adjustment unit 5 selects a target voltage value generated by a duty ratio, and the output synthesis unit 6 outputs the target PWM wave according to the target voltage value.
Referring to fig. 1, a first input terminal of the pulse time conversion unit 3 is connected to a first output terminal of the mirror current source 1, and a second input terminal of the pulse time conversion unit 3 is connected to an output terminal of the logic processing unit 2.
Referring to fig. 1, the sample-and-hold unit 4 includes: a first operational amplifier 41 and a sample-and-hold circuit 42; a first input terminal of the first operational amplifier 41 is connected to the pulse time conversion unit 3, a second input terminal of the first operational amplifier 41 is connected to the control terminal of the pulse time adjustment unit 5, an output terminal of the first operational amplifier 41 is connected to an input terminal of the sample-and-hold circuit 42, a control terminal of the sample-and-hold circuit 42 is connected to an output terminal of the logic processing unit 2, and an output terminal of the sample-and-hold circuit 42 is connected to an input terminal of the pulse time adjustment unit 5.
Referring to fig. 1, the pulse time adjusting unit 5 includes: a resistance voltage division string 51, a data selector 52 connected to the resistance voltage division string 51, and a selection module 53 connected to the data selector 52; the resistor voltage-dividing string 51 is respectively connected with the sample-and-hold circuit 42 and the second input end of the first operational amplifier 41; the data selector 52 is connected to the output synthesis unit 6.
Referring to fig. 1, the output combining unit 6 includes a second operational amplifier, a first input terminal of which is connected to the output terminal of the data selector 52, and a second input terminal of which is connected to the pulse period converting unit 7.
Referring to fig. 1, a first input terminal of the pulse period converting unit 7 is connected to the reset signal terminal of the logic processing unit 2, and a second input terminal of the pulse period converting unit 7 is connected to a second output terminal of the mirror current source 1.
Referring to fig. 1, the mirror current source 1 includes: first MOS pipe Q1, second MOS pipe Q2 and third MOS pipe Q3, the source of first MOS pipe Q1, the source of second MOS pipe Q2 and the source of third MOS pipe Q3 all are connected to VDD end, the grid of first MOS pipe Q1 is connected to the grid of second MOS pipe Q2, the grid of third MOS pipe Q3 is connected to the switch node, the drain electrode of first MOS pipe Q1 is connected to the switch node, the switch node ground connection. The switching node is located between the gate of the first MOS transistor Q1 and the gate of the second MOS transistor Q2.
Referring to fig. 1, the mirror current source 1 further includes an ammeter, one end of the ammeter is grounded, and the other end of the ammeter is connected to the switch node. The ammeter is used for measuring the current of the connection point of the drain electrode of the first MOS tube Q1 and the switch node.
Referring to fig. 1, the first MOS transistor Q1, the second MOS transistor Q2, and the third MOS transistor Q3 are all PMOS transistors.
The utility model provides a pair of PWM signal duty cycle regulating circuit's theory of operation does: the on _ time of input PWM is linearly detected by charging a capacitor by using a mirror current source 1, the voltage value of Vramp1 represents the on _ time of the current PWM wave in real time, the peak voltage of Vramp1 in the current period is stored by using a first operational amplifier 41 and a sampling and holding circuit 42, the required Vfb value of any proportion, namely Vref, which represents the voltage value generated by any duty ratio is selected by using the feedback resistor string proportion and a selector of the first operational amplifier 41, and then the voltage value is compared with Vramp2 in the lower period by using a second operational amplifier to output the target PWM wave, namely PWM _ out.
The working principle, working process and the like of the present embodiment can refer to the corresponding contents of the foregoing embodiments.
The same or similar parts in the above embodiments in this specification may be referred to each other, and each embodiment is described with emphasis on differences from other embodiments, but the differences are not limited to be replaced or superimposed with each other.
The above examples are only for illustrating the technical solutions of the present invention and not for limiting the same. It will be understood by those skilled in the art that any modification and equivalent arrangement that do not depart from the spirit and scope of the invention should fall within the scope of the claims of the invention.
Claims (9)
1. A PWM signal duty cycle adjustment circuit, comprising:
a mirror current source for providing a constant current;
the logic processing unit is used for accessing an external PWM signal;
the pulse time conversion unit is connected with a first current output end of the mirror current source, and a detection end of the pulse time conversion unit is connected with a first output end of the logic processing unit;
the input end of the sampling and holding unit is connected with the output end of the pulse time conversion unit, and the sampling signal input end of the sampling protection unit is connected with the second output end of the logic processing unit;
a pulse time adjusting unit connected to the sample-and-hold unit;
an output synthesis unit connected to the pulse time adjustment unit;
the pulse period conversion unit is connected among the logic processing unit, the mirror current source and the output synthesis unit; the first input end of the pulse period conversion unit is connected to the reset signal end of the logic processing unit, and the second input end of the pulse period conversion unit is connected to the second output end of the mirror current source.
2. The PWM signal duty ratio adjusting circuit according to claim 1, wherein the mirror current source linearly detects an on time of an input PWM wave, the logic processing unit processes the input PWM wave, the sample and hold unit holds a peak voltage output by the pulse time converting unit, the pulse time adjusting unit selects a target voltage value generated by the duty ratio, and the output synthesizing unit outputs the target PWM wave according to the target voltage value.
3. A PWM signal duty cycle adjusting circuit according to claim 1, wherein a first input terminal of the pulse time converting unit is connected to a first output terminal of the mirror current source, and a second input terminal of the pulse time converting unit is connected to an output terminal of the logic processing unit.
4. The PWM signal duty cycle adjusting circuit according to claim 1, wherein the sample-and-hold unit comprises: a first operational amplifier and a sample-and-hold circuit; the first input end of the first operational amplifier is connected to the pulse time conversion unit, the second input end of the first operational amplifier is connected to the control end of the pulse time adjustment unit, the output end of the first operational amplifier is connected to the input end of the sample-and-hold circuit, the control end of the sample-and-hold circuit is connected to the output end of the logic processing unit, and the output end of the sample-and-hold circuit is connected to the input end of the pulse time adjustment unit.
5. The PWM signal duty cycle adjusting circuit according to claim 4, wherein the pulse time adjusting unit comprises: the device comprises a resistance voltage division string, a data selector connected with the resistance voltage division string and a selection module connected with the data selector; the resistance voltage division string is respectively connected with the sampling hold circuit and the second input end of the first operational amplifier; the data selector is connected to the output combining unit.
6. The PWM signal duty cycle adjusting circuit of claim 5, wherein the output synthesizing unit comprises a second operational amplifier, a first input terminal of the second operational amplifier is connected to the output terminal of the data selector, and a second input terminal of the second operational amplifier is connected to the pulse period converting unit.
7. The PWM signal duty cycle adjusting circuit according to claim 1, wherein the mirror current source comprises: the switch comprises a first MOS tube, a second MOS tube and a third MOS tube, wherein the source electrode of the first MOS tube, the source electrode of the second MOS tube and the source electrode of the third MOS tube are connected to a VDD end, the grid electrode of the first MOS tube is connected to the grid electrode of the second MOS tube, the grid electrode of the third MOS tube is connected to a switch node, the drain electrode of the first MOS tube is connected to the switch node, and the switch node is grounded.
8. The PWM signal duty cycle adjusting circuit of claim 7, wherein the mirror current source further comprises a current meter, one end of the current meter is connected to ground, and the other end of the current meter is connected to the switch node.
9. The PWM signal duty cycle adjusting circuit of claim 7, wherein the first MOS transistor, the second MOS transistor and the third MOS transistor are all PMOS transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022034059.6U CN212935870U (en) | 2020-09-16 | 2020-09-16 | PWM signal duty ratio regulating circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202022034059.6U CN212935870U (en) | 2020-09-16 | 2020-09-16 | PWM signal duty ratio regulating circuit |
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| CN212935870U true CN212935870U (en) | 2021-04-09 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112039504A (en) * | 2020-09-16 | 2020-12-04 | 英麦科（厦门）微电子科技有限公司 | PWM signal duty ratio regulating circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112039504A (en) * | 2020-09-16 | 2020-12-04 | 英麦科（厦门）微电子科技有限公司 | PWM signal duty ratio regulating circuit |
| CN112039504B (en) * | 2020-09-16 | 2024-05-07 | 拓尔微电子股份有限公司 | PWM signal duty cycle regulating circuit |
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| GR01 | Patent grant | ||
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| TR01 | Transfer of patent right |
Effective date of registration: 20220330 Address after: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee after: Tuoer Microelectronics Co.,Ltd. Address before: Unit 410, 1702 Gangzhong Road, Xiamen area, China (Fujian) pilot Free Trade Zone, Xiamen City, Fujian Province Patentee before: INMICRO (XIAMEN) MICROELECTRONIC TECHNOLOGY CO.,LTD. |
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