CN112005498B

CN112005498B - Switch driving device

Info

Publication number: CN112005498B
Application number: CN201980023358.7A
Authority: CN
Inventors: 滨宪治; 小谷尚弘
Original assignee: Rohm Co Ltd
Current assignee: Rohm Co Ltd
Priority date: 2018-04-02
Filing date: 2019-01-15
Publication date: 2024-04-09
Anticipated expiration: 2039-01-15
Also published as: CN112005498A; US11923833B2; US20210044290A1; WO2019193805A1; DE112019000870T5; JP2023015040A; JPWO2019193805A1; JP7371200B2; DE112019000870B4

Abstract

For example, the switch driving device 100 includes: a driver 30 that drives the N-type semiconductor switching element PT1; a current limiting unit 50 capable of limiting a current supplied to a start-up capacitor BC1 included in the bootstrap circuit BTC; and a current control unit 60 that controls an operation of the current limiting unit 50, wherein when the charge voltage of the starting capacitor BC1 exceeds a threshold value, the current control unit 60 drives the current limiting unit 50 and limits the current supplied to the starting capacitor BC 1.

Description

Switch driving device

Technical Field

The present invention relates to a switch driving device.

Background

Some of the switch driving devices used as a switching regulator or a motor driver employ a half-bridge output stage in which two switching elements are connected in series and a connection point between them is connected to a load (for example, see patent document 1 described below). The half-bridge output stage is often combined with a bootstrap circuit to ensure a driving voltage required when an N-type semiconductor switching element (i.e., a high-side switching element) connected to one side of a driving power supply is turned on (for example, see patent document 2 below). In such a switch driving device, in order to secure a gate-source voltage (gate voltage) of a high-side switching element connected to a driving power supply, a charging voltage on a start-up capacitor included in a bootstrap circuit is used.

Prior art literature

Patent literature

Patent document 1: japanese patent application laid-open No. 2015-64045

Patent document 2: japanese patent laid-open publication 2016-82281

Disclosure of Invention

Problems to be solved by the invention

Disadvantageously, depending on the configuration of the switch driving device, the charging voltage on the start-up capacitor may be higher than the gate voltage allowed in the high-side element (allowable gate voltage), that is, so-called overcharge may occur. The overcharge of the start-up capacitor may cause the signal fed to the gate of the switching element to become higher than the allowable gate voltage, which may cause malfunction.

The invention provides a switch driving device which has a simple circuit structure and can reliably and stably drive a high-side element.

Means for solving the problems

To achieve the above object, according to one aspect of the present invention, a switch driving device includes: a gate driver configured to drive the N-type semiconductor switching element; a current limiter configured to limit a current fed to a start-up capacitor included in a bootstrap circuit configured to apply a voltage to the gate driver; and a current controller configured to control operation of the current limiter. The current controller drives the current limiter to limit a current fed to the start-up capacitor when the charging voltage on the start-up capacitor is above a threshold.

With this configuration, the current controller can drive the current limiter to limit the current fed to the starting capacitor according to the state of charge of the starting capacitor. This helps to prevent the gate of the N-type semiconductor switching element from being fed with a drive signal having a voltage level higher than the allowable gate voltage. Therefore, degradation or the like of the N-type semiconductor switching element can be prevented.

In the above configuration, the current limiter preferably includes a switching element configured to be turned on or off according to a signal from the current controller. With this configuration, it is possible to passively limit the current fed to the start-up capacitor.

In the above configuration, preferably, the current controller is configured to determine whether the starting capacitor is being charged and sense the charging voltage on the starting capacitor, and when the starting capacitor is being charged, the current controller is configured to drive the current limiter. With this configuration, it is possible to accurately sense when the boot capacitor is in an overcharged state. Therefore, the N-type semiconductor switching element can be made to operate stably.

In the above configuration, preferably, the current controller is configured to sense the charging voltage on the start-up capacitor based on an end-to-end voltage on the start-up capacitor or a divided voltage thereof. With this configuration, the state of charge of the boot capacitor can be sensed more accurately.

In the above configuration, it is preferable that the N-type semiconductor switching element is a high-side switching element provided between a power source and a load, forming a half-bridge output stage, and the current controller is configured to determine that the start-up capacitor is charged when the high-side switching element is turned off. With this configuration, the state of the boot capacitor entering the overcharged state can be easily sensed.

In the above configuration, preferably, the current controller is configured to determine whether the high-side switching element is on or off by acquiring a drive signal fed from outside to drive the high-side switching element. With this configuration, the overcharged state of the boot capacitor can be sensed with a simple circuit configuration.

In the above configuration, preferably, the N-type semiconductor switching element is a high-side switching element provided between a power supply and a load to form a half-bridge output stage, and the current controller is configured to sense a voltage at a connection point between the high-side switching element and the load to determine that the start-up capacitor is being charged when the voltage is equal to or less than a threshold value. With this configuration, the overcharged state of the boot capacitor can be sensed more accurately.

In the above configuration, preferably, the current limiter is an element whose resistance value is variable, and is connected to an anode side of a start-up diode included in the bootstrap circuit, and the current limiter is configured to sense a voltage of a control power supply to which the bootstrap circuit is connected. Preferably, the current limiter is configured to increase a resistance value of the current limiter when a control voltage is high, and to decrease the resistance value of the current limiter when the control voltage is low.

In the above configuration, preferably, the N-type semiconductor switching element employs a semiconductor made of silicon carbide (SiC).

ADVANTAGEOUS EFFECTS OF INVENTION

According to the present invention, it is possible to provide a switch driving device having a simple circuit structure and capable of reliably and stably driving an N-type semiconductor switching element.

Drawings

Fig. 1 is a schematic diagram showing a motor driving apparatus;

fig. 2 is a block diagram of a power supply provided with a switch driving device according to the present invention;

fig. 3 is a block diagram showing an outline configuration of a driver circuit;

fig. 4 is a timing chart showing an output operation of the switch driving device;

fig. 5 is a circuit diagram of one example of a high-side driver circuit used in the switch driving device according to the present invention;

FIG. 6 is a perspective view of the package from the underside;

fig. 7 is a plan view of a frame on which the elements of the switch driving device are chip-bonded;

fig. 8 is a schematic diagram showing an outline of an integrated circuit constituting a high-side driver circuit;

fig. 9 is a circuit diagram of another example of a high-side driver circuit provided in the switch driving device according to the present invention;

fig. 10 is a diagram showing how the overcharged state of the boot capacitor BC1 is suppressed;

fig. 11 is a circuit diagram of a modified example of the high-side driver circuit according to the present invention;

fig. 12 is a timing chart showing the timing at which overvoltage occurs;

fig. 13 is a circuit diagram showing another example of a high-side driver circuit used in the switch driving device according to the present invention; and

fig. 14 is a plan view showing an example of the configuration of pads in the high-side driver circuit.

Detailed Description

Embodiments of the present invention will be described below with reference to the accompanying drawings.

< first embodiment >

Fig. 1 is a schematic diagram showing a motor driving apparatus. As shown in fig. 1, the motor M is a three-phase alternating current motor. The motor M has a U-phase coil MU, a V-phase coil MV, and a W-phase coil MW (see fig. 2, which will be mentioned later). In the motor M, the coils MU, MV, and MW are star-connected. However, this is not meant to be limiting; instead, they may be delta-connected. The motor M is driven by a motor drive means MMC comprising a motor control unit MCU and a power supply PS.

The motor control unit MCU includes a logic circuit (not shown). Based on the information about the rotor position thereof from the motor M, the motor control unit MCU generates phase-by-phase excitation control signals to control excitation of coils of different phases (U-phase, V-phase, and W-phase) of the motor M at appropriate timings. The motor control unit MCU also changes the timing of excitation phase switching, for example, when the rotation direction of the motor M is switched, and when the rotation speed of the motor M is changed.

The power supply PS supplies driving power (current) to coils of different phases of the motor M at regular intervals according to the phase-by-phase excitation control signal fed from the motor control unit MCU.

Next, the power supply PS will be described with reference to the related drawings. Fig. 2 is a block diagram of a power supply provided with a switch driving device according to the present invention. As shown in fig. 1 and 2, the power supply PS includes a switch driving device 100 and a bootstrap circuit BTC. The switch driving device 100 includes a driver circuit DRV and a power switch circuit PSW.

As shown in fig. 2, in the switch driving device 100, the driver circuit DRV and the power switch circuit PSW constitute a bootstrap circuit BTC together with the diodes DiU, diV, and DiW, contained in one package ppg. Here, the start-up diodes DiU, div, and DiW are contained in the package Pkg. However, this is not meant to be limiting; they may alternatively be provided outside the package Pkg.

As shown in fig. 2, the power supply PS is connected to a first power supply PW1 and a second power supply PW2. The first power supply PW1 supplies a control voltage VCC (e.g., 10V to 25V) to the driver circuit DRV. The second power supply PW2 supplies a driving voltage VDC (e.g., about 300V (for a 600V model)) for driving the motor M.

The power switching circuit PSW includes six transistors PT1 to PT6. As the six transistors PT1 to PT6, for example, power MOSFETs are used. These power MOSFETs are built in a semiconductor substrate such as silicon carbide (SiC). That is, the transistors PT1 to PT6 are SiC-MOSFETs. The transistors PT1 to PT6 are all N-type MOSFETs.

In the power switching circuit PSW, the source of the transistor PT1 and the drain of the transistor PT2 are connected together. The drain of the transistor PT1 is connected to the second power source PW2. The source of the transistor PT2 is connected to the ground. In practice, the transistor PT2 may be connected to the ground point via a resistor for current sensing. The U-phase coil MU of motor M is connected to the connection point between the source of transistor PT1 and the drain of transistor PT 2.

Transistors PT3 and PT4 are connected together in a similar manner to transistors PT1 and PT 2. The V-phase coil MV of motor M is connected to the connection point between the source of transistor PT3 and the drain of transistor PT 4. Transistors PT5 and PT6 are connected together in a similar manner to transistors PT1 and PT 2. The W-phase coil MW of the motor M is connected to a connection point between the source of the transistor PT5 and the drain of the transistor PT6.

In this specification, the transistors PT1, PT3, and PT5 on the second power supply PW2 side of the power switch circuit PSW are referred to as high-side transistors, and the transistors PT2, PT4, and PT6 on the ground point side are referred to as low-side transistors.

The driver circuit DRV includes a high-side driver circuit 10 and a low-side driver circuit 20. The high-side driver circuit 10 is connected to the gates of the high-side transistors PT1, PT3, and PT5, and supplies driving signals HU, HV, and HW to these gates, respectively. When the respective driving signals HU, HV and HW have a voltage level of H level, the high-side transistors PT1, PT3 and PT5 are turned on. The low-side driver circuit 20 is connected to the gates of the low-side transistors PT2, PT4, PT6, and supplies driving signals LU, LV, LW to these gates, respectively. When the respective driving signals LU, LV, and LW have voltage levels of H level, the low-side transistors PT2, PT4, and PT6 are turned on. Here, the voltage level of the H level indicates a state where the voltage is higher than the predetermined voltage, and the voltage level of the L level indicates a state where the voltage is lower than the predetermined voltage.

For example, in the case where the transistors PT1 and PT4 are on and all other transistors are off, the drive voltage VDC from the second power source PW2 is applied to the U-phase coil MU and the V-phase coil MV. That is, a current flows from the U-phase coil MU to the V-phase coil MV. In this way, on/off timings of the transistors PT1 to PT6 are switched in accordance with the drive signal from the driver circuit DRV so that currents are supplied to the coils MU, MV, MW of different phases, and the coils are excited, thereby driving the motor M to rotate.

As shown in fig. 2, the high-side driver circuit 10 and the low-side driver circuit 20 operate by feeding a control voltage VCC from a first power supply PW 1. The high-side driver circuit 10 and the low-side driver circuit 20 are connected to the motor control unit MCU, and receive the energization control signals huin, hvin, hwin, luin, lvin and lwin therefrom for controlling energization of the transistors PT1 to PT 6. The excitation control signals huin, hvin and hwin are fed to the high-side driver circuit 10, and the excitation control signals luin, lvin and lwin are fed to the low-side driver circuit 20.

The driver circuit DRV feeds the drive signal HU to the gate of the transistor PT1 and the drive signal LU to the gate of the transistor PT 2. Likewise, the driver circuit DRV feeds the drive signal HV to the gate of the transistor PT3, and feeds the drive signal LV to the gate of the transistor PT 4. Further, the driver circuit DRV feeds the drive signal HW to the gate of the transistor PT5, and feeds the drive signal LW to the gate of the transistor PT 6.

The bootstrap circuit BTC is a circuit that supplies the high-side driver circuit 10 with a voltage required to drive the high-side transistors PT1, PT3, and PT 5. The bootstrap circuit BTC is provided to each of the high-side transistors PT1, PT3, and PT 5. For example, it is a circuit connected between the first power supply PW1 and the source of the transistor PT1, and has a start-up diode DiU and a start-up capacitor BC1 connected in series from the first power supply PW1 side. The voltage at the connection point between the start-up diode DiU and the start-up capacitor BC1 is taken by the high-side driver circuit 10 as the voltage required to drive the high-side transistor PT 1. The bootstrap circuit BTC may also have a resistor arranged between the first power supply PW1 and the start-up diode DiU for generating a current having a predetermined current value, which diode is omitted here.

The bootstrap circuit BTC is further provided with a start-up diode DiV and a start-up capacitor BC2 corresponding to the high-side transistor PT3 so that the high-side driver circuit 10 acquires a voltage required to drive it. The bootstrap circuit BTC is further provided with a start-up diode DiW and a start-up capacitor BC3 corresponding to the high-side transistor PT5, so that the high-side driver circuit 10 acquires a voltage required to drive it.

Next, the driver circuit will be described in more detail. The driver circuit DRV in the switch driving device 100 includes a circuit for driving the transistors PT1 and PT2, a circuit for driving the transistors PT3 and PT4, and a circuit for driving the transistors PT5 and PT 6. These circuits for driving the transistors all have the same configuration. Therefore, a part of a circuit serving as the driving transistors PT1 and PT2 will be described below as the driver circuit DRV. Also, a circuit including a start-up diode DiU corresponding to the transistor PT1 and a start-up capacitor BC1 will be described below as the bootstrap circuit BTC. The transistor PT1 will be referred to as a high-side transistor PT1, and the transistor PT2 as a low-side transistor PT2. The connection point between the source of the high-side transistor PT1 and the drain of the low-side transistor PT2 is referred to as a first point P1, and the connection point between the cathode of the start-up diode DiU in the bootstrap circuit BTC and the start-up capacitor BC1 is referred to as a second point P2.

Fig. 3 is a block diagram showing an outline of the configuration of the driver circuit. As described earlier, the driver circuit DRV shown in fig. 3 includes the high-side driver circuit 10 and the low-side driver circuit 20. In the switch driving device 100 according to the present invention, the low-side driver circuit 20 has the same configuration as that used in the conventional switch driving device. Accordingly, a detailed description of the configuration and operation of the low-side driver circuit 20 will not be given.

As shown in fig. 3, the high-side driver circuit 10 includes a high-side gate driver 30, an input signal control circuit 40, a current limiter 50, a current controller 60, and a high withstand voltage level shift circuit 70.

The input signal control circuit 40 feeds an excitation control signal (huin here) from the motor control unit MCU to the high-side gate driver 30 via the high withstand voltage level shift circuit 70.

Based on the signal fed from the input signal control circuit 40, the high-side gate driver 30 generates a drive signal HU for driving the high-side transistor PT1 and feeds it to the gate of the high-side transistor PT 1.

The high-side gate driver 30 acquires the voltage required to drive the high-side transistor PT1 from the bootstrap circuit BTC composed of the start-up diode DiU and the start-up capacitor BC 1. The bootstrap circuit BTC charges the start-up capacitor BC1 with a current fed from the first power supply PW1 such that the voltage across the start-up capacitor BC1 is, for example, equal to or higher than the gate threshold voltage. This keeps the voltage VB at the second point P2 higher than the voltage S at the first point P1 by the amount of the charging voltage on the start-up capacitor BC1, regardless of what voltage is present at the first point P1. Therefore, the high-side gate driver 30 can obtain the voltage required to drive the high-side transistor PT1 by obtaining the voltage VB at the second point P2.

A current limiter 50 is provided in a circuit connected between the first power supply PW1 and the start-up capacitor BC 1; more specifically, it is disposed between the first power supply PW1 and the anode of the start diode DiU. The current limiter 50 limits the current fed from the first power supply PW1 to the start-up capacitor BC1 according to a signal (current limit signal) from the current controller 60. That is, the end-to-end voltage (charging voltage) on the start-up capacitor BC1 is regulated (limited) by the current limiter 50. The construction of the current limiter 50 will be described in detail later.

Next, the operation of the switch driving device 100 according to the present invention will be described with reference to fig. 4. Fig. 4 is a timing chart showing the U-phase output operation (operation of mode 2 described later) of the switch driving device 100, and is a diagram showing the excitation control signals huin, luin, and the voltage VS from top to bottom. In the figure, vsd represents the source-drain voltage of the low-side transistor PT2, and Vf represents the forward voltage drop across the parasitic diode accompanying the low-side transistor T2. The V-phase and W-phase output operations are similar to the U-phase output operations, for which description the excitation control signals uin and uin have to be simply read as excitation control signals hvin and lvin, or as excitation control signals hwin and lwin, respectively. In fig. 4, for simplicity of description, or a slight delay time.

In the switch driving device 100, the high-side transistor PT1 and the low-side transistor PT2 are controlled to operate complementarily. That is, the high-side transistor PT1 and the low-side transistor PT2 are controlled such that, as observed between the time points t3 and t4 and between the time points t7 and t8, when the high-side transistor PT1 is turned on (uin=h), the low-side transistor PT2 is turned off (uin=l), and as observed between the time points t1 to t2, between the time points t5 and t6, and between the time points t9 and t10, when the low-side transistor PT2 is turned on (uin=h), the high-side transistor PT1 is turned off (uin=l). If a through current passes between the high-side transistor PT1 and the low-side transistor PT2, it may degrade or destroy these transistors. To avoid the situation observed between the time points t2 and t3, between the time points t4 and t5, between the time points t6 and t7, and between the time points t8 and t9, for example, switching from the on state of the high-side transistor PT1 to the on state of the low-side transistor PT2 is accompanied by a dead time (huin=luin=l) in which both the high-side transistor PT1 and the low-side transistor PT2 are off.

In the switch driving device 100 operated as described above, turning on the high-side transistor PT1 and turning off the low-side transistor PT2 causes the voltage from the second power source PW2 to be applied to the U-phase coil MU as a load; i.e. providing a current. At this time, the voltage VS at the first point P1 may be substantially equal to the driving voltage VDC of the second power source PW2, i.e., about 300V.

Due to the bootstrap circuit BTC, the voltage VB at the second point P2 to which the high-side gate driver 30 is connected is higher than the voltage VS at the first point P1 by an end-to-end voltage (hereinafter simply referred to as a charging voltage VBs) on the start-up capacitor BC1 generated by being charged. For example, in the case where the voltage VS at the first point P1 fluctuates between 0V and 300V, assuming that the charging voltage on BC1 is equal to 18V, the voltage VB at the second point P2 fluctuates between about 18V and 318V.

The high-side gate driver 30 can obtain a voltage at any time that can drive the high-side transistor PT1 by feeding the voltage VB from the second point P2. That is, the boot capacitor BC1 is used as a floating power supply. The start-up capacitor BC1 is configured to be chargeable to a voltage above the gate threshold voltage.

Charging of the start-up capacitor BC1 will now be described. First, the description proceeds assuming that the current limiter 50 does not exist. In the switch driving device 100, a state in which the motor current passes in the forward direction of the low-side transistor PT2 will be referred to as mode 1, and a state in which the body diode of the low-side transistor PT2 is turned on (during low-side regeneration) will be referred to as mode 2. The start-up capacitor BC1 is charged in mode 1 and mode 2.

In mode 1, the U-phase coil MU has a motor current IM flowing from the neutral point of the motor M through the first point P1 and the low-side transistor PT2 into the ground terminal in the U-phase coil MU. Here, the voltage VS at the first point P1 is equal to or approximately equal to the ground potential (0V). In practice, the voltage here is im×r higher than 0V due to the on-resistance of the low-side transistor PT2 and the resistance component R of the current sense resistor. Accordingly, the end-to-end voltage on the start-up capacitor BC1 is approximately equal to the control voltage VCC from the first power supply PW1, and in this state, the start-up capacitor BC1 is charged to the control voltage VCC. More precisely, when the charge voltage on the start-up capacitor BC1 is VBS, the forward voltage on the start-up diode DiU is VFB, the on-resistance value of the low-side transistor PT2 is Ron, and the motor current is IM, vbs=vcc-VFBOOT-ron×im. In mode 1, charging occurs when the voltage VB at the second point P2 becomes equal to or lower than the charging voltage VBs described above.

In mode 2, the operation proceeds as follows. As shown in fig. 3, the high-side transistor PT1 and the low-side transistor PT2 include parasitic diodes (body diodes). Let the forward voltage drop across the parasitic diode of the low-side transistor PT2 be Vf. When the motor M is operated regeneratively in mode 2, the U-phase coil MU has a motor current flowing therein from the first point P1 to the neutral point. At this time, the high-side transistor PT1 is turned off, and thus no current passes from the second power supply PW 2. Although the low-side transistor PT2 is turned off, current passes through the parasitic diode. Thus, the voltage VS at the first point P1 becomes equal to-vf, which is lower than the ground voltage. Thus, the end-to-end voltage on start-up capacitor BC1 is approximately equal to (vcc+vf). More precisely, the start-up capacitor BC1 is charged to vbs=vcc-vfboot+vf. Therefore, the charge voltage VBS on the start-up capacitor BC1 is higher in mode 2 than in mode 1.

The end-to-end voltage (vcc+vf) on the start-up capacitor BC1 may become higher than the allowed gate-source voltage (hereinafter referred to as the allowed gate voltage) in the high-side transistor PT1. If the end-to-end voltage (vcc+vf) on the start-up capacitor BC1 becomes higher than the allowable gate voltage, it may deteriorate or damage the high-side transistor PT1. The state where the charge voltage VBS to which the start-up capacitor BC1 has been charged reaches a point of a voltage higher than the allowable gate voltage of the high-side transistor PT1 will be referred to as an overcharged state. In particular, siC-based transistors are prone to the overcharged state described above due to the high forward voltage drop Vf of the parasitic diode that accompanies them.

To avoid this, in the high-side driver circuit 10, a circuit leading from the first power supply PW1 to the start diode DiU is provided with a current limiter 50. The current limiter 50 is operated to limit the current fed to the start-up capacitor BC1, thereby preventing the start-up capacitor BC1 from entering an overcharged state.

Next, as a main part of the switch driving device 100 according to the present invention, the high-side driver circuit 10 will be described. Fig. 5 is a circuit diagram of an example of the high-side driver circuit 10 used in the switch driving device 100 according to the present invention. As described above, the overcharged state of the start-up capacitor BC1 is caused by the end-to-end voltage (vcc+vf) on the start-up capacitor BC1 becoming too high. Further, the pilot capacitor BC1 is more likely to be overcharged when the control voltage VCC from the connected first power supply PW1 is high than when it is low. Therefore, in the switch driving device 100, the high-side driver circuit 10 is configured so that the start-up capacitor BC1 does not become overcharged regardless of which power supply voltage is connected. The high-side driver circuit 10 will now be described in detail.

As shown in fig. 5, the high-side driver circuit 10 includes a high-side gate driver 30, an input signal control circuit 40, a current limiter 50, a current controller 60, and a high withstand voltage level shift circuit 70. The current controller 60 sends a signal to the current limiter 50 to drive it to generate a voltage drop between the first power supply PW1 and the startup diode DIU, thereby reducing the voltage charging the startup capacitor BC 1. In other words, the current limiter 50 limits the current that charges the start-up capacitor BC 1.

The excitation control signal huin from the motor control unit MCU is fed to the input signal control circuit 40 (see fig. 1 and the like). The input signal control circuit 40 includes an inverter (schmitt buffer) 401 that converts the excitation control signal huin into an L signal or an H signal. It further includes a level shift circuit 402 that raises the voltage level of the signal output from the inverter 401. This facilitates the processing of signals in the high-side driver circuit 10. The input signal control circuit 40 further includes a pulse generator 403, and the pulse generator 403 outputs a set pulse signal and a reset pulse signal based on the signal output from the level shift circuit 402.

The set pulse signal and the reset pulse signal output from the pulse generator 403 are fed to the high withstand voltage level shift circuit 70. The high withstand voltage level shift circuit 70 includes a transistor 71, a transistor 72, a resistor 73, and a resistor 74. Transistors 71 and 72 are N-type MOSFETs and are high withstand voltage transistors. The drain of the transistor 71 is connected to the second point P2 via a resistor 73 or to a point at the same potential as the second point P2. The source of the transistor 71 is connected to a ground via a resistor not shown, and the gate of the transistor 71 is fed with a pulse signal from the pulse generator 403. The drain of the transistor 72 is connected to the second point P2 via a resistor 74 or to a point at the same potential as the second point P2. The source of the transistor 72 is connected to the ground via a resistor not shown, and the gate of the transistor 72 is fed with a pulse signal from the pulse generator 403. The circuit including the transistor 71 and the resistor 73 (i.e., the circuit outputting the set pulse signal) and the circuit including the transistor 72 and the resistor 74 (i.e., the circuit outputting the reset pulse signal) have signal lines arranged symmetrically, respectively. The connection point between the drain of the transistor 71 and the resistor 73, and the connection point between the drain of the transistor 72 and the resistor 74 are respectively connected to a clamp circuit 301 (see fig. 8), and the clamp circuit 301 limits the level of an input signal input to an inverter (not shown) constituting the input stage of the high-side gate driver 30 to a predetermined value or less.

As described above, the signal lines of the set pulse signal and the reset pulse signal are symmetrically arranged. For example, the length from the connection point between the drain of the transistor 71 and the resistor 73 to the clamp circuit 301 (i.e., the length of the conductor of the set pulse signal, for example) is equal to or approximately equal to the length from the connection point between the drain of the transistor 72 and the resistor 74 to the clamp circuit 301 (i.e., the length of the conductor of the reset pulse signal, for example). Further, the pair consisting of the transistor 71 and the resistor 73 and the pair consisting of the transistor 72 and the resistor 74 have their respective elements symmetrically arranged. This arrangement results in equal conductor resistance and equal parasitic capacitance and helps to suppress the deviation between signals due to conductor layout.

The current limiter 50 includes a transistor 501 and a resistor 502. A resistor 502 is provided in a circuit connected between the first power supply PW1 and the start diode DiU. The resistor 502 determines the value of the current fed to the start-up capacitor BC 1. The transistor 501 is connected in parallel with the resistor 502. The transistor 501 is a P-type MOSFET, and its source is connected to the connection point of the first power source PW1 and the resistor 502. The drain of transistor 501 is connected to the connection point between resistor 502 and start-up diode DiU. The gate of transistor 501 is fed with a signal from current controller 60.

The current controller 60 senses the voltage of the first power PW 1. For example, assume that VCC1 or VCC2 (< VCC 1) is allowed as the voltage of the first power supply PW 1. Then, when the first power supply PW1 generates a voltage VCC1, the current controller 60 supplies an H level signal to the gate of the transistor 501. That is, when the first power supply PW1 generates the voltage VCC1, the transistor 501 turns off. On the other hand, when the first power supply PW1 generates the voltage VCC2, the current controller 60 supplies an L-level signal to the gate of the transistor 501. That is, when the first power PW1 generates the voltage VCC2, the transistor 501 is turned on. As the current controller 60, a well-known UVLO circuit, for example, having a modified threshold voltage, may be used, and thus a detailed description will not be given in this regard.

For example, the resistance value of the resistor 502 is R1, and the resistance value of the transistor 501 is R2. Here, R1R 2. When the first power supply PW1 generates the voltage VCC1, the transistor 501 turns off based on a signal from the current controller 60. Therefore, the resistance value of the current limiter 50 is equal to R1. On the other hand, when the first power supply PW1 generates the voltage VCC2, the transistor 501 is turned on based on a signal from the current controller 60. Therefore, the resistance value of the current limiter 50 is equal to the combined resistance of the transistor 501 and the resistor 502 connected in parallel, that is, r1×r2/(r1+r2). Therefore, when the first power supply PW1 is higher, the current limiter 50 has a higher resistance value, and the current limiter 50 generates a higher voltage drop. This means that the current charging the start-up capacitor BC1 is low. Conversely, when the voltage of the first power supply PW1 is low, the current limiter 50 has a low resistance value, and the current limiter 50 generates a small voltage drop. This means that the current charging the start-up capacitor BC1 is higher.

With the above configuration, the switch driving device 100 can operate, for a user using it, with the control voltage VCC set at a high voltage and thus having a small margin for preventing overcharge, with a high resistance value, and for a user using it, with the control voltage VCC set at a low voltage and thus having a large margin for preventing overcharge, with a low resistance value.

As described above, the switch driving device 100 is formed to be accommodated in a single package Pkg. The package Pkg of the switch driving device 100 will now be described with reference to the related drawings. Fig. 6 is a perspective view of the package Pkg seen from the lower side. In the package Pkg, as shown in fig. 7 to be referred to later, the high-side driver circuit 10, the low-side driver circuit 20, the power switch circuit PSW, and the start diodes DiU, diV, and DiW are mounted on the frame BD and then sealed in the resin sealing member PB. The resin sealing member PB covers the frame BD with an electrically insulating resin. From the side surface of the resin sealing member PB, 25 terminals Pn1 to Pn25 protrude. These terminals will also be described below with reference to the aforementioned fig. 2.

Terminals Pn1, pn17, and Pn25 are non-connection terminals. Terminals Pn2 to Pn4 are floating power terminals of U-phase, V-phase, and W-phase (i.e., terminals fed with the voltage VB generated for each phase in the bootstrap circuit BTC). Terminals Pn5 to Pn7 are terminals fed with signals from the motor control unit MCU, and via these terminals, excitation control signals (huin, hvin, hwin) of high-side transistors PT1, PT3, and PT5 of U-phase, V-phase, and W-phase are fed to the high-side driver circuit 10. The terminal Pn8 is a terminal that feeds the control voltage VCC from the first power supply PW1 to the high-side driver circuit 10. Terminals Pn9 and Pn16 are ground terminals. Terminals Pn10 to Pn12 are terminals to which signals from the motor control unit MCU are fed, and via these terminals, excitation control signals (luin, lvin, lwin) of the low-side transistors PT2, PT4, PT6 of the U-phase, V-phase, W-phase are fed to the low-side driver circuit 20, respectively.

The terminal Pn13 is a terminal that feeds the control voltage VCC from the first power supply PW1 to the low-side driver circuit 20. The terminal Pn14 is a terminal via which an error signal of the switch driving device 100 is transmitted from the low-side driver circuit 20 to the motor control unit MCU. Terminal Pn15 is a short trip voltage sensing terminal. Terminals Pn18 to Pn20 are source electrodes of low-side transistors PT2, PT4, and PT6 of the U-phase, V-phase, and W-phase, respectively. Terminals Pn21 to Pn23 are output terminals connected to U-phase coil MU, V-phase coil MV, and W-phase coil MW, respectively. The terminal Pn24 is connected to the second power supply PW2, and feeds the drive voltage VDC to the power switch circuit PSW in the switch driving device 100.

As described above, the switch driving device 100 is connected to the first power source PW1 supplying the control voltage VCC and the second power source PW2 supplying the driving voltage VDC. It is assumed that the control voltage VCC is a low voltage and the driving voltage VDC is a high voltage. In the package ppg, terminals Pn5 to Pn16 and Pn18 to Pn20 are low-voltage side terminals to which a control voltage VCC or lower is applied, and terminals Pn2 to Pn4 and Pn21 and Pn24 are high-voltage side terminals to which a drive voltage VDC is applied. In the package Pkg, the gap between the low-voltage side terminals is smaller than the gap between the high-voltage side terminals. This is because the higher the voltage applied to the terminals, the more it is necessary to avoid short circuits between adjacent ones of them, and the greater the electrical effects (e.g., noise) they exert on the surrounding terminals and circuits.

Next, the arrangement of the internal components of the package Pkg of the switch driving device 100 will be described with reference to the related drawings. Fig. 7 is a plan view of the frame BD on which the elements of the switch driving device 100 are chip-bonded. As shown in fig. 7, in the middle portion of the frame BD, the high-side transistors PT1, PT3, and PT5 and the low-side transistors PT2, PT4, and PT6 are arranged in a row. The high-side transistors PT1, PT3, and PT5 and the low-side transistors PT2, PT4, and PT6 are elements to which a high voltage is applied (i.e., high withstand voltage elements), and are arranged with such a gap therebetween that they do not electrically affect each other. The high-side driver circuit 10 driving the high-side transistors PT1, PT3, and PT5 and the low-side driver circuit 20 driving the low-side transistors PT2, PT4, and PT6 are each configured as a single chip IC. Such a gap is provided between the high-side driver circuit 10 and the high-side transistors PT1, PT3, and PT5 so as not to electrically influence each other. Such a gap is provided between the low-side driver circuit 20 and the high-side transistors PT2, PT4, and PT6 so as not to electrically influence each other.

The high-side driver circuit 10 is provided in the middle or substantially in the middle in the arrangement direction of the high-side transistors PT1, PT3, PT 5. The high-side driver circuit 10 and the high-side transistors PT1, PT3, and PT5 are connected together by a wire BW of a low-resistivity metal such as gold. The position where the high-side driver circuit 10 is mounted on the frame BD is determined such that the wire BW has a length within a given range. As shown in fig. 7, the transistors PT1 to PT6 and the terminals Pn18 to Pn23 are connected together so as to correspond to each other, and they are also connected together by the wire BW. The positions of the setting transistors and terminals are determined so that the wire BW has a length within a given range. As the wire BW connecting between the transistors PT1 to PT6 and the terminals Pn18 to Pn23, an aluminum wire is used.

The high side driver circuit 10 and the start-up diodes DiU, diV and DiW are also connected together by a wire BW. The arrangement of the high-side driver circuit 10 and the start diodes DiU, diV, and DiW is determined so that the wire BW has a length within a given range. The high-side driver circuit 10 and the frame BD are connected together by a wire BW, and are formed such that the wire BW has a length within a given range. The low-side driver circuit 20 and the frame BD are connected together by a wire BW, and are formed such that the wire BW has a length within a given range.

By mounting the respective elements at appropriate positions on the frame BD in this way, it is possible to bring the length of the wire BW within a given range, thereby suppressing variations in the resistance and parasitic capacitance of the wire BW, and thus suppressing signal delays and the like due to variations in the resistance and parasitic capacitance of the wire BW. Therefore, the motor M can be accurately operated. In addition, shortening the wire BW helps to reduce defects in the manufacturing process, such as displaced wires.

As described above, the high-side driver circuit 10 is fed with both the high-voltage driving voltage VDC and the low-voltage control voltage VCC. The high-side driver circuit 10 includes an element (circuit) driven by a control voltage VCC, and an element (circuit) driven by a drive voltage VDC. The configuration of the high-side driver circuit 10 will now be described in detail with reference to the relevant drawings. Fig. 8 is a schematic diagram showing an outline of the configuration of an integrated circuit device constituting the high-side driver circuit 10. As shown in fig. 8, the high-side driver circuit 10 has an input block BK1 in which an input signal control circuit 40 (specifically, an inverter 401 and a level shift circuit 402) and a current controller 60 are arranged, the input signal control circuit 40 being fed with excitation control signals huin, hvin, and hwin. The high-side driver circuit 10 also has a U-phase block BKU, a V-phase block BKV, and a W-phase block BKW of the high-side gate driver 30 including gates of high-side transistors PT1, PT3, and PT5 for driving the U-phase, V-phase, and W-phase, respectively. The high-side driver circuit 10 also has current limiter regions RESU, RESV, and RESW, in which the current limiters 50 of the U-phase, V-phase, and W-phase are formed, respectively.

As shown in fig. 8, the input block BK1 is arranged at the left-hand end portion of the semiconductor substrate (chip). On the right side of the input block BK1, a W-phase block BKW is disposed adjacent to the input block BK1, a V-phase block BKV is disposed immediately right thereof, and a U-phase block BKU is disposed at the rightmost end portion. The current limiter regions RESU, RESV, and RESW are all arranged at the upper end of the semiconductor substrate (chip), and are arranged above the W-phase block BKW, the V-phase block BKV, and the U-phase block BKU, respectively. The anodes of the start-up diodes DiU, diV and DiW are connected to the current limiter areas RESU, RESV and RESW, respectively. Terminals Pn2 to Pn4 are connected to power supply pads of U-phase block BKU, V-phase block BKV, and W-phase block BKW.

The input block BK1 is a so-called low-voltage block in which elements controlled with a control voltage VCC (or an internal power supply voltage VREG generated based thereon) are arranged. In the input block BK1, in order to prevent a malfunction of the current controller 60, it is disposed in a region distant from the W-phase block BKW, that is, here, disposed at the upper left of the W-phase block BKW.

In each of the W-phase block BKW, the V-phase block BKV, and the U-phase block BKU, a pulse generator 403 in the input signal control circuit 40 is provided, and so is the high withstand voltage level shift circuit 70 and the high side gate driver 30. In the high-side gate driver 30, a clamp circuit 301 is provided. The high withstand voltage level shift circuit 70 and the high side gate driver 30 are regions to which the driving voltage VDC is applied, and thus are high voltage regions. As shown in fig. 8, the high withstand voltage level shift circuit 70 and the clamp circuit 301 are arranged adjacent to each other in the left-right direction, and are arranged with their respective intermediate lines aligned in the up-down direction. Accordingly, the structures of the wiring pattern of the signal line for transmitting the set pulse signal and the element connected thereto, and the structures of the wiring pattern of the signal line for transmitting the reset pulse signal and the element connected thereto are symmetrical to each other about the intermediate line just mentioned. This helps suppress variations in signals (more specifically, a set pulse signal and a reset pulse signal fed to an RS flip-flop (not shown) via an inverter (not shown) provided in the first stage of the high-side gate driver 30) from the high withstand voltage level shift circuit 70 to the clamp circuit 301.

The U-phase block BKU, the V-phase block BKV, and the W-phase block BKW each include a pulse generator 403. The pulse generators 403 in the U-phase block BKU, the V-phase block BKV, and the W-phase block BKW are respectively fed with signals for respectively controlling the energization of the high-side transistors PT1, PT3, and PT5 of different phases from the level shift circuit 402 arranged in the input block BK1 (but in fig. 8, the level shift circuit 402 is shown as a single block, in practice, the input block BK1 includes a level shift circuit for each of the different phases).

The semiconductor substrate (chip) of the high-side driver circuit 10 is a multilayer substrate having a plurality of (e.g., two) wiring layers. The first wiring layer formed on the element forming region of the semiconductor substrate (chip) has pattern wirings PC11, PC12, and PC13 extending upward from the right-hand end portion of the level shift circuit 402. The pattern wirings PC11, PC12, and PC13 are arranged between the input block BK1 and the W-phase block BKW, and are arranged parallel to each other in the left-right direction. The upper ends of the pattern wirings PC11, PC12, PC13 reach the upper end of the W-phase block BKW. On the second wiring layer arranged on the first wiring layer, pattern wirings PC21, PC22, and PC23 extending in the left-right direction are arranged, with the pattern wiring PC11 connected to the pattern wiring PC21, the pattern conductor PC12 connected to the pattern wiring PC22, and the pattern wiring PC13 connected to the pattern wiring PC23, each pair crossing an interlayer via (not shown). The pattern wirings PC21, PC22, and PC23 are arranged parallel to each other in the up-down direction. The pattern wiring PC21 is connected to the pulse generator 403 in the U-phase block BKU. The pattern wiring PC22 is connected to the pulse generator 403 in the V-phase block BKV. The pattern wiring PC23 is connected to the pulse generator 403 in the W-phase block BKW. The illustration in fig. 8 is only an example, and the layout of the arrangement pattern wiring may be modified as necessary.

As described above, providing the pattern wirings PC11, PC12, and PC13 in the first wiring layer and the pattern wirings PC21, PC22, and PC23 in the second wiring layer helps prevent the pattern wirings connected from the level shift circuit 402 to each of the U-phase block BKU, the V-phase block BKV, and the W-phase block BKW from intersecting other signals. Further, these pattern wirings are arranged to form a detour around the current controller 60. This makes the signal sent from the level shift circuit 402 to the pulse generator 403 less likely to be affected by other signals.

As described above, in the switch driving device 100, the bootstrap circuit BTC is reliably operated to ensure the voltage required for the operation of the high-side transistors PT1, PT3, and PT 5. In addition, the start-up capacitor BC1 is prevented from being overcharged, thereby preventing the driving signals for driving the high-side transistors PT1, PT3, and PT5 from becoming equal to or higher than the allowable gate voltage. Therefore, the high-side transistors PT1, PT3, and PT5 can be reliably operated, and degradation, destruction, and the like of the high-side transistors PT1, PT3, and PT5 due to being fed with a drive signal equal to or higher than the allowable gate voltage can be prevented.

< second embodiment >

Fig. 9 is a circuit diagram of another example of a high-side driver circuit provided in the switch driving device according to the present invention. The switch driving device 100A of this embodiment includes, in the high-side driver circuit 10A, an input signal control circuit 40A, a current limiter 50A, and a current controller 60A, which are different from those in the switch driving device 100. The high withstand voltage level shift circuit 70 here has the same configuration as in the first embodiment, and thus is not shown in detail here.

As shown in fig. 9, the current limiter 50A includes a current limiting transistor 51. The current limiting transistor 51 is a P-type MOSFET. The source of the current limiting transistor 51 is connected to a first power supply PW1. The drain of the current limiting transistor 51 is connected to the anode of the start-up diode DiU. The gate of the current limiting transistor 51 is fed with a current limiting signal CLMT from the current controller 60A.

When the current limit signal CLMT is an L signal, the current limit transistor 51 is turned on, and a current is fed to the start-up capacitor BC1. When the current limit signal CLMT is an H signal, the current limit transistor 51 is turned off and limits the current supply to the start-up capacitor BC1.

The current controller 60A includes a voltage sensing circuit 61 and a level shifting circuit 62. The voltage sensing circuit 61 senses the voltage (VB-VS) of the second point P2 relative to the first point P1. In other words, the voltage (VB-VS) is the charging voltage VBS on the start-up capacitor BC1.

As shown in fig. 9, the voltage sensing circuit 61 includes two resistors 611 and 612, and the two resistors 611 and 612 are voltage dividing resistors connected in series between the second point P2 and the first point P1. The connection point between the resistors 611 and 612 is connected to an inverting input terminal of the comparator 613, to which a voltage higher than the voltage VS of the first point P1 by a prescribed voltage is fed. The prescribed voltage is a threshold voltage. That is, the comparator 613 outputs an H signal before the voltage (VB-VS) exceeds the threshold voltage. When the voltage (VB-VS) exceeds the threshold voltage, the comparator 613 outputs an L signal. The output of the comparator 613 is fed to the level shift circuit 62.

The level shift circuit 62 receives a signal from the voltage sense circuit 61 and a signal from the input signal control circuit 40A, and feeds a current limit signal to the current limiter 50A.

The level shift circuit 62 includes a first transistor 621, a second transistor 622, a current sense resistor 623, and a comparator 624. The first transistor 621 is a P-type MOSFET, and the second transistor 622 is an N-type MOSFET. The source of the first transistor 621 is connected to the second point P2 or to the same potential as the second point P2. The drain of the first transistor 621 is connected to the drain of the second transistor 622. The gate of the first transistor 621 is fed to the output signal of the comparator 613 in the voltage sensing circuit 61. The source of the second transistor 622 is grounded via a resistor 623. The gate of the second transistor 622 is fed with a signal from the input signal control circuit 40A. A surge absorbing diode 6221 is connected between the gate and the source of the second transistor 622.

The voltage at the connection point between the source of the second transistor 622 and the resistor 623 is fed to the non-inverting input terminal of the comparator 624. Between the non-inverting input terminal of the comparator 624 and the ground terminal, a surge absorbing diode 6241 is connected with its polarity as shown. The inverting input terminal of the comparator 624 is fed with a predetermined threshold voltage. The output of the comparator 624 is fed as a current limit signal CLMT to the gate of the current limit transistor 51 in the current limiter 50A.

As previously mentioned, the voltage VB at the second point P2 may be up to 300V or more. To cope with this, the first transistor 621 is provided with a voltage clamp zener diode 6211 connected in parallel thereto. Therefore, the voltage between the source and the drain of the first transistor 621 is clamped to be equal to or lower than a prescribed voltage. Although in fig. 9 the clamper is shown as a single zener diode 6211, it may alternatively consist of a plurality of zener diodes 6211 connected in series. As the second transistor 622, a high withstand voltage transistor is used.

The first transistor 621 is turned off when its gate is fed with an H signal and turned on when its gate is fed with an L signal. That is, when the charging voltage on the start-up capacitor BC1 reaches the threshold voltage, the L signal from the comparator 613 is fed to the gate of the first transistor 621. This turns on the first transistor 621 so that current can now pass in the first transistor 621. However, as long as the second transistor 622 is turned off, no current flows.

The second transistor 622 is turned on when its gate is fed with an H signal and turned off when its gate is fed with an L signal. When the excitation control signal huin from the motor control unit MCU is an H signal, the input signal control circuit 40A feeds an L signal to the second transistor 622. When the excitation control signal huin from the motor control unit MCU is an L signal, the input signal control circuit 40A feeds an H signal to the second transistor 622. Further, when the excitation control signal huin is an L signal, the high-side transistor PT1 is turned off. Thus, when the high-side transistor PT1 is turned off, the second transistor 622 is turned on.

That is, in the level shift circuit 62, when the high-side transistor PT1 is turned off and additionally the charging voltage on the start-up capacitor BC1 is higher than the threshold voltage, a current flows in the current sense resistor 623. The current flowing through the current sense resistor 623 causes a voltage to be applied to the non-inverting input terminal of the comparator 624. Accordingly, the comparator 624 outputs the H signal as the current limit signal CLMT. This turns off the current limiting transistor 51 and the current charging the start-up capacitor BC1 is limited.

That is, the switching drive device 100A operates as follows. In the voltage sensing circuit 61, the charging voltage on the boot capacitor BC1 is sensed. In the input signal control circuit 40A, whether the high-side transistor PT1 is on or off is detected based on the excitation control signal huin. When the high-side transistor PT1 is turned off and additionally the charging voltage on the start-up capacitor BC1 is higher than the threshold voltage, the current charging the start-up capacitor BC1 is limited, so that the charging of the start-up capacitor BC1 is limited. It should be noted that the start-up capacitor BC1 is charged when the high-side transistor PT1 is turned off. Therefore, the current controller 60A limits the current to charge the boot capacitor BC1 when the charging voltage on the boot capacitor BC1 exceeds a predetermined value in a state where the boot capacitor BC1 is charged (being charged).

With the above configuration, it is possible to provide the switch driving device 100A that can make the bootstrap circuit BTC operate accurately while suppressing the overcharged state of the boot capacitor BC 1. Thus, it is possible to apply a sufficient voltage to the load (motor) with accurate timing and allow the load (motor) to operate accurately.

Fig. 10 is a diagram showing how the overcharged state of the boot capacitor BC1 is suppressed. In the graph depicting the charging voltage VBS on the start-up capacitor BC1, the solid line indicates the behavior in this embodiment, while the dashed line indicates the normal behavior.

As shown in fig. 10, in the switch driving device 100A of the present embodiment, when the current limit signal CLMT becomes high level, the current limit transistor 51 is turned off, and the charging current to the start-up capacitor BC1 is cut off. Therefore, the floating power supply voltage (i.e., the voltage VB at the second point P2) does not excessively rise.

As the comparator 613 in the voltage sensing circuit 61, a hysteresis comparator having two values, i.e., an overcharge sensing threshold value VthH and an overcharge sensing cancellation threshold value VhthL (where VthH > VthL), is preferably used as the threshold voltage to be compared with the charge voltage VBS on the start-up capacitor BC 1.

For example, the overcharge sensing threshold VthH may be set to a voltage value (e.g., 19.5V (between 18V minimum and 21V maximum, taking into account variations)) slightly below the absolute maximum rated gate voltage VGr (e.g., 22V in SiC-based MOSFETs) of each of the high-side transistors PT1, PT3, and PT 5. The overcharge sense elimination threshold VthL may be set to a voltage value (e.g., 19V (between a minimum value of 17.5V and a maximum value of 20.5V, taking into account the variation)) that is still below the overcharge detection threshold VhH. These arrangements allow the high-side transistor to be driven at or below its absolute maximum rated gate voltage.

< modified example >

Modified examples of the discussed embodiments will now be described with reference to the relevant drawings. Fig. 11 is a circuit diagram showing a modified example of the high-side driver circuit according to the present invention. The high-side driver circuit 10B shown in fig. 11 is a modified version of the high-side driver circuit 10A shown in fig. 9. Therefore, similar to the high-side driver circuit 10A, the high-side driver circuit 10B detects the high-side transistor PT1 to be off based on the excitation control signal huin, and limits the current to charge the start-up capacitor BC1 when the charging voltage on the start-up capacitor BC1 reaches the threshold voltage.

The high-side driver circuit 10B differs from the high-side driver circuit 10A as follows. As shown in fig. 11, the current limiter 50B includes an inverter 52, and the inverter 52 inverts an input signal fed to the current limiter 50B (i.e., an output signal of the delay 627) and then outputs the result. The output of inverter 52 is fed to the gate of current limiting transistor 51.

The voltage sensing circuit 61B in the current controller 60B includes resistors 611 and 612, as those in the voltage sensing circuit 61.

The output of the comparator 613 is fed through an inverter 618 to a delay circuit (RC time constant circuit) composed of a resistor 614 and a capacitor 615. The delay circuit delays the output signal of the inverter 618, thereby adjusting the timing of the current limit. The output of the delay circuit is fed through a buffer 619 to the gate of transistor 616. Buffer 619 may include two stages of inverters connected in series. Inverter 618 may be replaced with a buffer and buffer 619 may be replaced with an inverter. Any number of stages of inverters may be provided in the stages following the comparator 613 as long as the gate of the transistor 616 newly introduced here can be fed with a gate signal having an appropriate logic level. Transistor 616 is an N-type MOSFET. The drain of the transistor 616 is connected to the second point P2 via the resistor 617, or to a point at the same potential as the second point P2. The source of the transistor 616 is connected to the first point P1 or to a point having the same potential as the first point P1. Thus, when the L signal is output from the comparator 613, the transistor 616 is turned on so that a current passes in the resistor 617. This causes a voltage to appear between the gate and source of the first transistor 621 in the level shift circuit 62B, causing the first transistor 612 to be turned on. Accordingly, after the charging voltage on the start-up capacitor BC1 has reached the threshold voltage, the voltage sensing circuit 61B turns on the first transistor 621.

The input signal control circuit 40B includes a level shifter 41 and an inverter 42. The excitation control signal huin fed to the input signal control circuit 40B is, for example, a 0V/5V signal. The switch driving device 100B uses, for example, 18V as the control voltage VCC. Accordingly, the level shifter 41 raises the excitation control signal huin to adapt it to the control voltage VCC for the switch driving device 100B. Inverter 42 inverts the signal thus raised. The inverted signal, i.e., the inverted signal of the excitation control signal huin, is fed to the gate of the second transistor 622. Although shown in a simplified manner in fig. 11, the input signal control circuit 40B has a similar configuration to the input signal control circuit 40 (see fig. 5 mentioned earlier), and has a signal path through a schmitt buffer, then through a level shifter, then a pulse generator, so as to transmit the output of the level shifter to the inverter 42.

One end of the current sense resistor 623 of the level shift circuit 62B is connected to the ground terminal. An inverter 625 inverting the input signal and outputting it is connected to a connection point between the source of the second transistor 622 and the resistor 623, instead of the comparator 624. Further, a diode 6231 is connected in parallel with the resistor 623, which is directed forward from ground to the inverter 625. The output of inverter 625 is fed to level shifter 626 and the output of level shifter 626 is fed to delay 627. The output of the delay 627 is fed to the current limiter 50B.

For example, when an L-level signal as the excitation control signal huin is fed to the input signal control circuit 40B, the high-side transistor PT1 is turned off. Here, in the input signal control circuit 40B, although the level shifter 41 is ready to perform level shifting, since the input signal is at the L level, the L level thereof is held. The inverter 42 inverts the signal level so that the H-level signal is fed to the gate of the second transistor 622. This turns on the second transistor 622. When the first transistor 621 is turned on, a current flows in the resistor 623, and an H-level signal is fed to the inverter 625, and the inverter 625 then outputs an L-level signal. Although the level shifter 626 is ready to perform level shifting, since the input signal is at the L level, its L level is maintained. The signal is then delayed by a delay 627. A delay 627 is provided for canceling noise. As described above, the input signal control circuit 40B has a similar configuration to the input signal control circuit 40 (see fig. 5 mentioned earlier), and has a signal path through the schmitt buffer, then through the level shifter, then the pulse generator, so that the output of the level shifter is transmitted to the inverter 42.

The L-level output signal of the delay 627 is fed to the inverter 52 in the current limiter 50B. The L-level input signal is inverted by the inverter 52, so that the H-level output signal is fed to the gate of the current limiting transistor 51. This turns off the current limiting transistor 51, and thus stops the supply of the charging current to the starting capacitor BC 1.

In the switch driving device 100B, the use of a plurality of inverters helps to eliminate the influence of delay caused by parasitic capacitance in conductors, resistors, transistors, and the like. Therefore, the load (motor) can be controlled more finely.

Next, the time when the overcharge occurs will be described in addition with reference to fig. 12. Fig. 12 is a timing chart showing the timing of occurrence of overcharge describing the charge voltage VBS (solid line) and the motor current IM (broken line) on the start-up capacitor BC1, and is accompanied by a partial chart on a short time scale describing the excitation control signal huin, the gate-source voltage Vgs of the high-side transistor PT1, the voltage VS at the first point, and the charge voltage VBS.

As shown in fig. 12, at the start of overcharge, huin=l and vs=l. In view of this behavior, in the second embodiment (and its modified examples) described earlier, when it is sensed that the charging voltage on the boot capacitor BC1 is higher than the threshold voltage, the charging current to the boot capacitor BC1 is limited, and in addition, huin=l is also limited.

However, as will be clear from fig. 12, as a trigger for sensing the timing at which overcharge occurs, vs=l may be sensed instead of huin=l. As a modified example having such a design, a third embodiment will be presented below.

< third embodiment >

Another example of the switch driving device according to the present invention will now be described with reference to the related drawings. Fig. 13 is a circuit diagram showing another example of a high-side driver circuit used in the switch driving device according to the present invention. The high-side driver circuit 10C shown in fig. 13 includes a current controller 60C that senses the voltage VS at the first point P1, and is different from the high-side driver circuit 10B shown in fig. 11 in this respect. Another difference is that the input signal control circuit 40 does not output a signal fed to the gate of the second transistor 622 in the level shift circuit 62C. That is, the input signal control circuit 40 includes only a circuit that outputs a signal for driving the high-side gate driver 30. In other respects, the high-side driver circuit 10C has the same configuration as the high-side driver circuit 10B shown in fig. 11. Thus, substantially the same portions will be identified by the same reference numerals, and the description of the same portions will not be repeated.

Now, a description will be given of the overcharge of the start-up capacitor BC 1. As described above, by the regenerating operation of the U-phase coil MU, when the voltage VS at the first point P1 becomes a predetermined potential lower than the ground potential, the start capacitor BC1 is overcharged. To avoid this, in the switch driving device 100C, instead of sensing the input signal (excitation control signal huin), the voltage VS at the first point P1 is sensed to sense the occurrence timing of the overcharge of the start-up capacitor BC1, and the time when the voltage VS at the first point P1 becomes equal to the predetermined potential (low level) is taken as the timing of the occurrence of the overcharge. Then, when the voltage VS at the first point P1 becomes equal to the prescribed voltage (low level) and the charging voltage VBS on the boot capacitor BC1 reaches the threshold voltage in addition, the boot capacitor BC1 is judged to enter the overcharged state.

The reference voltage sensing circuit 63 senses the voltage VS at the first point P1. As shown in fig. 13, in a circuit connected between the first power supply PW1 or a point at the same potential as the first power supply PW1 and the first point P1 or a point at the same potential as the first point, a first resistor 631, a second resistor 632, and a diode 633 are connected in series in this order from the first power supply PW1 side. The cathode of the diode 633 is connected to the first point P1, or to a point at the same potential as the first point. The reference voltage sensing circuit 63 includes a transistor 634. Transistor 634 is a P-type MOSFET. The source of the transistor 634 is connected to a point at the same potential as the first power supply PW 1. The drain of the transistor 634 is connected to a ground terminal via a resistor 635 serving as a load.

The gate of the transistor 634 is connected to a connection point between the first resistor 631 and the second resistor 632. The junction between the drain of transistor 634 and resistor 635 is connected to the input of inverter 636. The output of the inverter 636 is connected to the input of the inverter 637, and the inverter 637 output is connected to the gate of the second transistor 622 in the level shift circuit 62C. The inverters 636 and 637 each output an output signal having a voltage level inverted from that of an input signal input thereto.

For example, when the voltage VS at the first point P1 is equal to or higher than the control voltage VCC from the first power supply PW1, no current flows in the diode 633. Therefore, no current flows into the first resistor 631 and the second resistor 632. Thus, the transistor 634 is turned off. As a result, the L-level signal is fed to the inverter 636, and the inverter 636 thus outputs the H-level signal. The H-level signal is fed to the inverter 637, and the L-level signal is fed to the gate of the second transistor 622. Thus, the second transistor 622 is turned off.

On the other hand, when the voltage VS at the first point P1 is lower than the control voltage VCC from the first power supply PW1, the current in the diode 633 flows to the first point P1. The current flows from the first power supply PW1 to the first resistor 631 and the second resistor 632. As a result of the current flowing in the first resistor 631, the end-to-end voltage thereon causes a voltage to be applied between the gate and the source of the transistor 634, and the transistor 634 is thus turned on. As a result, a current that has flowed in the transistor 634 flows in the resistor 635. Here, the H-level signal is fed to the inverter 637, which thus outputs the L-level signal. The L-level signal is fed to the inverter 637, and the H-level signal is fed to the gate of the second transistor 622. Thus, the second transistor 622 is turned on. Now, a state is reached in which an overcharged state can be sensed.

The gate-source voltage for turning on the transistor 634 is determined by the resistance value of the first resistor 631 and the value of the current flowing through the first resistor 631. The current passing in the first resistor 631 is determined by the combined resistance of the first resistor 631 and the second resistor 632 and the difference (VCC-VS) between the control voltage VCC from the first power supply PW1 and the voltage VS of the first point P1. The diode 633 also has an internal resistance, however, which is much lower than that of the first and second resistors 631 and 632, and thus is omitted. Therefore, adjusting the resistance values of the first resistor 631 and the second resistor 632 allows the transistor 634 to be turned on when the voltage VS at the first point P1 becomes a voltage at which overcharge is likely to occur.

Surge absorbing diodes 638 and 639 are connected between the gate and the drain of the transistor 634 and also between the gate and the source, respectively.

As described above, the current controller 60C in the switch driving device 100C senses the voltage VS at the first point P1 in the reference voltage sensing circuit 63. When the voltage VS becomes equal to a prescribed voltage lower than the ground voltage (the voltage VS when the starting capacitor BC1 enters the overcharged state) and furthermore when the charging voltage VBS on the starting capacitor BC1 reaches the threshold voltage, the current controller 60C judges that the starting capacitor BC1 enters the overcharged state and limits the charging current to the starting capacitor BC 1. Therefore, the boot capacitor BC1 can be reliably charged to a desired voltage, and can be more reliably prevented from entering an overcharged state.

In the second and third embodiments, the current controller 60B (60C) checks whether the start-up capacitor BC1 is in an overcharged state by checking the input signal huin or the voltage VS at the first point P1 and the charging voltage VBS on the start-up capacitor BC 1. As previously described, the start-up capacitor BC1 may enter an overcharged state when the high-side transistor PT1 and the low-side transistor PT2 are in mode 2. Thus, the current limiter 50 can also be controlled by sensing the gate signal HU for the high-side transistor PT1 and the gate signal LU for the low-side transistor PT2 and thereby sensing that they are in mode 2, i.e. by detecting that the high-side transistor PT1 is off and that the low-side transistor PT2 is off.

Finally, the pad arrangement in the high-side driver circuit 10 will be studied. Fig. 14 is a plan view showing an example of pad arrangement in the high-side driver circuit. As for the high-side driver circuit 10 in the first embodiment (fig. 5), the chip, pads, and wires thereof are indicated by solid lines. On the other hand, with the high-side driver circuits 10A to 10C in the second embodiment (fig. 9 and 11) and the third embodiment (fig. 13), the chips, pads, and wires thereof are indicated by broken lines.

As shown in fig. 14, on the surface of the high-side driver circuit 10, a plurality of pads (BVCC 1 to BVCC3, AVB1 to ABV3, DVB1 to DVB3, HIN1 to HIN3, AVCC, DVCC, ACOM, DCOM, VS1 to VS3, and HO1 to HO 3) are formed. These pads will now be described with reference also to the aforementioned fig. 2 and 7, when necessary.

The pads BVCC1 to BVCC3 are connected to anodes of the start diodes DiU, diV and DiW, respectively.

Both pads AVB1 and DVB1 are connected to the cathode of start-up diode DiU (i.e., to terminal Pn 2). Both pads AVB2 and DVB2 are connected to the cathode of start-up diode DiV (i.e., to terminal Pn 3). Pads ABV3 and DVB3 are both connected to the cathode of start-up diode DiW (i.e., to terminal Pn 4). Pads AVB1 through ABV3 are connected to analog system start-up power lines of different phases within the chip, respectively. On the other hand, the pads DVB1 to DVB3 are respectively connected to digital system start-up power supply lines of different phases within the chip.

The pads HIN1 to HIN3 are connected to terminals Pn5 to Pn7 (i.e., input terminals for excitation control signals huin, hvin, and hwin), respectively.

A plurality of pads AVCC are provided, which are all connected to the terminal Pn8 (i.e., to the input terminal of the control voltage VCC). The pad DVCC is also connected to the terminal Pn8. The pad AVCC is connected to an analog system control voltage line within the chip. On the other hand, the pad DVCC is connected to a digital system control voltage line within the chip.

The pads ACOM and DCOM are both connected to the terminal Pn9 (i.e., the terminal to which the ground potential is applied). The pad ACOM is connected to an analog system common power line within the chip. On the other hand, the pad DCOM is connected to a digital system common power line within the chip.

Pads VS1 and HO1 are connected to the source and gate of the high-side transistor PT1, respectively. Pads VS2 and HO2 are connected to the source and gate of the high-side transistor PT3, respectively. Pads VS3 and HO3 are connected to the source and gate of the high-side transistor PT5, respectively.

As shown in fig. 14, the high-side driver circuit 10 in the first embodiment and the high-side driver circuits 10A to 10C in the second and third embodiments have different circuit elements integrated together, and accordingly have different chip sizes. More specifically, in the left-right direction of the drawing, the high-side driver circuits 10A to 10C indicated by the broken lines have a greater length than the high-side driver circuit 10 indicated by the solid lines.

The arrangement of the respective pads is preferably adjusted so that the lengths of the wires respectively connected to the respective pads are within a given range, according to the above-described difference in chip size. For example, the optimized pad arrangement as shown in fig. 14 makes it possible to utilize existing packages that have been time tested, and thereby give the switch driving device enhanced reliability.

< other variants >

The various technical features disclosed herein may be implemented in any other way than the above-described embodiments, and many variations are allowed without departing from the spirit of the invention. That is, the above-described embodiments should be understood to be illustrative in every respect and not restrictive. The technical scope of the present invention is defined not by the description of the embodiments given above but by the appended claims, and should be construed to include any modifications that are made in the meaning and scope equivalent to those of the claims.

Industrial applicability

The switch driving device according to the present invention can be applied to, for example, a motor driver that supplies driving power to a motor provided with a coil.

Description of symbols

10. 10A, 10B, 10C high side driver circuit

20. Low side driver circuit

30. High side gate driver

40. 40A, 40B input signal control circuit

41. Level shifter

42. Inverter with a high-speed circuit

50. 50A, 50B current limiter

51. Current limiting transistor

52. Inverter with a high-speed circuit

60. 60A, 60B, 60C current controller

61. 61B voltage sensing circuit

62. 62B, 62C level shift circuit

63. Reference voltage sensing circuit

70. High withstand voltage level shift circuit

71. Transistor with a high-voltage power supply

72. Transistor with a high-voltage power supply

73. Resistor

74. Resistor

100. 100A, 100B and 100C switch driving device

301. Clamping circuit

401. Inverter with a high-speed circuit

402. Level shift circuit

403. Pulse generator

501. Transistor with a high-voltage power supply

502. Resistor

611. Resistor

612. Resistor

613. Comparator with a comparator circuit

614. Resistor

615. Capacitor with a capacitor body

616. Transistor with a high-voltage power supply

617. Resistor

618. Inverter with a high-speed circuit

619. Buffer device

621. First transistor

6211. Zener diode

622. Second transistor

6221. Diode

623. Resistor

6231. Diode

624. Comparator with a comparator circuit

6241. Diode

625. Inverter with a high-speed circuit

626. Level shifter

627. Delay device

631. First resistor

632. Second resistor

633. Diode

634. Transistor with a high-voltage power supply

635. Resistor

636. Inverter with a high-speed circuit

637. Inverter with a high-speed circuit

638. Diode

639. Diode

ACOM bonding pad

AVB1, AVB2, AVB3 bonding pad

AVCC bonding pad

BC1, BC2, BC3 starting capacitor

BD frame

BK1 input block

BKU U-phase block

BKV V-phase block

BKW W-phase block

BTC bootstrap circuit

BVCC1, BVCC2, BVCC3 bonding pad

BW wire

CLMT current limit signal

DCOM bonding pad

DRV driver circuit

DiU, diV, diW starting diode

DVB1, DVB2, DVB3 bonding pad

DVCC bonding pad

HIN1, HIN2, HIN3 bonding pad

HO1, HO2, HO3 bonding pad

HU, HV, HW drive signals

huin, hvin, hwin excitation control signal

IM motor current

LU, LV, LW drive signals

luin, lvin, lwin excitation control signal

M motor

MCU motor control unit

MMC motor driving device

MU U-phase coil

MV V-phase coil

MW W-phase coil

P1 first point

P2 second point

PB resin sealing member

PC11 pattern wiring

PC12 pattern wiring

PC13 pattern wiring

PC21 pattern wiring

PC22 pattern wiring

PC23 pattern wiring

Pkg encapsulation

PS power supply

PSW power supply switching circuit

PT1, PT3, PT5 high side transistors

PT2, PT4, PT6 low side transistors

PW1 first power supply

PW2 second power supply

Pn1 to Pn25 terminals

RESU, RESV, RESW current limiter region

Voltage at the second point of VB

VBS charging voltage

VCC control voltage

VDC drive voltage

Voltage at the first point of VS

VS1, VS2, VS3 bonding pad

Claims

1. A switch driving device, comprising:

a gate driver configured to operate by being fed with a driving voltage from the bootstrap circuit so as to drive the N-type semiconductor switching element;

a current limiter configured to limit a current flowing between an anode of a start-up diode included in the bootstrap circuit and a first power supply; and

a current controller configured to control operation of the current limiter,

wherein,

the current limiter includes a switch and a resistor connected in parallel between the anode of the start-up diode and the first power supply, and

the current controller is configured to sense a voltage of the first power source, the current limiter is configured to:

when the voltage of the first power supply is the first voltage, the switch is turned off, and

and when the voltage of the first power supply is a second voltage lower than the first voltage, the switch is turned on.

2. The switch driving device according to claim 1, wherein,

the current controller is configured to determine whether a start-up capacitor included in the bootstrap circuit is being charged and sense a charging voltage on the start-up capacitor, and

the current controller is configured to: the current limiter is driven when the start-up capacitor is being charged, the charging voltage on the start-up capacitor becoming higher than a threshold value.

3. The switch driving device according to claim 2, wherein,

the current controller is configured to: the charging voltage on the start-up capacitor is sensed based on an end-to-end voltage on the start-up capacitor or a divided voltage thereof.

4. The switch driving device according to claim 2, wherein,

the N-type semiconductor switching element is a high-side switching element arranged between the second power supply and the load to form a half-bridge output stage, an

The current controller is configured to: when the high-side switching element is turned off, it is judged that the start-up capacitor is being charged.

5. The switch driving device according to claim 4, wherein,

the current controller is configured to: the high-side switching element is driven by determining whether the high-side switching element is on or off by acquiring a drive signal fed from the outside.

6. The switch driving device according to claim 2, wherein,

The current controller is configured to: when the voltage is equal to or less than a threshold value, a voltage at a connection point between the high-side switching element and the load is sensed to determine that the start-up capacitor is being charged.

7. The switch driving device according to claim 1, wherein,

the current limiter is used as an element with a variable resistance value, and

the current limiter is configured to: the resistance value of the current limiter is increased when the voltage of the first power supply is the first voltage, and the resistance value of the current limiter is decreased when the voltage of the first power supply is the second voltage.

8. The switch driving device according to claim 1, wherein,

let the resistance value of the resistor be R1 and the resistance value of the switch be R2, R1R 2.

9. The switch driving device according to claim 1, further comprising:

an input signal control circuit configured to receive the excitation control signal, and

A level shift circuit configured to: is connected between the input signal control circuit and the gate driver.

10. The switch driving device according to claim 1, wherein,

the gate driver, the current limiter, and the current controller are formed in a single chip.

11. The switch driving device according to claim 1, further comprising:

a resin sealing member configured to: and sealing the switch driving device, the N-type semiconductor switching element, and the start diode.

12. The switch driving device according to claim 11, wherein,

the start diode is provided on a terminal inside the resin sealing member.

13. The switch driving device according to any one of claims 1 to 12, wherein,

the N-type semiconductor switching element employs a semiconductor made of silicon carbide (SiC).

14. The switch driving device according to any one of claims 1 to 12, wherein,

the load is a three-phase alternating current motor.