CN112003462A - Harmonic compensation method and device of PFC circuit and terminal equipment - Google Patents
Harmonic compensation method and device of PFC circuit and terminal equipment Download PDFInfo
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- CN112003462A CN112003462A CN202010864317.5A CN202010864317A CN112003462A CN 112003462 A CN112003462 A CN 112003462A CN 202010864317 A CN202010864317 A CN 202010864317A CN 112003462 A CN112003462 A CN 112003462A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/12—Arrangements for reducing harmonics from ac input or output
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention is suitable for the technical field of power electronics, and provides a harmonic compensation method, a harmonic compensation device and terminal equipment of a PFC circuit, wherein the method comprises the following steps: acquiring the current load rate of a target PFC circuit; determining a target compensation signal corresponding to the target PFC circuit under the current load rate based on the corresponding relation between the load rate and the compensation signal, wherein the target compensation signal is used for compensating current harmonics of the main control signal under the current load rate; superposing the target compensation signal with a master control signal of a target PFC circuit to obtain a target control signal; generating a PWM control signal according to the target control signal; and controls the target PFC circuit according to the PWM control signal. According to the method and the device, the original master control signal is compensated through the target compensation signal, so that the duty ratio of the PWM control signal is adjusted, the harmonic input of a circuit is reduced, the calculated amount is small and simple, the chip resource overhead is reduced, and the control stability is ensured.
Description
Technical Field
The invention belongs to the technical field of power electronics, and particularly relates to a harmonic compensation method and device of a PFC circuit and terminal equipment.
Background
In computer servers, communication power systems and special processing, large-capacity direct current power supplies are generally required, and when loads require the power supplies to supply thousands of amperes or even higher of current, the switching stress of switching tubes and rectifier diodes becomes very considerable if a single power supply is used. The interleaved parallel PFC (Power Factor Correction) circuit can reduce the effective values of input current ripple and output capacitor ripple current without increasing switching loss, improve the input current ripple frequency and improve the Power level of the circuit, so that the PFC circuit has high application value.
Because the input harmonic can seriously affect the quality of an electric signal when the PFC circuit is in a light-load state, the PFC circuit has strict requirements on the input harmonic in the light-load state. However, the inductance of the interleaved parallel PFC circuit in a light load state is usually in an intermittent continuous alternating state, so that the problem of overlarge input harmonic wave is caused.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method and an apparatus for compensating for a harmonic of a PFC circuit, and a terminal device, so as to solve the problem in the prior art that an input harmonic of the PFC circuit is too large.
A first aspect of an embodiment of the present invention provides a harmonic compensation method for a PFC circuit, including:
acquiring the current load rate of a target PFC circuit;
determining a target compensation signal corresponding to the target PFC circuit under the current load rate based on the corresponding relation between the load rate and the compensation signal, wherein the target compensation signal is used for compensating current harmonics of the main control signal under the current load rate;
superposing the target compensation signal and a master control signal of the target PFC circuit to obtain a target control signal;
generating a PWM control signal according to the target control signal; and controlling the target PFC circuit according to the PWM control signal.
A second aspect of an embodiment of the present invention provides a harmonic compensation apparatus for a PFC circuit, including:
the load rate acquisition module is used for acquiring the current load rate of the target PFC circuit;
the compensation signal acquisition module is used for determining a target compensation signal corresponding to the target PFC circuit under the current load rate based on the corresponding relation between the load rate and the compensation signal, wherein the target compensation signal is used for compensating current harmonics of the main control signal under the current load rate;
the control signal compensation module is used for superposing the target compensation signal and a main control signal of the target PFC circuit to obtain a target control signal;
the PWM control signal generation module is used for generating a PWM control signal according to the target control signal; and controlling the target PFC circuit according to the PWM control signal.
A third aspect of the embodiments of the present invention provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the harmonic compensation method of the PFC circuit as described above when executing the computer program.
A fourth aspect of embodiments of the present invention provides a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of the harmonic compensation method of the PFC circuit as described above.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: the embodiment firstly obtains the current load rate of a target PFC circuit; then determining a target compensation signal corresponding to the target PFC circuit under the current load rate based on the corresponding relation between the load rate and the compensation signal, wherein the target compensation signal is used for compensating current harmonics of the main control signal under the current load rate; then, superposing the target compensation signal with a master control signal of a target PFC circuit to obtain a target control signal; finally, generating a PWM control signal according to the target control signal; and controls the target PFC circuit according to the PWM control signal. According to the method and the device, the original master control signal is compensated through the target compensation signal, so that the duty ratio of the PWM signal is adjusted, the harmonic input of a circuit is reduced, the calculated amount is small and simple, the chip resource overhead is reduced, and the control stability is ensured.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic flowchart of a harmonic compensation method of a PFC circuit according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of an interleaved parallel PFC circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a harmonic compensation device of a PFC circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a terminal device according to an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
In one embodiment of the present invention, as shown in fig. 1, fig. 1 shows a flow of implementing harmonic compensation of a PFC circuit, and the process thereof is detailed as follows:
s101: acquiring the current load rate of a target PFC circuit;
s102: determining a target compensation signal corresponding to the target PFC circuit under the current load rate based on the corresponding relation between the load rate and the compensation signal, wherein the target compensation signal is used for compensating current harmonics of the main control signal under the current load rate;
s103: superposing the target compensation signal and a master control signal of the target PFC circuit to obtain a target control signal;
s104: generating a PWM control signal according to the target control signal; and controlling the target PFC circuit according to the PWM control signal.
The embodiment is suitable for controlling the PFC circuit, and the target PFC circuit comprises a single PFC circuit and a multi-path interleaving parallel PFC circuit.
As shown in fig. 2, fig. 2 shows a circuit structure of an interleaved PFC circuit, when the PFC circuit is in a light load state, the inductors L1 and L2 in the PFC circuit are in an intermittent and continuous alternating control state, which may generate a large current harmonic in the PFC circuit. Therefore, the PWM control signal needs to be adjusted to change the intermittent, continuous state of the inductors L1 and L2 in the PFC circuit.
In order to reduce the current harmonics of the target PFC circuit, the present embodiment compensates the main control signal, and generates the PWM control signal according to the compensated target control signal, thereby adjusting the duty ratio of the PWM control signal.
Specifically, the corresponding relationship between the load factor and the compensation signal is a relationship determined by data obtained in an open-loop control experiment. The target compensation signal corresponding to the current load rate is a compensation signal of which the current harmonic wave after the compensation signal compensation circuit is applied is smaller than a preset current harmonic wave threshold value. Preferably, the present embodiment uses the total distortion rate of the current harmonics as a quantifiable index of the current harmonics.
Based on the corresponding relation between the load rate and the compensation signal, the corresponding target compensation signal is directly searched according to the obtained current load rate of the target PFC circuit in the subsequent application process, the calculation is simple, the calculation amount is small, the compensation amount does not need to be calculated according to the real-time harmonic component in the control process, and therefore the stability of the control of the switching tube is improved.
In an embodiment, the implementation procedure of the harmonic compensation of the PFC circuit provided in this embodiment further includes:
s201: determining a target load interval of the target PFC circuit based on the structural parameters of the target PFC circuit;
s202: judging whether the current load rate of the target PFC circuit is within the target load interval or not;
s203: and if the current load rate of the target PFC circuit is within the target load interval, continuing to execute the step of determining a target compensation signal corresponding to the target PFC circuit under the current load rate based on the corresponding relation between the load rate and the compensation signal.
In this embodiment, the structural parameter of the target PFC circuit is the number of branches of the target PFC circuit, that is, the number of PFC units included in the target PFC circuit. The PFC circuit with the branch number has strict requirements on the input harmonic content in different load intervals.
Specifically, if the target PFC circuit is a single-path PFC circuit, the target load interval is selected from an interval having a load rate of 15% to 20%. If the target PFC circuit is a double-circuit, namely the double-circuit is connected in parallel in a staggered mode, the target load interval is selected from an interval with the load rate of 30% -40%, and the like, and the target load interval is determined according to the number of branches of the target PFC circuit.
In one embodiment, the target PFC circuit comprises an interleaved parallel PFC circuit, the target compensation signal comprising a single target compensation signal; the specific implementation process of S103 includes:
and superposing the single-path target compensation signal with a main control signal of a first path of PFC unit to obtain a target control signal of the first path of PFC unit, wherein the first path of PFC unit is any one path of PFC unit of the staggered parallel PFC circuit.
In this embodiment, the target compensation signal may act on the main control signals of each of the PFC units of the target PFC circuit, or may only compensate the main control signal of one of the PFC units. When the target compensation signal is only applied to one of the PFC units, the target compensation signal is a single-path target compensation signal, and when the target compensation signal is applied to all the PFC units of the target PFC circuit, the target compensation signal is a compensation signal corresponding to all the paths.
In an embodiment, the implementation procedure of the harmonic compensation of the PFC circuit provided in this embodiment further includes:
s301: acquiring a current load rate experimental value of a PFC test circuit;
s302: acquiring a target compensation signal corresponding to the current load factor experimental value based on a control experiment of the PFC test circuit, wherein the target compensation signal is a compensation signal corresponding to the situation that the current harmonic wave of the PFC test circuit is smaller than a preset current harmonic wave;
s303: and updating the current load rate experimental value of the PFC test circuit, and repeatedly executing the process of acquiring the target compensation signal corresponding to the current load rate experimental value until the acquisition of the target compensation signals of all the load rate experimental values is completed, so as to obtain the corresponding relation between the load rate and the compensation signals.
In this embodiment, a load rate set is first set, where the load rate set includes a plurality of load rate experimental values, and the load rate experimental values may be selected from a target load interval. And then selecting the load rate experimental values according to a preset sequence to carry out an open-loop control test of the parallel staggered PFC test circuit. The preset sequence may be from small to large, or from large to small.
Specifically, the specific implementation flow of S302 includes:
the method comprises the following steps: and setting compensation values of a plurality of compensation signals, and selecting the compensation signals according to a preset sequence. After the compensation signal is selected, the current compensation signal is used for compensating the master control signal to obtain a target control signal, a current PWM control signal is generated according to the target control signal, the PFC test circuit is controlled according to the current PWM control signal, and the current harmonic wave total distortion rate of the PFC test circuit under the action of the current PWM control signal is obtained;
step two: judging whether the total current harmonic distortion rate is smaller than a preset total current harmonic distortion rate or not;
step three: if the current harmonic total distortion rate is smaller than the preset current harmonic total distortion rate, taking the current compensation signal as a target compensation signal corresponding to the current load rate experimental value;
step four: and if the total current harmonic distortion rate is greater than or equal to the preset total current harmonic distortion rate, selecting a next compensation value according to a preset sequence, and repeatedly executing the steps from the first step to the fourth step until the total current harmonic distortion rate corresponding to the updated compensation signal is less than the preset total current harmonic distortion rate.
Preferably, the preset current harmonic total distortion rate may be set to a value of 3%, 5%, 8%, or the like, or an interval range thereof.
Preferably, the present embodiment takes the third, fifth and seventh harmonics as examples, and calculates the total distortion rate of the current harmonics of the third, fifth and seventh harmonics.
After the target compensation signal of the current load rate experimental value is obtained, selecting the next load rate experimental value from the load rate set according to the preset sequence, and repeatedly executing S301-S303 until the target compensation signals of all the load rate experimental values are obtained, so as to obtain the corresponding relation between the load rate and the compensation signals.
In this embodiment, if the total current harmonic distortion rate corresponding to the PFC test circuit after compensation of all the compensation signals is greater than or equal to the preset total current harmonic distortion rate after the experiments corresponding to all the compensation signals of the current load factor experimental value are completed, the compensation signal with the minimum total current harmonic distortion rate of the compensated circuit in the set of experiments is selected as the target compensation signal of the current load factor experimental value.
In an embodiment, the implementation procedure of the harmonic compensation of the PFC circuit provided in this embodiment further includes:
and performing curve fitting on each load rate experimental value of the PFC test circuit and the corresponding target compensation signal to obtain a load rate-compensation signal fitting curve.
Accordingly, the specific implementation flow of S102 in fig. 1 includes:
and determining a target compensation signal corresponding to the target PFC circuit under the current load rate based on the load rate-compensation signal fitting curve.
In this embodiment, the corresponding relationship between the load factor and the compensation signal includes a load factor-compensation signal comparison table and a load factor-compensation signal fitting curve.
When the corresponding relation between the load rate and the compensation signal is a load rate-compensation signal comparison table, more load rate experimental values can be set in the load rate set in order to ensure the accuracy of harmonic compensation; if the corresponding relationship between the load factor and the compensation signal is a load factor-compensation signal fitting curve, fewer load factor experimental values can be set in the load factor set.
In this embodiment, when the corresponding relationship between the load rate and the compensation signal is the load rate-compensation signal comparison table, because the load rate of the circuit in practical application may be inconsistent with the load rate selected in the test process, after determining each load rate experimental value and the corresponding target compensation signal of the PFC test circuit, the present embodiment establishes the load rate subinterval of each load rate experimental value according to the preset value range, thereby implementing the association between the load rate subinterval and the target compensation signal, and forming the load rate subinterval-compensation signal comparison table.
Correspondingly, in practical application, after the current load rate of the target PFC circuit is determined, the load rate subinterval where the current load rate is located is searched, and the target compensation signal corresponding to the target PFC circuit under the current load rate is determined according to the load rate subinterval where the current load rate is located and the load rate subinterval-compensation signal comparison table, so that input harmonic compensation of the target PFC circuit is achieved.
In an embodiment of the present invention, on the basis of compensating the main control signal by the compensation signal and adjusting the duty ratio of the PWM control signal, in order to further improve the current harmonics of the PFC circuit, the embodiment may further reduce the current harmonics of the PFC circuit by adjusting the switching frequency of the PWM control signal.
Specifically, a corresponding relationship between the load rate and the carrier frequency is obtained based on the PFC control test, and then the carrier frequency corresponding to the target PFC circuit at the current load rate is obtained based on the corresponding relationship between the load rate and the carrier frequency. And superposing the target compensation signal and the main control signal to obtain a target control signal, generating a modulation signal according to the target control signal, and superposing the modulation signal and the obtained carrier to generate a PWM control signal.
By the method, the duty ratio and the switching frequency of the PWM control signal can be adjusted simultaneously, so that the accuracy of harmonic compensation is further improved.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
In one embodiment, as shown in fig. 3, fig. 3 shows a structure of a harmonic compensation apparatus 100 of a PFC circuit provided in this embodiment, which includes:
a load rate obtaining module 110, configured to obtain a current load rate of the target PFC circuit;
a compensation signal obtaining module 120, configured to determine, based on a corresponding relationship between a load rate and a compensation signal, a target compensation signal corresponding to the target PFC circuit at a current load rate, where the target compensation signal is used to compensate a current harmonic of the main control signal at the current load rate;
a control signal compensation module 130, configured to superimpose the target compensation signal and a main control signal of the target PFC circuit to obtain a target control signal;
a PWM control signal generation module 140, configured to generate a PWM control signal according to the target control signal; and controlling the target PFC circuit according to the PWM control signal.
In an embodiment, the structure of the harmonic compensation apparatus 100 of the PFC circuit provided in this embodiment further includes:
a target load interval obtaining module, configured to determine a target load interval of the target PFC circuit based on a structural parameter of the target PFC circuit;
the load rate judging module is used for judging whether the current load rate of the target PFC circuit is within the target load interval or not;
and the execution judging module is used for continuously executing the step of determining the target compensation signal corresponding to the target PFC circuit under the current load rate based on the corresponding relation between the load rate and the compensation signal if the current load rate of the target PFC circuit is within the target load interval.
In one embodiment, the PFC circuit comprises an interleaved parallel PFC circuit, the target compensation signal comprising a single target compensation signal; the control signal compensation module includes:
and superposing the single-path target compensation signal with a main control signal of a first path of PFC unit to obtain a target control signal of the first path of PFC unit, wherein the first path of PFC unit is any one path of PFC unit of the staggered parallel PFC circuit.
In an embodiment, the structure of the harmonic compensation apparatus 100 of the PFC circuit provided in this embodiment further includes:
the load rate experimental value acquisition module is used for acquiring the current load rate experimental value of the PFC test circuit;
a target compensation signal obtaining module, configured to obtain a target compensation signal corresponding to the current load factor experimental value based on a control experiment of the PFC test circuit, where the target compensation signal is a compensation signal corresponding to a case where a current harmonic of the PFC test circuit is smaller than a preset current harmonic;
and the cyclic updating module is used for updating the current load rate experimental value of the PFC experimental circuit and repeatedly executing the process of acquiring the target compensation signal corresponding to the current load rate experimental value until the acquisition of the target compensation signals of all the load rate experimental values is completed, so as to obtain the corresponding relation between the load rate and the compensation signal.
In an embodiment, the structure of the harmonic compensation apparatus 100 of the PFC circuit provided in this embodiment further includes: and the curve fitting module is used for performing curve fitting on each load rate experimental value of the PFC test circuit and the corresponding target compensation signal to obtain a load rate-compensation signal fitting curve.
Accordingly, the compensation signal obtaining module 120 includes: and determining a target compensation signal corresponding to the target PFC circuit under the current load rate based on the load rate-compensation signal fitting curve.
Fig. 4 is a schematic diagram of a terminal device according to an embodiment of the present invention. As shown in fig. 4, the terminal device 4 of this embodiment includes: a processor 40, a memory 41 and a computer program 42 stored in said memory 41 and executable on said processor 40. The processor 40, when executing the computer program 42, implements the steps in the above-described harmonic compensation method embodiments of the respective PFC circuits, such as the steps 101 to 104 shown in fig. 1. Alternatively, the processor 40, when executing the computer program 42, implements the functions of the modules/units in the above-mentioned device embodiments, such as the functions of the modules 110 to 140 shown in fig. 3.
The computer program 42 may be partitioned into one or more modules/units that are stored in the memory 41 and executed by the processor 40 to implement the present invention. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution process of the computer program 42 in the terminal device 4.
The terminal device 4 may be a desktop computer, a notebook, a palm computer, a cloud server, or other computing devices. The terminal device may include, but is not limited to, a processor 40, a memory 41. Those skilled in the art will appreciate that fig. 4 is merely an example of a terminal device 4 and does not constitute a limitation of terminal device 4 and may include more or fewer components than shown, or some components may be combined, or different components, e.g., the terminal device may also include input-output devices, network access devices, buses, etc.
The Processor 40 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 41 may be an internal storage unit of the terminal device 4, such as a hard disk or a memory of the terminal device 4. The memory 41 may also be an external storage device of the terminal device 4, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are provided on the terminal device 4. Further, the memory 41 may also include both an internal storage unit and an external storage device of the terminal device 4. The memory 41 is used for storing the computer program and other programs and data required by the terminal device. The memory 41 may also be used to temporarily store data that has been output or is to be output.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other ways. For example, the above-described embodiments of the apparatus/terminal device are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow of the method according to the embodiments of the present invention may also be implemented by a computer program, which may be stored in a computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method embodiments may be implemented. . Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A method of harmonic compensation in a PFC circuit, comprising:
acquiring the current load rate of a target PFC circuit;
determining a target compensation signal corresponding to the target PFC circuit under the current load rate based on the corresponding relation between the load rate and the compensation signal, wherein the target compensation signal is used for compensating current harmonics of the main control signal under the current load rate;
superposing the target compensation signal and a master control signal of the target PFC circuit to obtain a target control signal;
generating a PWM control signal according to the target control signal; and controlling the target PFC circuit according to the PWM control signal.
2. The method of harmonic compensation in a PFC circuit of claim 1, wherein prior to the determining the target compensation signal for the target PFC circuit at the current load rate based on the load rate versus compensation signal correspondence, the method further comprises:
determining a target load interval of the target PFC circuit based on the structural parameters of the target PFC circuit;
judging whether the current load rate of the target PFC circuit is within the target load interval or not;
and if the current load rate of the target PFC circuit is within the target load interval, continuing to execute the step of determining a target compensation signal corresponding to the target PFC circuit under the current load rate based on the corresponding relation between the load rate and the compensation signal.
3. The method of harmonic compensation in a PFC circuit of claim 1, wherein the target PFC circuit comprises an interleaved parallel PFC circuit, the target compensation signal comprising a single target compensation signal;
the superimposing the target compensation signal and the main control signal of the target PFC circuit to obtain a target control signal includes:
and superposing the single-path target compensation signal with a main control signal of a first path of PFC unit to obtain a target control signal of the first path of PFC unit, wherein the first path of PFC unit is any one path of PFC unit of the staggered parallel PFC circuit.
4. The method of harmonic compensation in a PFC circuit of claim 1, wherein prior to the obtaining the current load rating of the target PFC circuit, the method further comprises:
acquiring a current load rate experimental value of a PFC test circuit;
acquiring a target compensation signal corresponding to the current load factor experimental value based on a control experiment of the PFC test circuit, wherein the target compensation signal is a compensation signal corresponding to the situation that the current harmonic wave of the PFC test circuit is smaller than a preset current harmonic wave;
and updating the current load rate experimental value of the PFC test circuit, and repeatedly executing the process of acquiring the target compensation signal corresponding to the current load rate experimental value until the acquisition of the target compensation signals of all the load rate experimental values is completed, so as to obtain the corresponding relation between the load rate and the compensation signals.
5. The method of harmonic compensation in a PFC circuit of claim 4, further comprising:
performing curve fitting on each load rate experimental value of the PFC test circuit and the corresponding target compensation signal to obtain a load rate-compensation signal fitting curve;
correspondingly, the determining a target compensation signal corresponding to the target PFC circuit at the current load rate based on the corresponding relationship between the load rate and the compensation signal includes:
and determining a target compensation signal corresponding to the target PFC circuit under the current load rate based on the load rate-compensation signal fitting curve.
6. A harmonic compensation apparatus for a PFC circuit, comprising:
the load rate acquisition module is used for acquiring the current load rate of the target PFC circuit;
the compensation signal acquisition module is used for determining a target compensation signal corresponding to the target PFC circuit under the current load rate based on the corresponding relation between the load rate and the compensation signal, wherein the target compensation signal is used for compensating current harmonics of the main control signal under the current load rate;
the control signal compensation module is used for superposing the target compensation signal and a main control signal of the target PFC circuit to obtain a target control signal;
the PWM control signal generation module is used for generating a PWM control signal according to the target control signal; and controlling the target PFC circuit according to the PWM control signal.
7. The harmonic compensation apparatus of a PFC circuit of claim 6, the apparatus further comprising:
a target load interval obtaining module, configured to determine a target load interval of the target PFC circuit based on a structural parameter of the target PFC circuit;
the load rate judging module is used for judging whether the current load rate of the target PFC circuit is within the target load interval or not;
and the execution judging module is used for continuously executing the step of determining the target compensation signal corresponding to the target PFC circuit under the current load rate based on the corresponding relation between the load rate and the compensation signal if the current load rate of the target PFC circuit is within the target load interval.
8. The harmonic compensation apparatus of the PFC circuit of claim 6, wherein the PFC circuit comprises an interleaved parallel PFC circuit, the target compensation signal comprising a single target compensation signal;
the control signal compensation module includes:
and superposing the single-path target compensation signal with a main control signal of a first path of PFC unit to obtain a target control signal of the first path of PFC unit, wherein the first path of PFC unit is any one path of PFC unit of the staggered parallel PFC circuit.
9. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any of claims 1 to 5 when executing the computer program.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 5.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112688544A (en) * | 2020-12-28 | 2021-04-20 | 漳州科华技术有限责任公司 | Harmonic compensation method and device of inverter circuit and terminal equipment |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080310201A1 (en) * | 2007-06-15 | 2008-12-18 | The Regents Of The University Of Colorado | Digital Power Factor Correction |
| US8098505B1 (en) * | 2009-07-20 | 2012-01-17 | Fairchild Semiconductor Corporation | Phase management for interleaved power factor correction |
| CN102497700A (en) * | 2011-12-05 | 2012-06-13 | 北方工业大学 | Power factor correction method for LED (light-emitting diode) lighting |
| US20130076317A1 (en) * | 2011-09-22 | 2013-03-28 | Chia-An YEH | Power factor control circuit and power factor control method |
| US20160079868A1 (en) * | 2014-09-11 | 2016-03-17 | Acbel Polytech Inc. | Power supply and method for compensating low-frequency output voltage ripple thereof |
| CN106787668A (en) * | 2015-11-20 | 2017-05-31 | 南京理工大学 | A kind of power factor correcting converter of loading range wide |
| CN106849639A (en) * | 2017-03-20 | 2017-06-13 | 矽力杰半导体技术(杭州)有限公司 | Circuit of power factor correction, control method and controller |
-
2020
- 2020-08-25 CN CN202010864317.5A patent/CN112003462B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080310201A1 (en) * | 2007-06-15 | 2008-12-18 | The Regents Of The University Of Colorado | Digital Power Factor Correction |
| US8098505B1 (en) * | 2009-07-20 | 2012-01-17 | Fairchild Semiconductor Corporation | Phase management for interleaved power factor correction |
| US20130076317A1 (en) * | 2011-09-22 | 2013-03-28 | Chia-An YEH | Power factor control circuit and power factor control method |
| CN102497700A (en) * | 2011-12-05 | 2012-06-13 | 北方工业大学 | Power factor correction method for LED (light-emitting diode) lighting |
| US20160079868A1 (en) * | 2014-09-11 | 2016-03-17 | Acbel Polytech Inc. | Power supply and method for compensating low-frequency output voltage ripple thereof |
| CN106787668A (en) * | 2015-11-20 | 2017-05-31 | 南京理工大学 | A kind of power factor correcting converter of loading range wide |
| CN106849639A (en) * | 2017-03-20 | 2017-06-13 | 矽力杰半导体技术(杭州)有限公司 | Circuit of power factor correction, control method and controller |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112688544A (en) * | 2020-12-28 | 2021-04-20 | 漳州科华技术有限责任公司 | Harmonic compensation method and device of inverter circuit and terminal equipment |
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