CN112688544A - Harmonic compensation method and device of inverter circuit and terminal equipment - Google Patents
Harmonic compensation method and device of inverter circuit and terminal equipment Download PDFInfo
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Abstract
The invention is suitable for the technical field of power electronics, and provides a harmonic compensation method, a harmonic compensation device and terminal equipment of an inverter circuit, wherein the method comprises the following steps: acquiring monitoring data of a target inverter circuit in a first time interval, wherein the first time interval is the time interval in which the value of a current signal is zero; determining a target limit value corresponding to the monitoring data according to the monitoring data and the monitoring data-limit value corresponding relation; and generating a PWM control signal based on the carrier wave, the initial modulation wave and the target limit value of the target inverter circuit, wherein the PWM control signal is used for controlling the target inverter circuit to compensate the current harmonic wave of the target inverter circuit in the first time interval. The harmonic compensation method of the inverter circuit can determine the target limit value according to the dynamic change adaptability of the target inverter circuit monitoring data, thereby effectively performing harmonic compensation on the inverter circuit on the premise of not needing to perform large-scale calculation and improving the efficiency of harmonic compensation.
Description
Technical Field
The invention belongs to the technical field of power electronics, and particularly relates to a harmonic compensation method and device for an inverter circuit and terminal equipment.
Background
In the inverter circuit, a carrier wave and a modulation wave output by a control loop are modulated to generate a PWM control signal, and the PWM control signal is used for controlling a switch tube. When the current value of the current flowing through the switching tube is close to zero, harmonic interference is obvious, and the current value is increased or reduced sharply, namely the current is distorted.
When harmonic compensation is performed on current output by an inverter circuit, a commonly used method is to perform harmonic compensation by using a control algorithm, however, the control algorithm can only effectively compensate low-order harmonics, and when a large proportion of higher harmonics exist, the conventional harmonic compensation method has a poor effect.
Disclosure of Invention
In view of this, embodiments of the present invention provide a harmonic compensation method and apparatus for an inverter circuit, and a terminal device, so as to solve the problem in the prior art that a higher harmonic compensation effect in the inverter circuit is not good.
A first aspect of an embodiment of the present invention provides a harmonic compensation method for an inverter circuit, including:
acquiring monitoring data of a target inverter circuit in a first time interval; the first time interval is a time interval in which the value of the current signal is zero; the current signal is a current signal output by a target inverter circuit;
determining a target limit value corresponding to the monitoring data according to the monitoring data and the monitoring data-limit value corresponding relation;
generating a PWM control signal based on a carrier wave of the target inverter circuit, an initial modulation wave and the target limit value; the PWM control signal is used for controlling the target inverter circuit to compensate current harmonics of the target inverter circuit in a first time interval.
A second aspect of an embodiment of the present invention provides a harmonic compensation apparatus for an inverter circuit, including:
the monitoring data acquisition module is used for acquiring monitoring data of the target inverter circuit in a first time interval; the first time interval is the time interval of the moment when the value of the current signal is zero, and the current signal is the current signal output by the target inverter circuit;
a target limit value obtaining module, configured to determine a target limit value corresponding to the harmonic component data according to the monitoring data and a monitoring data-limit value correspondence;
the PWM control signal generation module is used for calculating a carrier wave, an initial modulation wave and the target limit value of the target inverter circuit to generate a PWM control signal; the PWM control signal is used for controlling the target inverter circuit to compensate current harmonics of the target inverter circuit.
A third aspect of an embodiment of the present invention provides a terminal device, including: memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the steps of the method as described above are implemented when the processor executes the computer program.
A fourth aspect of the embodiments of the present invention provides a computer-readable storage medium, which stores a computer program, characterized in that, when the computer program is executed by a processor, the computer program implements the steps of the method as described above.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: the embodiment of the invention provides a harmonic compensation method, a harmonic compensation device and terminal equipment of an inverter circuit, wherein the method comprises the following steps: acquiring monitoring data of a target inverter circuit in a first time interval, wherein the first time interval is the time interval in which the value of a current signal is zero; determining a target limit value corresponding to the monitoring data according to the monitoring data and the monitoring data-limit value corresponding relation; and generating a PWM control signal based on the carrier wave, the initial modulation wave and the target limit value of the target inverter circuit, wherein the PWM control signal is used for controlling the target inverter circuit to compensate the current harmonic wave of the target inverter circuit in the first time interval. The harmonic compensation method of the inverter circuit can determine the target limit value according to the dynamic change adaptability of the target inverter circuit monitoring data, thereby effectively performing harmonic compensation on the inverter circuit on the premise of not needing to perform large-scale calculation and improving the efficiency of harmonic compensation.
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In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic flow chart illustrating an implementation of a harmonic compensation method for an inverter circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating the effect of a harmonic compensation method of an inverter circuit in the prior art;
fig. 3 is a schematic diagram of a target modulation wave in a harmonic compensation method of an inverter circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating an effect of a harmonic compensation method of an inverter circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a harmonic compensation device of an inverter circuit according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a terminal device according to an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Referring to fig. 1, an embodiment of the present invention provides a harmonic compensation method for an inverter circuit, including:
s101: acquiring monitoring data of a target inverter circuit in a first time interval; the first time interval is a time interval in which the value of the current signal is zero, and the current signal is a current signal output by the target inverter circuit.
Optionally, a time when the value of the current signal is zero is used as a reference point, and a sum of an interval of a preset time length before the reference point and an interval of a preset time length after the reference point is a first time interval.
Fig. 2 shows the effect of the harmonic compensation method of the inverter circuit in the prior art, and referring to fig. 2, the current output by the target inverter circuit is not a standard sine wave due to the interference of harmonics, but a significant distortion occurs at a portion where the current value is close to zero, which is shown as an excessively large slope of the current curve. For the low harmonics, the compensation method commonly used at present is calculation compensation, however, for the high harmonics, such as 13-15 harmonics, the calculation amount of calculation compensation is too large to be practically implemented.
Specifically, the slope of the current signal is directly controlled by the duty ratio of the PWM control signal, that is, at a position where the current value is close to zero, the duty ratio of the corresponding PWM control signal reaches a maximum value.
In this embodiment, since the current signal is severely interfered by the harmonic at the portion where the current value is close to zero, the pertinence of the harmonic compensation can be enhanced by selecting the first time interval as the target of monitoring and compensation, and meanwhile, only the monitoring data in the first time interval is acquired, so that the calculation amount of the harmonic compensation can be further reduced.
S102: determining a target limit value corresponding to the monitoring data according to the monitoring data and the monitoring data-limit value corresponding relation;
in this embodiment, the target limit values corresponding to different monitoring data are different, the target limit value corresponding to the monitoring data is determined according to the monitoring data and the monitoring data-limit value correspondence, so that the effect of harmonic compensation can be improved, the corresponding target limit value is adjusted in time according to the change of the monitoring data, and the adaptability of harmonic compensation is increased.
S103: generating a PWM control signal based on a carrier wave of the target inverter circuit, an initial modulation wave and the target limit value; the PWM control signal is used for controlling the target inverter circuit to compensate current harmonics of the target inverter circuit in a first time interval.
The harmonic compensation method for the inverter circuit according to the present embodiment performs harmonic compensation only for a time interval in which the value of the current signal is near zero, and can improve the pertinence of harmonic compensation on the premise of reducing the calculation amount.
In this embodiment, before S103, the method further includes:
an initial modulation wave and a carrier wave are acquired.
Optionally, the initial modulation wave is generated by a control loop of the target inverter circuit.
In order to effectively compensate the current harmonics in the inverter circuit, the present embodiment performs amplitude limiting on the initial modulation wave in the target inverter circuit or performs limit value adjustment on the duty ratio of the PWM control signal, so as to limit the harmonics of the current curve near zero in the current value, avoid spike-like distortion, and reduce the influence of the harmonics.
The inverter circuit harmonic compensation method provided by the embodiment of the invention can dynamically adjust the corresponding target limit value according to the current monitoring data of the target inverter circuit without carrying out large amount of calculation, thereby simplifying the harmonic compensation process and improving the harmonic compensation effect.
In one embodiment of the present invention, the monitoring data-limit value correspondence includes a monitoring data-modulation wave limit value correspondence, and the target limit value includes a modulation wave target limit value;
s103 includes:
s201: carrying out amplitude limiting on the initial modulation wave based on the modulation wave target amplitude limiting value to generate a target modulation wave;
s202: and modulating the carrier wave and the target modulation wave to generate the PWM control signal.
Fig. 3 is a schematic diagram illustrating a target modulation wave in a harmonic compensation method of an inverter circuit according to an embodiment of the present invention. Referring to fig. 3, after the amplitude of the initial modulation wave is limited, the amplitude of the target modulation wave is less than or equal to the target amplitude limit value. Fig. 4 is a schematic diagram illustrating an effect of the harmonic compensation method of the inverter circuit according to the embodiment of the present invention. The maximum values of the modulation wave in fig. 3 correspond to the zero points of the current flowing through the switching tube in the target inverter circuit in fig. 4. In the embodiment, the amplitude limitation of the modulation wave can reduce the duty ratio of the PWM control signal when the current of the switching tube is near the zero point, thereby reducing the change rate of the current of the switching tube near the zero point and reducing the interference of higher harmonics.
As can be seen from comparing fig. 2 and fig. 4, the harmonic compensation method of the inverter circuit according to the embodiment of the present invention can effectively implement harmonic compensation and reduce current distortion.
In one embodiment of the invention, the monitored data-limit correspondence comprises a monitored data-duty cycle limit correspondence, and the target limit comprises a duty cycle target limit;
s103 includes:
s301: modulating the carrier wave and the initial modulation wave to generate an initial PWM control signal;
s302: and adjusting the initial PWM control signal according to the duty ratio target limit value to generate the PWM control signal.
In one embodiment of the present invention, S302 includes:
acquiring the duty ratio of the initial PWM control signal in each carrier period;
limiting the duty ratio of the period to be adjusted in the initial PWM control signal by adopting the target limit value of the duty ratio to generate the PWM control signal; and the period to be adjusted is a carrier period of which the duty ratio in the initial PWM control signal is greater than the target limit value of the duty ratio.
Optionally, the duty ratio target limit is often adopted to limit the duty ratio of the period to be adjusted in the initial PWM control signal, and generating the PWM control signal includes:
multiplying the duration of the carrier period by the target limit value of the duty ratio, and calculating to obtain the high-level duration limit value of the PWM control signal in one carrier period;
acquiring an initial PWM control signal in a first period to be adjusted; the first period to be adjusted is any period to be adjusted.
And setting the high-level signal out of the high-level duration limit value in the initial PWM control signal in the first period to be adjusted to zero, so that the duty ratio of the initial PWM control signal in the first period to be adjusted is adjusted to be the duty ratio target limit value.
And repeating the steps to adjust the initial PWM control signals in all the periods to be adjusted to generate the PWM control signals.
According to the harmonic compensation method of the inverter circuit, the duty ratio of the PWM control signal is limited within the range smaller than or equal to the target limit value of the duty ratio through the steps, so that the problem of too fast current acceleration caused by too large duty ratio is avoided, and the influence of higher harmonics is reduced.
In an embodiment of the present invention, before S101, the method further includes:
s401: acquiring at least one test monitoring data in the test inverter circuit; the structure of the test inverter circuit is the same as that of the target inverter circuit;
s402: carrying out optimization test on each test monitoring data in the test inverter circuit to obtain an optimal limit value corresponding to each test monitoring data;
s403: and generating the monitoring data-limit value corresponding relation according to the optimal limit value corresponding to each test monitoring data.
Specifically, the optimizing test comprises a modulating wave amplitude limiting value optimizing test and a duty ratio limiting value optimizing test, the corresponding relation between the monitoring data and the modulating wave amplitude limiting value is determined through the modulating wave amplitude limiting value optimizing test, and the corresponding relation between the monitoring data and the duty ratio limiting value is determined through the duty ratio limiting value optimizing test.
In this embodiment, S402 includes:
when the monitoring data in the test inverter circuit is first monitoring data, adjusting the limit values of the test inverter circuit in sequence by preset step length, and simultaneously acquiring the current harmonic distortion rate of the test inverter circuit corresponding to each limit value;
selecting the limit value with the minimum current harmonic distortion rate in the limit values corresponding to the first monitoring data as the optimal limit value corresponding to the first monitoring data;
and determining the optimal limit value corresponding to each monitoring data according to the steps.
Specifically, adjusting the limit value of the test inverter circuit in sequence by a preset step length specifically includes:
and sequentially adjusting the limit values of the test inverter circuit in a first limit value interval according to a first preset step length from small to large.
Optionally, after the harmonic distortion rate corresponding to each limit value corresponding to the first monitoring data is obtained, a second limit value interval is intercepted from the first limit value interval according to each harmonic distortion rate, the limit values of the test inverter circuit are sequentially adjusted in the second interval by a second preset step length, and meanwhile, the current harmonic distortion rate of the test inverter circuit corresponding to each limit value in the second limit value interval is obtained. The second limit interval is a limit interval in which the harmonic distortion rate in the first limit interval is smaller than a preset threshold; the second is then compensated for a step size smaller than the first preset step size. Illustratively, the second preset step size is one tenth of the first preset step size.
Through the steps, the calculation amount can be reduced on the basis of ensuring the accuracy of the optimal limit value, and the calculation efficiency of the optimal limit value is improved.
In the present embodiment, S403 includes:
and dividing the monitoring data into a plurality of monitoring data intervals according to the distribution of the test monitoring data, and matching corresponding optimal limit values for each monitoring data interval so as to obtain the monitoring data-limit value corresponding relation.
Accordingly, S102: the method comprises the following steps:
and determining a monitoring data interval corresponding to the current monitoring data so as to determine an optimal limit value corresponding to the current monitoring data, and taking the optimal limit value as a target limit value corresponding to the current monitoring data.
In one embodiment of the present invention, the monitoring data includes harmonic component data in a current signal output by a target inverter circuit, and the harmonic component data includes a harmonic content rate corresponding to each harmonic; the monitoring data-limit value corresponding relation comprises a harmonic component-limit value corresponding relation;
s102 includes:
and determining a target limit value corresponding to the harmonic component data according to the harmonic component data and the harmonic component-limit value corresponding relation.
In the present embodiment, the harmonic component data includes a main harmonic and a corresponding harmonic content.
Optionally, the harmonic with the harmonic content greater than a preset harmonic content threshold is used as a main harmonic;
optionally, the preset number of harmonics with the largest harmonic content rate is used as the main harmonic.
In this embodiment, the determination of the target limit value according to the harmonic component data and the harmonic component-limit value correspondence may adaptively perform harmonic compensation according to the main harmonic and the corresponding harmonic content in the first time interval, so as to improve the efficiency of harmonic compensation.
In one embodiment of the invention, the harmonic component-limit value correspondence includes a harmonic component-modulation wave amplitude limit correspondence, and the target limit value includes a modulation wave target limit value;
determining a target limit value corresponding to the harmonic component data according to the harmonic component data and the harmonic component-limit value correspondence includes:
determining a modulation wave target amplitude limit value corresponding to the current harmonic component according to the current harmonic component data and the harmonic component-modulation wave amplitude limit value corresponding relation;
in an embodiment of the present invention, before S103, the method further includes:
and judging whether the harmonic component data meets a preset component condition, and if so, executing the step S103.
Specifically, the preset composition condition includes a harmonic content interval corresponding to a preset number of harmonics.
Since the low order harmonics can be compensated by the control algorithm, and the high order harmonics such as 13 th order harmonics and 15 th order harmonics are suitable for compensation by the method provided by the embodiment of the present invention, it is necessary to determine whether the harmonic component data meets the component condition before performing step S103.
In an embodiment of the present invention, after S102, the method further includes:
s501: acquiring the current load rate of the target inverter circuit;
s502: determining an adjusting coefficient corresponding to the current load rate based on the load rate-adjusting coefficient corresponding relation;
s503: adjusting the target limit based on the adjustment factor.
In the present embodiment, the corresponding target limit value is also changed according to the load factor of the target inverter circuit. Specifically, as the load factor of the target inverter circuit increases, the corresponding adjustment coefficient also increases.
In this embodiment, adjusting the target limit value based on the current load rate of the target inverter circuit may further optimize the effect of the harmonic compensation.
In this embodiment, before S501, the method further includes:
s601: setting at least one test load rate in the test inverter circuit; the structure of the test inverter circuit is the same as that of the target inverter circuit; the test load rate is the load rate in the test load rate interval;
s602: carrying out optimization test on each test load rate in the test inverter circuit to obtain an adjustment coefficient corresponding to each test load rate;
s603: and generating the load rate-adjustment coefficient corresponding relation according to the adjustment coefficient corresponding to each test load rate.
In this embodiment, before S601, the method further includes: and determining the range of the test load rate interval according to actual requirements. For example, in practical applications, the requirement on the harmonic distortion rate of the input current of the load rate of 30% to 50% in the inverter circuit is relatively strict, and therefore, the load rate of 30% to 50% can be selected as a test load rate interval.
In this embodiment, S601 includes: and selecting at least one test load rate within the test load rate interval according to a preset load rate interval.
Optionally, the experimental load rate interval is divided into a common load rate interval and other load rate intervals according to actual requirements, a smaller load rate interval is set in the common load rate interval of the target inverter circuit, and a larger load rate interval is set in the other load rate intervals.
Optionally, a smaller load rate interval is set in a load rate interval in which the target inverter circuit is greatly affected by the harmonic, and a larger load rate interval is set in a load rate interval except for the load rate interval greatly affected by the harmonic.
In this embodiment, S602 includes:
keeping the load rate of a test inverter circuit as a first load rate, sequentially adjusting the adjustment coefficients of the test inverter circuit by a third preset step length, and simultaneously acquiring the current harmonic distortion rate of the test inverter circuit corresponding to each adjustment coefficient;
and selecting the adjusting coefficient with the minimum harmonic distortion rate in the limit values corresponding to the first load rate as the optimal adjusting coefficient corresponding to the first load rate.
And determining the optimal adjustment coefficient corresponding to each test load rate according to the steps.
In this embodiment, S603 includes: and performing curve fitting on the optimal adjustment coefficient corresponding to each test load rate to generate a load rate-adjustment coefficient corresponding relation corresponding to the test load interval.
In one embodiment of the present invention, the monitoring data includes a load rate of the target inverter circuit, and the monitoring data-limit value correspondence includes a load rate-limit value correspondence;
s102 includes:
and determining a target limit value corresponding to the load rate according to the corresponding relation between the load rate and the load rate limit value.
In this embodiment, the first time interval corresponds to a time interval in which the amplitude of the modulated wave reaches the maximum value, and in the process of performing harmonic compensation on the target inverter circuit through the target limit value, only the part with the too large amplitude of the modulated wave is limited, or only the part with the too large duty ratio in the initial PWM control signal is limited, and the other parts of the signal are not processed, so that harmonic compensation can be performed on the current in the first interval with serious harmonic distortion in a targeted manner.
In this embodiment, the target limit value is determined according to the load rate of the target inverter circuit and the pre-stored load rate-limit value correspondence, so that the data processing amount in the harmonic compensation process can be reduced, and the harmonic compensation efficiency can be improved.
In this embodiment, before S101, the method further includes:
s701: setting at least one test load rate in a test inverter circuit, wherein the structure of the test inverter circuit is the same as that of the target inverter circuit;
s702: carrying out optimization test on each test load rate in the test inverter circuit to obtain an optimal limit value corresponding to each test load rate;
s703: and generating the load rate-limit value corresponding relation according to the optimal limit value corresponding to each test load rate.
In this embodiment, the load rate-limit value correspondence relationship includes a load rate-modulation wave amplitude limit value correspondence relationship and a load rate-duty ratio limit value correspondence relationship, the optimization test includes a modulation wave amplitude limit value optimization test and a duty ratio limit value optimization test, the load rate-limit value correspondence relationship is determined through the modulation wave amplitude limit value optimization test, and the load rate-duty ratio limit value correspondence relationship is determined through the duty ratio limit value optimization test.
In this embodiment, S702 includes:
when the load rate of the test inverter circuit is a first test load rate, sequentially adjusting the limit values of the test inverter circuit by preset step lengths, and simultaneously acquiring the current harmonic distortion rate corresponding to each limit value;
selecting the limit value with the minimum current harmonic distortion rate in the limit values corresponding to the first test load rate as the optimal limit value corresponding to the first test load rate;
and determining the optimal limit value corresponding to each test load rate according to the steps.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
Referring to fig. 5, an embodiment of the present invention provides a harmonic compensation apparatus 10 for an inverter circuit, including:
the monitoring data acquisition module 110 is configured to acquire monitoring data of a target inverter circuit in a first time interval; the first time interval is the time interval of the moment when the value of the current signal is zero, and the current signal is the current signal output by the target inverter circuit;
a target limit value obtaining module 120, configured to determine a target limit value corresponding to the monitoring data according to the monitoring data and the monitoring data-limit value correspondence;
a PWM control signal generating module 130, configured to generate a PWM control signal based on the carrier of the target inverter circuit, the initial modulation wave, and the target limit; the PWM control signal is used for controlling the target inverter circuit to compensate current harmonics of the target inverter circuit in a first time interval.
The harmonic compensation device of the inverter circuit provided by the embodiment of the invention can dynamically adjust the target limit value according to the monitoring data of the current signal in the target inverter circuit and generate the PWM control signal according to the target limit value, thereby effectively performing harmonic compensation on the target inverter circuit on the premise of not needing to perform large-scale calculation, improving the efficiency of harmonic compensation and improving the effect of harmonic compensation.
In one embodiment of the present invention, the monitoring data-limit value correspondence includes a monitoring data-modulation wave limit value correspondence, and the target limit value includes a modulation wave target limit value;
the PWM control signal generation module 130 includes:
a modulated wave generating unit for performing amplitude limiting on the initial modulated wave based on the modulated wave target limit value to generate a target modulated wave;
and a first PWM control signal generation unit configured to modulate the carrier wave and the target modulation wave to generate a PWM control signal.
In one embodiment of the invention, the monitored data-limit correspondence comprises a monitored data-duty cycle limit correspondence, and the target limit comprises a duty cycle target limit;
the PWM control signal generation module 130 includes:
an initial PWM control signal generation unit configured to modulate the carrier wave and the initial modulation wave to generate an initial PWM control signal;
and the second PWM control signal generation unit is used for adjusting the initial PWM control signal according to the target duty ratio limit value and generating the PWM control signal.
In one embodiment of the present invention, the second PWM control signal generating unit includes:
a duty ratio obtaining subunit, configured to obtain a duty ratio of the initial PWM control signal in each carrier period;
a duty ratio adjusting subunit, configured to limit a duty ratio of a period to be adjusted in the initial PWM control signal by using the target duty ratio limit, and generate the PWM control signal; and the period to be adjusted is a carrier period of which the duty ratio in the initial PWM control signal is greater than the target limit value of the duty ratio.
In one embodiment of the present invention, the harmonic compensation device 10 of the inverter circuit further includes:
the optimizing test module is used for acquiring at least one test monitoring data in the test inverter circuit; the structure of the test inverter circuit is the same as that of the target inverter circuit; carrying out optimization test on each test monitoring data in the test inverter circuit to obtain an optimal limit value corresponding to each test monitoring data; and generating the monitoring data-limit value corresponding relation according to the optimal limit value corresponding to each test monitoring data.
In one embodiment of the present invention, the monitoring data includes harmonic component data in a current signal output by a target inverter circuit, and the harmonic component data includes a harmonic content rate corresponding to each harmonic; the monitoring data-limit value corresponding relation comprises a harmonic component-limit value corresponding relation; the target limit acquisition module 120 is specifically configured to:
and determining a target limit value corresponding to the harmonic component data according to the harmonic component data and the harmonic component-limit value corresponding relation.
In one embodiment of the present invention, the harmonic compensation device 10 of the inverter circuit further includes:
the target limit value adjusting module is used for acquiring the current load rate of the target inverter circuit; determining an adjusting coefficient corresponding to the current load rate based on the load rate-adjusting coefficient corresponding relation; adjusting the target limit based on the adjustment system.
In one embodiment of the present invention, the monitoring data includes harmonic component data in a current signal output by a target inverter circuit, and the harmonic component data includes a harmonic content rate corresponding to each harmonic; the monitoring data-limit value corresponding relation comprises a harmonic component-limit value corresponding relation; the target limit acquisition module 120 is specifically configured to:
and determining a target limit value corresponding to the harmonic component data according to the harmonic component data and the harmonic component-limit value corresponding relation.
In one embodiment of the present invention, the monitoring data includes a load rate of the target inverter circuit, and the monitoring data-limit value correspondence includes a load rate-limit value correspondence;
the target limit acquisition module 120 is further configured to:
and determining a target limit value corresponding to the load rate according to the corresponding relation between the load rate and the load rate limit value.
Fig. 6 is a schematic diagram of a terminal device according to an embodiment of the present invention. As shown in fig. 6, the terminal device 6 of this embodiment includes: a processor 60, a memory 61 and a computer program 62 stored in said memory 61 and executable on said processor 60. The processor 60, when executing the computer program 62, implements the steps in the above-described harmonic compensation method embodiments of the respective inverter circuits, such as S101 to S103 shown in fig. 1. Alternatively, the processor 60, when executing the computer program 62, implements the functions of the modules/units in the above-mentioned device embodiments, such as the functions of the modules 110 to 130 shown in fig. 5.
Illustratively, the computer program 62 may be partitioned into one or more modules/units that are stored in the memory 61 and executed by the processor 60 to implement the present invention. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution of the computer program 62 in the terminal device 6. For example, the computer program 62 may be divided into a load rate acquisition module, a target clipping value determination module, a PWM control signal generation module, and a compensation module.
The terminal device 6 may be a desktop computer, a notebook, a palm computer, a cloud server, or other computing devices. The terminal device may include, but is not limited to, a processor 60, a memory 61. Those skilled in the art will appreciate that fig. 6 is merely an example of a terminal device 6 and does not constitute a limitation of terminal device 6 and may include more or less components than those shown, or some components in combination, or different components, for example, the terminal device may also include input output devices, network access devices, buses, etc.
The Processor 60 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 61 may be an internal storage unit of the terminal device 6, such as a hard disk or a memory of the terminal device 6. The memory 61 may also be an external storage device of the terminal device 6, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are provided on the terminal device 6. Further, the memory 61 may also include both an internal storage unit and an external storage device of the terminal device 6. The memory 61 is used for storing the computer program and other programs and data required by the terminal device. The memory 61 may also be used to temporarily store data that has been output or is to be output.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other ways. For example, the above-described embodiments of the apparatus/terminal device are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow of the method according to the embodiments of the present invention may also be implemented by a computer program, which may be stored in a computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method embodiments may be implemented. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A harmonic compensation method of an inverter circuit, comprising:
acquiring monitoring data of a target inverter circuit in a first time interval; the first time interval is the time interval of the moment when the value of the current signal is zero, and the current signal is the current signal output by the target inverter circuit;
determining a target limit value corresponding to the monitoring data according to the monitoring data and the monitoring data-limit value corresponding relation;
generating a PWM control signal based on a carrier wave of the target inverter circuit, an initial modulation wave and the target limit value; the PWM control signal is used for controlling the target inverter circuit to compensate current harmonics of the target inverter circuit in a first time interval.
2. The method of claim 1, wherein the monitoring data-limit value correspondence comprises a monitoring data-modulation wave limit value correspondence, and the target limit value comprises a modulation wave target limit value;
the generating of the PWM control signal based on the carrier wave of the target inverter circuit, the initial modulation wave, and the target limit value includes:
carrying out amplitude limiting on the initial modulation wave based on the modulation wave target amplitude limiting value to generate a target modulation wave;
and modulating the carrier wave and the target modulation wave to generate the PWM control signal.
3. The method of claim 1, wherein the monitored data-limit correspondence comprises a monitored data-duty cycle limit correspondence, and the target limit comprises a duty cycle target limit;
the generating of the PWM control signal based on the carrier wave of the target inverter circuit, the initial modulation wave, and the target limit value includes:
modulating the carrier wave and the initial modulation wave to generate an initial PWM control signal;
and adjusting the initial PWM control signal according to the duty ratio target limit value to generate the PWM control signal.
4. The method of claim 3, wherein the adjusting the initial PWM control signal according to the duty cycle target limit to generate the PWM control signal comprises:
acquiring the duty ratio of the initial PWM control signal in each carrier period;
limiting the duty ratio of the period to be adjusted in the initial PWM control signal by adopting the target limit value of the duty ratio to generate the PWM control signal; and the period to be adjusted is a carrier period of which the duty ratio in the initial PWM control signal is greater than the target limit value of the duty ratio.
5. The method of claim 1, wherein prior to the obtaining of the monitoring data of the target inverter circuit in the first time interval, the method further comprises:
acquiring at least one test monitoring data in the test inverter circuit; the structure of the test inverter circuit is the same as that of the target inverter circuit;
carrying out optimization test on each test monitoring data in the test inverter circuit to obtain an optimal limit value corresponding to each test monitoring data;
and generating the monitoring data-limit value corresponding relation according to the optimal limit value corresponding to each test monitoring data.
6. The method according to any one of claims 1 to 5, wherein the monitoring data includes harmonic component data in the current signal output from the target inverter circuit, the harmonic component data including a harmonic content rate corresponding to each harmonic; the monitoring data-limit value corresponding relation comprises a harmonic component-limit value corresponding relation; the determining the target limit value corresponding to the monitoring data according to the monitoring data and the monitoring data-limit value corresponding relation includes:
and determining a target limit value corresponding to the harmonic component data according to the harmonic component data and the harmonic component-limit value corresponding relation.
7. The method of claim 1, wherein after determining the target limit corresponding to the monitored data according to the monitored data and the monitored data-target limit correspondence, the method further comprises:
acquiring the load rate of the target inverter circuit;
determining an adjusting coefficient corresponding to the load rate based on the corresponding relation of the load rate and the adjusting coefficient;
adjusting the target limit based on the adjustment factor.
8. A harmonic compensation device for an inverter circuit, comprising:
the monitoring data acquisition module is used for acquiring monitoring data of the target inverter circuit in a first time interval; the first time interval is the time interval of the moment when the value of the current signal is zero, and the current signal is the current signal output by the target inverter circuit;
the target limit value acquisition module is used for determining a target limit value corresponding to the monitoring data according to the monitoring data and the monitoring data-limit value corresponding relation;
the PWM control signal generation module is used for generating a PWM control signal based on the carrier wave of the target inverter circuit, the initial modulation wave and the target limit value; the PWM control signal is used for controlling the target inverter circuit to compensate current harmonics of the target inverter circuit in a first time interval.
9. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.
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