KR20140077675A

KR20140077675A - Digital pre-distortion apparatus

Info

Publication number: KR20140077675A
Application number: KR1020120146746A
Authority: KR
Inventors: 오정훈; 김명돈; 이정남
Original assignee: 한국전자통신연구원
Priority date: 2012-12-14
Filing date: 2012-12-14
Publication date: 2014-06-24

Abstract

The present invention relates to a digital pre-distortion apparatus. The digital pre-distortion apparatus comprises: an input delay unit which delays processing of input data as many as the order of a memory; a constant storing unit storing constant numbers of an polynomial expression corresponding to the order of the memory; a digital pre-distortion unit performing an operation using the input data through the input delay unit and the constant numbers of the polynomial expression corresponding to the order of the memory; and an addition unit storing an output of the digital pre-distortion unit, adding a number of the order of the memory to the output a time period of the order of the memory later, and outputting a result of the addition. According to the present invention, the digital pre-distortion apparatus can be implemented using hardware resources at the minimum. Thus, an increment in the hardware resources due to an extension of the order of the memory can be minimized when the digital pre-distortion apparatus considering memory effects is implemented.

Description

[0001] DIGITAL PRE-DISTORTION APPARATUS [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital predistortion (DPD) apparatus, and more particularly, to a digital predistorter used for improving the linearity of a power amplifying apparatus.

As will be appreciated, the power amplifying device can employ a digital predistorter for improved linearity.

In addition, the digital predistorter is implemented by a mixture of software and hardware. Particularly, in order to transmit real time data, an associative device such as a multiplier must be included, which is implemented in hardware.

However, this power amplifying device has a memory effect in which the past input affects the current input.

Considering such a memory effect by the prior art, there is a problem that the hardware resources are increased according to the expansion of the memory order, which burdens the implementation of the system.

An embodiment of the present invention is to implement a digital predistorter used for improving the linearity of a power amplifying device by using less hardware resources.

The problems to be solved by the present invention are not limited to those mentioned above, and another problem to be solved can be clearly understood by those skilled in the art from the following description.

As one aspect of the present invention, a digital predistorter includes an input delay unit for delaying input data by a memory order, a constant storage unit for storing a polynomial constant corresponding to the memory order, A digital predistorter for calculating the data by using the polynomial constant for each memory order, and an adder for storing the output of the digital predistorter and adding the same as the memory order after a time corresponding to the memory order can do.

According to the embodiment of the present invention, a digital predistorter used for improving the linearity of the power amplifying device can be implemented using the minimum hardware resources.

Therefore, there is an effect of minimizing the increase of hardware resources due to the expansion of the memory order when implementing the digital predistorter considering the memory effect.

1 is a configuration diagram of a power amplifying apparatus to which a digital predistorter can be applied.
2 is a detailed configuration diagram of a digital predistorter.
3 is a block diagram of a digital predistorter according to an embodiment of the present invention.
4 is a detailed configuration diagram of the constant storage unit shown in FIG.
5 is a detailed configuration diagram of the adder shown in FIG.
FIG. 6 is a timing chart for explaining an operation of a digital predistorter according to an embodiment of the present invention. Referring to FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions in the embodiments of the present invention, which may vary depending on the intention of the user, the intention or the custom of the operator. Therefore, the definition should be based on the contents throughout this specification.

1 is a configuration diagram of a power amplifying apparatus to which a digital predistorter can be applied.

As shown, the power amplifying device 10 includes a nonlinear power amplifier 11, mixers 12 and 13, a digital-to-analog converter 14, an analog-to-digital converter 15, and a digital predistortion device 16 And the digital predistorter 16 includes a digital predistortion section 16a and a digital predistortion control section 16b.

In this power amplifying device 10, the initial output of the nonlinear power amplifier 11 is not linearly output from the output according to the input. (N) is generated by comparing the output signal z (n), which is the feedback signal of the nonlinear power amplifier 11, with the original signal x (n), and the generated correction signal y (n) Linear power amplifier 11, the output of the nonlinear power amplifier 11 is linearly outputted.

Here, the power amplifier 10 has a memory effect in which past input affects the current input, and is modeled as a polynomial equation.

Referring to Equation (1), the output y (n) of the digital predistorter 16 is the past input x (n-1), x (n-2), ... , and x (n-q), respectively.

Equation (1) is expressed by an equivalent circuit as shown in FIG.

3 is a block diagram of a digital predistorter according to an embodiment of the present invention.

The digital predistorter 100 according to the embodiment includes an input delay unit 110, a constant storage unit 120, a digital predistortion unit 130, and an adder 140.

The input delay unit 110 stores the input data so that the digital predistorter 130 can calculate the input data by the memory order.

The constant storage unit 120 stores a polynomial constant corresponding to the memory order.

The digital predistorter 130 calculates the input data and a polynomial constant for each memory order.

The adder 140 stores the output of the digital predistorter < EMI ID = 2.0 >

According to such a digital predistorter 100, the input delay unit 110 delays input data by a memory order.

The digital predistorter 130 performs an operation using the input data passed through the input delay unit 110 and a polynomial constant for each memory order stored in the constant storage unit 120. [

Here, the adder 140 stores the output of the digital predistorter 130, and outputs the result after adding a memory degree after a time corresponding to the memory order.

4 is a detailed configuration diagram of the constant storage unit 120 shown in FIG.

The constant storing unit 120 stores a constant value of Equation 1 calculated by the digital predistortion controller (16b in FIG. 1), and has a constant value as much as the memory order for the input data. The constant storage unit 120 may be implemented in various ways such as a memory, a first in first out (FIFO), and the like.

FIG. 5 is a detailed configuration diagram of the adder 140 shown in FIG.

The adder 140 stores a predistortion calculation result using a constant corresponding to a memory order for one input, and outputs a sum of the outputs when the calculations for the memory order are completed.

FIG. 6 is an exemplary timing diagram for a memory order (Q = 3) for explaining the operation of the digital predistorter 100 in consideration of a memory effect according to an embodiment of the present invention.

6 (a) shows an operation for input data when a digital predistorter corresponding to a memory order is applied as shown in FIG.

If the data input is D1, D2, D3, ... The output of the digital predistorter 1, the output of the digital predistorter 2, and the output of the digital predistorter 3, respectively. The memory order used here is (Q = 3), and the constant values of the polynomials used in the digital predistortion units are all different.

In this process, the digital predistortion output considering the memory effect can be made by summing the results of each digital predistorter after the memory time. That is, in the case where the memory effect is not taken into account, the output of y (1) is determined only by the input D3, but when the memory effect is taken into consideration, the output is influenced by past inputs D1 and D2.

Such a parallel structure scheme consumes a large amount of hardware resources, and in order to compensate for this, the present invention operates as shown in FIG. 6 (b).

The input speed of the data to the input delay unit 110 of FIG. 3 is the same as that of FIG. 6 (a), but the output of the input delay unit 110 has a higher clock speed by the memory order as shown in FIG. 6 (b). Therefore, the digital predistortion apparatus 100 according to the present invention performs digital predistortion calculation by a memory order at a time when the digital predistortion unit of the parallel structure processes one data, and the calculated result is output to the adder 140 After being stored in the digital predistortion output storage and after a period of time corresponding to the memory order, an output considering the memory effect is obtained by performing the addition as shown by the arrows in FIG. 6 (b).

Therefore, the digital predistorter 100 according to the present invention can obtain the same or better calculation results as compared with the conventional technology, while using a small amount of hardware resources in an addition manner.

The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

Claims

An input delay unit for delaying input data by a memory order;
A constant storage unit for storing a polynomial constant corresponding to the memory order;
A digital predistorter for calculating the input data through the input delay unit and the polynomial constant for each memory order,
And an adder which stores the output of the digital predistorter and outputs the added result by the memory order after a time corresponding to the memory order.