CN111987146A - Wafer for preparing semiconductor device and back thinning method of wafer - Google Patents
Wafer for preparing semiconductor device and back thinning method of wafer Download PDFInfo
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- CN111987146A CN111987146A CN202010992591.0A CN202010992591A CN111987146A CN 111987146 A CN111987146 A CN 111987146A CN 202010992591 A CN202010992591 A CN 202010992591A CN 111987146 A CN111987146 A CN 111987146A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims description 39
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 25
- 238000001259 photo etching Methods 0.000 claims description 12
- 238000000227 grinding Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 230000001681 protective effect Effects 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 abstract description 4
- 238000001039 wet etching Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
Abstract
The invention relates to a wafer for preparing a semiconductor device, which comprises a wafer body, wherein a groove is formed in the back surface of the wafer body through back surface thinning, the wafer body surrounds the groove to form a support ring positioned on the edge of the wafer body, and the side surface of the support ring, namely the inner side surface of the groove, is an inclined surface. The photoresist of the wafer for preparing the semiconductor device is not easy to remain during back N-type exposure, so that the influence of the photoresist on equipment during annealing is avoided.
Description
Technical Field
The present invention relates to a wafer, and more particularly, to a wafer for manufacturing a semiconductor device. In addition, the invention also discloses a back thinning method of the wafer.
Background
When semiconductor devices such as RC-IGBT are prepared, back side N-type photoetching is needed to be carried out on the wafer. Before photoetching, the wafer must be thinned to a specified thickness (60um-130um), and the back surface photoetching equipment has higher requirements on the thickness of the wafer, and the current back surface photoetching equipment cannot directly process the thinner wafer, so the prior art adopts a TAIKO process to grind the back surface of the wafer.
The TAIKO process comprises the following steps: pasting a protective film (a blue film or a UV film) on the front surface of the wafer; grinding the inside of the wafer (dry etching and wet etching) to a thin slice (the thickness is less than 60-130 um); removing the protective film; back side processes (including photoresist coating, back side lithography, ion implantation, photoresist removal, annealing, back side metallization); dotting and testing; ring cutting (removal of the support ring) and dicing, etc.
In the TAIKO process, when the wafer is ground, the entire plane of the wafer, i.e., the silicon wafer, is not thinned, but only the middle portion of the wafer is thinned, and the edge portion (3-5.5mm) of the periphery of the wafer is not thinned, and the edge portion which is not thinned forms the support ring. Through the technology, the carrying risk of the thin wafer can be reduced, the warping and the fragments of the wafer are reduced, and the processing requirement on the ultrathin wafer with the thickness less than 100um is met. But this technique also introduces new problems as follows.
Currently, the wafer ground by the TAIKO process has a width of 3-5.5mm and a thickness of 725um (8 inch wafer), and the thickness of the wafer is about 60-130um, and the inner sidewall of the wafer edge support ring forms a 90 DEG right angle with the inner upper surface of the wafer. When the back photoresist is removed, photoresist is easily accumulated at a right angle formed by the inner side wall of the wafer edge support ring and the inner upper surface of the wafer, so that the photoresist is remained. In the next annealing process, the photoresist is volatilized due to high temperature, so that a furnace tube is polluted or a lens of laser annealing equipment is shielded, the impurity activation efficiency is influenced, and the product yield is reduced. Meanwhile, the wafer ground by the TAIKO process has large stress, which is easy to cause photoetching misalignment and affect the performance of the device.
In addition, the wafer ground by the TAIKO process has a supporting width of 3-5.5mm of the edge supporting ring, which reduces the effective utilization area of the chip and the number of the obtained effective chips, thereby being not beneficial to saving the cost.
In view of the above-mentioned drawbacks, the present inventors have made active research and innovation to create a wafer for manufacturing a semiconductor device with a novel structure, so that the wafer has more industrial application value.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide a wafer for manufacturing a semiconductor device, in which a photoresist is not easily left. In addition, the invention also relates to a back thinning method of the wafer.
The wafer for preparing the semiconductor device comprises a wafer body, wherein the back surface of the wafer body is thinned to form a groove, the wafer body surrounds the groove to form a support ring positioned at the edge of the wafer body, and the side surface of the support ring, namely the inner side surface of the groove, is an inclined surface.
Furthermore, the included angle between the inner side surface of the support ring and the upper surface of the support ring is 30-45 degrees.
Furthermore, the width of the top surface of the support ring is 0.8-1.2 mm.
By the scheme, the invention at least has the following advantages: according to the wafer for preparing the semiconductor device, the slope is arranged, so that the gradient of the inner side surface of the support ring is more moderate, the photoresist is not easy to remain between the support ring and the bottom wall of the groove, and the equipment is prevented from being polluted in the subsequent process.
In summary, the wafer for manufacturing a semiconductor device of the present invention has a simple processing method, and can also solve the problem of photoresist residue caused by backside lithography in the TAIKO process.
A method for thinning the back side of the wafer for preparing the semiconductor device comprises the following steps:
s1: carrying out light grinding on the back of the wafer to form a thin wafer with a flat surface and a thickness smaller than that of the original wafer;
s2: coating photoresist on the back of the thin wafer, and photoetching by adopting a mask pattern corresponding to the support ring pattern;
s3: sequentially exposing and developing the back of the thin wafer, so as to form a support ring photoresist pattern corresponding to the mask on the back of the thin wafer;
s4: and (3) corroding the back of the thin wafer to 60-130 microns by a wet method, so that a groove is formed on the back of the thin wafer, and the inner side surface of the support ring is obliquely intersected with the bottom surface of the groove.
Further, in the method for thinning the back surface of the wafer of the present invention, the thickness of the light grinding in step S1 is 50 to 100 μm.
Further, the method for thinning the back side of the wafer of the present invention includes a step of attaching a protective film to the front side of the wafer before step S1, where the protective film is a blue film or a UV film.
According to the wafer manufactured by the back thinning method of the wafer, the inner side surface of the support ring is an inclined surface, so that the gradient of the wafer is reduced, and photoresist is not easy to remain during back N-type photoetching. Meanwhile, the wet etching can reduce wafer cracking, chipping and corner collapse caused by grinding, and the wet etching can relieve stress and ensure better surface flatness of the wafer. In addition, the back thinning method of the wafer of the invention manufactures the support ring by a photoetching process, thereby ensuring the uniformity of the width of the support ring around the periphery. The invention replaces the whole-course physical grinding TAIKO process and adopts a novel back thinning process of light grinding and chemical corrosion with glue.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Drawings
FIG. 1 is a cross-sectional view of a conventional wafer;
FIG. 2 is a cross-sectional view of a wafer used in the fabrication of a semiconductor device in accordance with the present invention;
in the figure, a wafer body 1, a groove 2 and a support ring 3 are shown.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
Referring to fig. 1 to 2, a wafer for manufacturing a semiconductor device according to a preferred embodiment of the present invention includes a wafer body 1, a back surface of the wafer body is thinned to form a groove 2, and the wafer body forms a support ring 3 around the groove and located at an edge of the wafer body, and the wafer body is characterized in that: the side surface of the supporting ring, namely the inner side surface of the groove is an inclined surface.
The slope of the inner side surface of the support ring is more moderate due to the arrangement of the inclined surface, so that photoresist is not easy to remain between the support ring and the bottom wall of the groove during back N-type photoetching, and further equipment is prevented from being polluted in subsequent processes. Specifically, the groove is a truncated cone with an opening radius larger than the radius of the bottom surface, an obtuse angle larger than 90 degrees is formed between the side surface of the groove, that is, the inner side surface of the support ring, and the bottom surface of the groove, and an included angle alpha between the side surface of the groove and the upper surface of the support ring is between 30 degrees and 45 degrees. When the bottom surface of the groove is located in the horizontal plane, the angle a is an included angle between the inner side surface of the groove and the horizontal plane. The smaller angle alpha enables the space between the inner side surface of the support ring and the bottom surface of the groove to be relatively smooth, and further accumulation and residue of photoresist are prevented. The specific preparation process of the wafer is as follows:
taking an N-type RC-IGBT device as an example, an N-type single crystal silicon material or an N-type epitaxial silicon material is used as a semiconductor substrate material wafer to serve as a drift region of the RC-IGBT device.
And omitting the front process forming process of the RC-IGBT device, and directly carrying out the back process.
A blue film or a UV film is pasted on the front surface of the wafer to protect the front device structure from being damaged;
and (4) lightly grinding the back surface of the wafer to 50-100um to form a flat edge so as to be beneficial to back surface photoetching and wet etching.
Coating a layer of photoresist on the back of the wafer;
carrying out back exposure and development by using the mask pattern, and transferring the mask pattern onto the photoresist to obtain a support ring photoresist pattern;
corroding the back of the wafer to the thickness of 60-130um by a wet method with glue to form a step-shaped, inclined-angle and gentle-slope flat-side ring, namely a support ring;
removing the protective film;
performing a back process including photoresist coating, back photolithography, ion implantation, photoresist removal, annealing, back metallization and the like to form a back device structure, and finally forming a complete RC-IGBT device structure;
dotting and testing;
and performing ring cutting to remove the support ring, the scribing and the like. A plurality of independent chips with complete device structures are formed.
Preferably, in the wafer for manufacturing the semiconductor device, an included angle between the inner side surface of the support ring and the vertical surface is 30-45 degrees.
Preferably, the width of the top surface of the support ring of the wafer for manufacturing the semiconductor device of the embodiment is 0.8-1.2 mm.
The support ring with smaller width improves the utilization rate of the wafer, so that each wafer can produce more semiconductor device chips, and the cost is saved. It is preferably 1 mm.
A method for thinning the back side of the wafer for preparing the semiconductor device comprises the following steps:
s1: carrying out light grinding on the back of the wafer to form a thin wafer with a flat surface and a thickness smaller than that of the original wafer;
s2: coating photoresist on the back of the thin wafer, and photoetching by adopting a mask pattern corresponding to the support ring pattern;
s3: sequentially exposing and developing the back of the thin wafer, so as to form a support ring photoresist pattern corresponding to the mask on the back of the thin wafer;
s4: and (3) corroding the back of the thin wafer to 60-130 microns by a wet method, so that a groove is formed on the back of the thin wafer, and the inner side surface of the support ring is obliquely intersected with the bottom surface of the groove.
Preferably, in the method for thinning the back surface of the wafer according to the present invention, the thickness of the light grinding in step S1 is 50 to 100 μm.
Preferably, the method for thinning the back surface of the wafer according to the present invention includes a step of attaching a protective film to the front surface of the wafer before step S1, where the protective film is a blue film or a UV film.
The protective film can protect the front device structure of the wafer from being damaged.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description.
In addition, the above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention. Also, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (6)
1. A wafer for preparing a semiconductor device comprises a wafer body (1), wherein a groove (2) is formed on the back surface of the wafer body through back surface thinning, a supporting ring (3) located at the edge of the wafer body is formed around the groove by the wafer body, and the wafer is characterized in that: the side surface of the supporting ring, namely the inner side surface of the groove is an inclined surface.
2. The wafer for manufacturing a semiconductor device according to claim 1, wherein: and an included angle between the inner side surface of the support ring and the upper surface of the support ring is 30-45 degrees.
3. The wafer for manufacturing a semiconductor device according to claim 2, wherein: the width of the top surface of the support ring is 0.8-1.2 mm.
4. A method of back-thinning a wafer for manufacturing a semiconductor device according to claim 3, comprising the steps of:
s1: carrying out light grinding on the back of the wafer to form a thin wafer with a flat surface and a thickness smaller than that of the original wafer;
s2: coating photoresist on the back of the thin wafer, and photoetching by adopting a mask pattern corresponding to the support ring;
s3: sequentially exposing and developing the back of the thin wafer, so as to form a support ring photoresist pattern corresponding to the mask on the back of the thin wafer;
s4: and (3) corroding the back of the thin wafer to 60-130 microns by a wet method, so that a groove is formed on the back of the thin wafer, and the inner side surface of the support ring is obliquely intersected with the bottom surface of the groove.
5. The method of claim 3, wherein: the thickness of the light grinding in step S1 is 50-100 μm.
6. The method of claim 3, wherein: step S1 is preceded by a step of attaching a protective film to the front surface of the wafer, wherein the protective film is a blue film or a UV film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010992591.0A CN111987146A (en) | 2020-09-21 | 2020-09-21 | Wafer for preparing semiconductor device and back thinning method of wafer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010992591.0A CN111987146A (en) | 2020-09-21 | 2020-09-21 | Wafer for preparing semiconductor device and back thinning method of wafer |
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| CN111987146A true CN111987146A (en) | 2020-11-24 |
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| CN202010992591.0A Pending CN111987146A (en) | 2020-09-21 | 2020-09-21 | Wafer for preparing semiconductor device and back thinning method of wafer |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101281861A (en) * | 2007-04-05 | 2008-10-08 | 株式会社迪思科 | Wafer processing method |
| KR20150085474A (en) * | 2014-01-15 | 2015-07-23 | 가부시기가이샤 디스코 | Wafer processing method |
| JP2015177170A (en) * | 2014-03-18 | 2015-10-05 | 株式会社ディスコ | Processing method of wafer |
| US20180315610A1 (en) * | 2017-04-28 | 2018-11-01 | Disco Corporation | Wafer processing method |
| CN109599330A (en) * | 2018-11-30 | 2019-04-09 | 中国振华集团永光电子有限公司（国营第八七三厂） | A kind of wafer back side processing technology |
| CN111446164A (en) * | 2020-03-31 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Manufacturing method of edge-gentle-slope/step-shaped wafer |
| CN111446163A (en) * | 2020-03-27 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Wafer with edge stepped/gentle slope type protection ring and manufacturing method thereof |
-
2020
- 2020-09-21 CN CN202010992591.0A patent/CN111987146A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101281861A (en) * | 2007-04-05 | 2008-10-08 | 株式会社迪思科 | Wafer processing method |
| KR20150085474A (en) * | 2014-01-15 | 2015-07-23 | 가부시기가이샤 디스코 | Wafer processing method |
| JP2015177170A (en) * | 2014-03-18 | 2015-10-05 | 株式会社ディスコ | Processing method of wafer |
| US20180315610A1 (en) * | 2017-04-28 | 2018-11-01 | Disco Corporation | Wafer processing method |
| CN109599330A (en) * | 2018-11-30 | 2019-04-09 | 中国振华集团永光电子有限公司（国营第八七三厂） | A kind of wafer back side processing technology |
| CN111446163A (en) * | 2020-03-27 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Wafer with edge stepped/gentle slope type protection ring and manufacturing method thereof |
| CN111446164A (en) * | 2020-03-31 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Manufacturing method of edge-gentle-slope/step-shaped wafer |
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