CN114242579A - Method for improving wafer warpage before TAIKO thinning and film stripping - Google Patents
Method for improving wafer warpage before TAIKO thinning and film stripping Download PDFInfo
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- CN114242579A CN114242579A CN202111541358.1A CN202111541358A CN114242579A CN 114242579 A CN114242579 A CN 114242579A CN 202111541358 A CN202111541358 A CN 202111541358A CN 114242579 A CN114242579 A CN 114242579A
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000001039 wet etching Methods 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 9
- 238000001704 evaporation Methods 0.000 claims abstract description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 3
- 229910017604 nitric acid Inorganic materials 0.000 claims description 3
- 238000001179 sorption measurement Methods 0.000 abstract description 4
- 238000000227 grinding Methods 0.000 abstract description 3
- 238000003631 wet chemical etching Methods 0.000 abstract description 3
- 230000002159 abnormal effect Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 241001050985 Disco Species 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention provides a method for improving wafer warpage before TAIKO thinning and film stripping, wherein a UV film is attached to the front surface of a wafer; pre-thinning the back of the wafer; carrying out TAIKO thinning on the back of the wafer, wherein the middle of the thinned back of the wafer is concave, and a support ring is formed at the edge part; peeling the UV film on the front surface of the wafer; carrying out wet etching on the concave part in the middle of the back surface of the wafer, and protecting the front surface of the wafer; evaporating metal on the back of the wafer to form a metal layer; cutting the front surface of the wafer and attaching a film; and performing ring cutting on the wafer, and removing the support ring on the back of the wafer. The invention provides a process method for improving the problem of wafer warpage before TAIKO thinning and film stripping, which reduces the wafer warpage degree before film stripping by reducing the physical grinding thickness before film stripping, thereby improving the problem that the wafer warpage before film stripping causes abnormal vacuum adsorption and cannot be processed. And after stripping, the wafer is thinned to the target thickness through wet chemical etching.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for improving wafer warping before TAIKO thinning and film stripping.
Background
The TAIKO thinning process is an ultrathin thinning process developed by DISCO company of Japan, the TAIKO thinning process thins the whole plane of a wafer, namely a silicon wafer, but thins the middle part of the wafer, the width of the edge part of the wafer is about 2-5 mm, the thinning is not carried out, and the edge part forms a support ring.
Generally, when the silicon wafer is thin to a certain degree and has a large area, the mechanical strength of the silicon wafer is greatly reduced, and when the thickness of the silicon wafer is less than 200 micrometers, the silicon wafer is curled, so that the silicon wafer cannot be transported, transferred and processed. After the TAIKO thinning process is adopted, only the middle part of the silicon wafer is thinned, and an integrated circuit device is formed by utilizing the middle part of the silicon wafer; the thicker support ring is used for maintaining the mechanical strength of the whole silicon wafer and preventing the silicon wafer from curling. Is beneficial to the carrying, transferring and processing of the subsequent silicon chip.
However, in a wafer of a vertical structure device, such as a medium-high voltage MOSFET, as the depth of a trench increases, the wafer warpage caused by the stress of a silicon wafer further increases, and the wafer warpage caused by the factors such as the increase of the oxidation thickness, the increase of the thermal treatment, the deposition stress of a passivation layer, and the like, also increases with the increase of the operating voltage. On the other hand, in order to seek lower device performance such as on-resistance, the wafer warpage is also increased by reducing the thickness of TAIKO.
These problems all cause the TAIKO process to have the problems of transportation, transfer and processing caused by wafer warpage even if the peripheral support ring exists, such as the failure of chip or vacuum adsorption in the back processing process. Particularly, in the film peeling step after the TAIKO is thinned, the vacuum can not be absorbed and fixed due to the wafer warping problem, and further the processing can not be performed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for improving wafer warpage before TAIKO thinning and stripping, which is used to solve the problem in the prior art that vacuum cannot be fixed by suction due to wafer warpage after TAIKO thinning.
To achieve the above and other related objects, the present invention provides a method for improving wafer warpage before TAIKO thinning stripping, comprising:
step one, providing a wafer, and attaching a UV film to the front surface of the wafer;
step two, pre-thinning the back of the wafer;
step three, carrying out TAIKO thinning on the back of the wafer, wherein the middle of the thinned back of the wafer is concave, and a support ring is formed at the edge part;
step four, peeling off the UV film on the front side of the wafer;
step five, performing wet etching on the concave part in the middle of the back surface of the wafer, and protecting the front surface of the wafer;
step six, evaporating metal on the back of the wafer to form a metal layer;
seventhly, cutting film attachment is carried out on the front surface of the wafer;
and step eight, performing ring cutting on the wafer, and removing the support ring on the back of the wafer.
Preferably, the thickness of the wafer in the first step is 700 to 750 μm.
Preferably, after the back surface of the wafer is pre-thinned in the second step, the remaining thickness of the wafer is 660 μm.
Preferably, the height of the support ring in step three is 600 μm.
Preferably, the wet etching solution in the fifth step is HNO3 and HF.
Preferably, the wet etching thickness of the concave part in the middle of the back surface of the wafer in the fifth step is 50 μm.
Preferably, in the fifth step, the thickness of the wet etching on the concave part in the middle of the back surface of the wafer is 5-20 μm.
As described above, the method for improving wafer warpage before TAIKO thinning and stripping of the film according to the present invention has the following beneficial effects: the invention provides a process method for improving the problem of wafer warpage before TAIKO thinning and film stripping, which reduces the wafer warpage degree before film stripping by reducing the physical grinding thickness before film stripping, thereby improving the problem that the wafer warpage before film stripping causes abnormal vacuum adsorption and cannot be processed. And after stripping, the wafer is thinned to the target thickness through wet chemical etching.
Drawings
FIG. 1 is a schematic view of a structure of attaching a UV film thickness to the front surface of a wafer according to the present invention;
FIG. 2 is a schematic view of a wafer with a pre-thinned back side according to the present invention;
FIG. 3 is a schematic view of the wafer backside TAIKO thinning according to the present invention;
FIG. 4 is a schematic view of the front side of the wafer after UV stripping;
FIG. 5 is a schematic structural diagram of the wafer after wet etching of the concave portion in the middle of the back surface of the wafer;
FIG. 6 is a schematic structural diagram of the wafer after metal deposition on the back side of the wafer;
FIG. 7 is a schematic structural view of the front surface of the wafer after the dicing film is attached;
FIG. 8 is a schematic diagram of a wafer after ring-cutting in the present invention;
FIG. 9 is a flowchart of a method of improving wafer warpage before TAIKO thinning and stripping in the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The invention provides a method for improving wafer warpage before TAIKO thinning and stripping, as shown in FIG. 9, FIG. 9 is a flow chart of the method for improving wafer warpage before TAIKO thinning and stripping in the invention, the method at least comprises the following steps:
step one, providing a wafer, and attaching a UV film to the front surface of the wafer; as shown in fig. 1, fig. 1 is a schematic structural view illustrating the UV film thickness attached to the front surface of the wafer according to the present invention. In the first step, the wafer 01 is provided, and the UV film 02 is attached to the front surface of the wafer 01. The UV film 02 is used to protect the front side of the wafer from damage during subsequent TAIKO thinning.
Further, the thickness of the wafer in the first step of the embodiment is 700 to 750 μm. That is, before the wafer is thinned in the first step of the present invention, the thickness of the wafer is 700 to 750 μm.
Step two, pre-thinning the back of the wafer; as shown in fig. 2, fig. 2 is a schematic structural view of the wafer with the back surface thereof being pre-thinned. In the second step, the back surface of the wafer is thinned in advance, and the thickness of the wafer 03 thinned in advance needs to meet the requirements of subsequent TAIKO thinning and wet thinning.
Further, in the second step of this embodiment, the back surface of the wafer is pre-thinned, and the remaining thickness of the pre-thinned wafer 03 is 660 μm.
Step three, carrying out TAIKO thinning on the back of the wafer, wherein the middle of the thinned back of the wafer is concave, and a support ring is formed at the edge part; as shown in fig. 3, fig. 3 is a schematic structural view of the wafer after the wafer is subjected to TAIKO thinning. And in the third step, TAIKO thinning is carried out on the back surface of the wafer, the middle of the back surface of the wafer after TAIKO thinning is provided with a concave back surface 05 of the wafer, and the edge part of the back surface of the wafer forms a support ring 04.
Further, the height of the support ring 04 in step three of this embodiment is 600 μm.
Step four, peeling off the UV film on the front side of the wafer; as shown in fig. 4, fig. 4 is a schematic structural view of the front surface of the wafer after UV stripping. In the fourth step, the wafer 06 from which the UV film is peeled is formed.
Step five, performing wet etching on the concave part in the middle of the back surface of the wafer, and protecting the front surface of the wafer; as shown in fig. 5, fig. 5 is a schematic structural view of the wafer after wet etching of the concave portion in the middle of the back surface of the wafer. And in the fifth step, the front surface of the wafer is protected so as to prevent the front surface of the wafer from being damaged when wet etching is carried out on the back surface.
Further, in the present invention, the wet etching solution in the fifth step of this embodiment is HNO3 and HF. The wafer 07 after wet etching is formed after wet etching the concave portion of the wafer backside as shown in fig. 5.
Further, in the fifth step of this embodiment, the wet etching thickness of the concave portion in the middle of the back surface of the wafer is 50 μm.
Step six, evaporating metal on the back of the wafer to form a metal layer; as shown in fig. 6, fig. 6 is a schematic structural diagram of the wafer back surface after metal deposition. In the sixth step, metal evaporation is performed on the back surface of the wafer, and the formed metal layer 08 covers the back surface of the wafer 07 subjected to wet etching and the inner side of the support ring.
Seventhly, cutting film attachment is carried out on the front surface of the wafer; as shown in fig. 7, fig. 7 is a schematic structural view of the front surface of the wafer after the dicing film is attached. In the seventh step, the dicing film 09 is attached to the front surface of the wafer.
And step eight, performing ring cutting on the wafer, and removing the support ring on the back of the wafer. As shown in fig. 8, fig. 8 is a schematic structural view of a wafer after ring-cutting in the present invention. In the eighth step, the support ring is cut along the direction perpendicular to the wafer surface inside the support ring, so as to form the structure shown in fig. 8.
In summary, the invention provides a process method for improving the wafer warpage problem before TAIKO thinning and film stripping, which reduces the wafer warpage degree before film stripping by reducing the physical grinding thickness before film stripping, thereby improving the problem that processing cannot be performed due to vacuum adsorption abnormality caused by wafer warpage before film stripping. And after stripping, the wafer is thinned to the target thickness through wet chemical etching. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (7)
1. A method for improving wafer warpage before TAIKO thinning stripping is characterized by at least comprising the following steps:
step one, providing a wafer, and attaching a UV film to the front surface of the wafer;
step two, pre-thinning the back of the wafer;
step three, carrying out TAIKO thinning on the back of the wafer, wherein the middle of the thinned back of the wafer is concave, and a support ring is formed at the edge part;
step four, peeling off the UV film on the front side of the wafer;
step five, performing wet etching on the concave part in the middle of the back surface of the wafer, and protecting the front surface of the wafer;
step six, evaporating metal on the back of the wafer to form a metal layer;
seventhly, cutting film attachment is carried out on the front surface of the wafer;
and step eight, performing ring cutting on the wafer, and removing the support ring on the back of the wafer.
2. The method for improving wafer warpage before TAIKO thinning and stripping as claimed in claim 1, wherein: the thickness of the wafer in the first step is 700-750 μm.
3. The method for improving wafer warpage before TAIKO thinning and film stripping according to claim 1 or 2, wherein: and in the second step, after the back surface of the wafer is pre-thinned, the residual thickness of the wafer is 660 microns.
4. The method for improving wafer warpage before TAIKO thinning and stripping as claimed in claim 3, wherein: the height of the support ring in step three is 600 μm.
5. The method for improving wafer warpage before TAIKO thinning and stripping as claimed in claim 1, wherein: and the wet etching solution in the fifth step is HNO3 and HF.
6. The method for improving wafer warpage before TAIKO thinning and stripping as claimed in claim 4, wherein: and fifthly, the thickness of the wet etching on the concave part in the middle of the back surface of the wafer is 50 mu m.
7. The method for improving wafer warpage before TAIKO thinning and stripping as claimed in claim 1, wherein: and fifthly, the thickness of the wet etching on the concave part in the middle of the back surface of the wafer is 5-20 mu m.
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CN202111541358.1A CN114242579A (en) | 2021-12-16 | 2021-12-16 | Method for improving wafer warpage before TAIKO thinning and film stripping |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN115881527A (en) * | 2023-02-23 | 2023-03-31 | 广州粤芯半导体技术有限公司 | Wafer and wafer warping degree optimization method |
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2021
- 2021-12-16 CN CN202111541358.1A patent/CN114242579A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN115881527A (en) * | 2023-02-23 | 2023-03-31 | 广州粤芯半导体技术有限公司 | Wafer and wafer warping degree optimization method |
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