CN211858584U

CN211858584U - Integrated circuit wafer thinning process supporting structure

Info

Publication number: CN211858584U
Application number: CN202020179392.3U
Authority: CN
Inventors: 苏晋苗; 苏冠暐
Original assignee: Beijing Xinzhilu Enterprise Management Center LP
Current assignee: Beijing Xinzhilu Enterprise Management Center LP
Priority date: 2020-02-18
Filing date: 2020-02-18
Publication date: 2020-11-03
Anticipated expiration: 2030-02-18

Abstract

The utility model belongs to the technical field of the electronic technology and specifically relates to an integrated circuit wafer thinization processing procedure bearing structure, the wafer of arranging circuit chip or device is made including integrated circuit, a side that circuit chip or device were arranged to the wafer is the front, and wafer another side is the back, the back protrusion of wafer has graphic skeleton texture, graphic skeleton texture is connected with between big annular structure and the little annular structure that is close to wafer center department including the big annular structure that is located the peripheral edge of wafer, big annular structure and the little annular structure and is connected the arch, the utility model discloses a bearing structure can realize the wafer thinization processing procedure demand of great diameter and attenuate.

Description

Integrated circuit wafer thinning process supporting structure

Technical Field

The utility model relates to the field of electronic technology, the specific field is an integrated circuit wafer thinization processing procedure bearing structure.

Background

With the rapid development of integrated circuit technology, the process is now being integrated and miniaturized to achieve the purpose of increasing performance and reducing cost, wherein the TAIKO process only grinds the central portion of the wafer and is called the TAIKO (TAIKO) process, and accordingly the peripheral edge of the wafer is not polished to remain the original thickness for maintaining the strength of the wafer and preventing the wafer from being damaged or warped during the subsequent processing or transportation, and the wafer is thinned to 40 microns due to the requirements of short, light and thin integrated circuit, heat dissipation and loss of power devices, precision of sensors, and the like, whereas the TAIKO process is insufficient when the wafer thickness is required to be less than 90 microns in the thinning process of more than 8 inches.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide an integrated circuit wafer thinization processing procedure bearing structure to structural strength is low after solving among the prior art wafer thinization, makes the easy damaged or warping problem of wafer.

In order to achieve the above object, the utility model provides a following technical scheme: the utility model provides an integrated circuit wafer thinization processing procedure bearing structure, includes that integrated circuit makes the wafer of arranging circuit chip or device, the wafer has been arranged a side of circuit chip or device and is the front, and wafer another side is the back, the back protrusion of wafer has figure skeleton texture, figure skeleton texture is including the little ring structure that is located the peripheral edge of wafer big ring structure and is close to wafer center department, is connected with between big ring structure and the little ring structure and connects the arch.

Preferably, the small annular structure is located at a quarter radius of the center of the circle on the back of the wafer.

Preferably, the number of the connecting bulges is three, and the three connecting bulges are uniformly distributed between the large annular structure and the small annular structure at an included angle of 120 degrees to form a three-fork graph structure.

Preferably, the width of the large ring-shaped structure and the small ring-shaped structure is 3-5 mm.

Preferably, the width of the coupling projection is 3 to 5 mm.

Preferably, the thickness of the graphic framework structure is 250-800 nm.

Compared with the prior art, the beneficial effects of the utility model are that: the utility model discloses use wafer thinization processing procedure to form convex dicyclo and trident figure skeleton texture at the wafer back to strengthen the support intensity after the wafer thinization, fall and subtract broken piece damage of wafer. Utilize the technical scheme of the utility model can realize 12 inches or above wafer thinization processes of great diameter to and be applied to beneficial effects such as thinization thickness reaches product demand below 40 microns, and finally reached the purpose that increases the productivity, promoted the yield.

Drawings

Fig. 1 is a schematic view of the framework of the supporting structure of the present invention;

FIG. 2 is a block diagram of method steps of an embodiment of the present invention;

in the figure: 10. the back of the wafer; 101. a large ring structure; 102. a small annular structure; 103. a three-fork graph structure; S1-S4, thinning the wafer to make the supporting structure.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1, the present invention provides a technical solution: the utility model provides an integrated circuit wafer thinization processing procedure bearing structure, includes that integrated circuit makes the wafer of arranging circuit chip or device, the wafer has been arranged a side of circuit chip or device and is the front, and wafer another side is the back, the back protrusion of wafer has figure skeleton texture, figure skeleton texture is including the little ring structure that is located the peripheral edge of wafer big ring structure and is close to wafer center department, is connected with between big ring structure and the little ring structure and connects the arch.

The small ring structure is located at a quarter radius of the center of the wafer back surface, which depends on the actual requirement and is not limited to the description.

The three connecting bulges are uniformly distributed between the large annular structure and the small annular structure at an included angle of 120 degrees to form a three-fork graph structure, and the three connecting bulges are determined according to actual requirements and are not limited to the description.

The width of the large ring-shaped structure and the small ring-shaped structure is 3-5 mm, which depends on the practical requirement and is not limited to the description.

The width of the connecting projection is 3-5 mm, which depends on the actual requirement and is not limited to the description.

The thickness of the graphic framework structure is 250-800 nm, which depends on the practical requirement and is not limited to the description.

As shown in fig. 1-2, a method for fabricating a support structure for an integrated circuit wafer thinning process includes the following steps:

(1) providing a wafer needing a thinning process;

(2) forming a silicon oxide mask layer on the back of the wafer by chemical vapor deposition of tetraethoxysilane;

(3) exposing or photoetching the wafer back mask layer to form a patterned photoresist layer;

(4) performing an etching process on the back surface of the wafer by using Hydrogen Fluoride (HF), removing the part of the photoresist layer which is not covered by the photoresist layer, reserving the pattern on the photoresist layer, and then removing the photoresist layer;

(5) and performing another etching or developing on the back surface of the wafer by using tetramethylammonium hydroxide (TMAH), removing the mask layer and partial area of the back surface of the wafer, and reserving the pattern on the mask layer to the back surface of the wafer to obtain a protruded patterned structure on the back surface of the wafer.

According to the step (3), the patterned photoresist layer is a large ring structure covering the outer edge of the back surface of the wafer, a small ring structure near the center of the back surface of the wafer, and a three-fork connection pattern structure between the two ring structures.

After the protruding pattern skeleton structure is obtained on the back surface of the wafer, the wafer can be further thinned by various thinning processes on the back surface of the wafer.

The thinning process is one or more of finally grinding, etching and laser thinning process, and the thinning process is used for thinning the part of the back surface of the wafer except the protruded pattern skeleton structure.

The above description is not limited to the description, which is determined by practical requirements.

With the present technical solution, the steps of the method for thinning the process supporting structure are shown in fig. 2, and include: s1 arranging circuit chips or devices on the front surface of the wafer, and sticking or coating a protective layer on the integrated circuit; s2 forming a light shield on the back of the wafer and exposing the photoresist layer on the wafer according to the pattern of the utility model, removing the photoresist by developing, and keeping the pattern on the wafer back substrate; s3 the back of the wafer is thinned to form a convex supporting skeleton structure without thinning the pattern, the pattern is a double ring with three-fork connection; s4 the front face of the wafer is cleaned by removing the adhesive or the protective layer, and then the wafer is sent to the next process, the utility model discloses maintain the intact structure of wafer after supporting the wafer thinization.

The utility model discloses when using in the thin manufacturing procedure, carry out various thin manufacturing procedures and form convex figure skeleton texture at wafer back 10, the figure skeleton texture includes the great ring structure (outer loop skeleton texture) 101 that is located wafer peripheral edge and the little ring structure (inner loop skeleton texture) 102 that is located the wafer apart from the radius of a quarter of centre of a circle, and this two ring structure is connected with trident figure skeleton texture 103 of contained angle 120 degrees; after the skeleton structure is obtained, the wafer can be thinned by various thinning processes on the back surface of the wafer in the next step.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A integrated circuit wafer thinning process supporting structure comprises a wafer with circuit chips or devices arranged on the surface, and is characterized in that: the wafer is arranged a side of circuit chip or device and is the front, and wafer another side is the back, the back protrusion of wafer has figure skeleton texture, figure skeleton texture is including the little ring structure that is located the peripheral edge of wafer big ring structure and is close to wafer center department, is connected with between big ring structure and the little ring structure and connects the arch.

2. The integrated circuit wafer thinning process support structure of claim 1, wherein: the small annular structure is positioned on the back of the wafer and is one quarter of the radius away from the center of the circle.

3. The integrated circuit wafer thinning process support structure of claim 1, wherein: the three connecting bulges are uniformly distributed between the large annular structure and the small annular structure at an included angle of 120 degrees to form a three-fork graph structure.

4. The integrated circuit wafer thinning process support structure of claim 1, wherein: the width of the large ring-shaped structure and the small ring-shaped structure is 3-5 mm.

5. The integrated circuit wafer thinning process support structure of claim 1, wherein: the width of the connecting projection is 3-5 mm.

6. The integrated circuit wafer thinning process support structure of claim 1, wherein: the thickness of the graphic framework structure is 250-800 nm.