CN111966195A - Start control circuit and method - Google Patents

Start control circuit and method Download PDF

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Publication number
CN111966195A
CN111966195A CN202010739701.2A CN202010739701A CN111966195A CN 111966195 A CN111966195 A CN 111966195A CN 202010739701 A CN202010739701 A CN 202010739701A CN 111966195 A CN111966195 A CN 111966195A
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circuit
processor
power supply
management component
power
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CN111966195B (en
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王琴
吴杰
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Accelink Technologies Co Ltd
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Accelink Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)

Abstract

The embodiment of the invention provides a starting control circuit and a starting control method. Wherein the circuit comprises: the power supply device comprises a first power supply circuit, a processor, a power management component circuit and a restart control circuit; the first power supply circuit is used for supplying power to the processor; the processor is used for receiving a remote restart instruction and responding to the restart instruction to output a first control signal; the restart instruction is used for instructing the processor to restart; the power management component circuit is used for responding to the first control signal and sending a de-enabling signal to the first power supply circuit so as to enable the first power supply circuit to stop supplying power to the processor; the restarting control circuit is used for sending a second control signal to the power management component circuit after detecting that the processor is powered off; and the power management component circuit is also used for responding to the second control signal and sending an enabling signal to the first power supply circuit so as to enable the first power supply circuit to supply power to the processor again. Therefore, the processor is restarted after being powered off.

Description

Start control circuit and method
Technical Field
The present invention relates to the field of electronic circuits, and in particular, to a start control circuit and method.
Background
In a communication system, a master control card (also called a master single disk) manages a service control card (also called a service single disk), a fan control card (also called a fan single disk) and the like of the whole communication system, and the master control card can monitor and manage power supplies of other control cards, including power-off restart. But some special scenarios also require a power-on restart (i.e., a cold restart) after powering down the processor on the host control card. The traditional cold restart mode needs manual operation and needs personnel to operate on site.
Disclosure of Invention
To solve the related technical problems, embodiments of the present invention provide a start control circuit and method.
The technical scheme of the embodiment of the invention is realized as follows:
the embodiment of the invention provides a starting control circuit which is arranged on a master control card and comprises:
the power supply device comprises a first power supply circuit, a processor, a power management component circuit and a restart control circuit; wherein the content of the first and second substances,
the first power supply circuit is used for supplying power to the processor;
the processor is used for receiving a remote restart instruction and responding to the restart instruction to output a first control signal; the restart instruction is used for instructing the processor to restart;
the power management component circuit is used for responding to the first control signal and sending a de-enabling signal to the first power supply circuit so as to enable the first power supply circuit to stop supplying power to the processor;
the restart control circuit is used for sending a second control signal to the power management component circuit after detecting that the processor is powered off;
the power management component circuit is further configured to send an enable signal to the first power supply circuit in response to the second control signal, so that the first power supply circuit re-supplies power to the processor.
In the foregoing solution, the restart control circuit is configured to:
detecting a voltage of a first pin of the power management component circuit; a first pin of the power management component circuit receives a voltage signal output by a first pin of the processor;
determining that the processor has been powered down when it is detected that the voltage of the first pin of the power management component circuit is less than a first preset voltage.
In the above solution, the restart control circuit includes: a second power supply circuit and a pull-up resistor; wherein the content of the first and second substances,
when the voltage of the first pin of the power management component circuit is smaller than a first preset voltage, the voltage of the first pin of the power management component circuit is increased through the second power supply circuit and a pull-up resistor, so that the power management component circuit sends an enabling signal to the first power supply circuit;
and the first end of the pull-up resistor is connected with the second power supply circuit, and the second end of the pull-up resistor is connected with the first pin of the power management component.
In the above scheme, the second power supply circuit is further configured to supply power to the power management component circuit.
In the above scheme, the power management component circuit includes an and gate circuit and a delay circuit;
two input ends of the AND gate circuit are connected with a first pin of the power management component circuit, and the output end of the AND gate circuit is connected with the input end of the delay circuit; the output end of the delay circuit is connected with a second pin of the power management component circuit; and the second pin of the power management component circuit is connected with the enabling input end of the first power supply circuit.
In the above scheme, the processor is configured to obtain a remote restart instruction through the communication interface.
In the above scheme, the first power supply circuit is further configured to perform voltage conversion on a dc voltage input by an external power supply, and apply the converted voltage to the processor.
In the above scheme, the second power supply circuit is further configured to perform voltage conversion on a dc voltage input by an external power supply, and output the converted voltage.
The embodiment of the invention also provides a starting control method which is applied to the master control card and comprises the following steps: the processor of the starting control circuit receives a remote restarting instruction and responds to the restarting instruction to output a first control signal; the restart instruction is used for instructing the processor to restart;
the power management component circuit of the starting control circuit receives the first control signal and responds to the first control signal to send a de-enabling signal to the first power supply circuit of the starting control circuit so as to enable the first power supply circuit to stop supplying power to the processor;
after a restart control circuit of the starting control circuit detects that the processor is powered off, a second control signal is sent to the power management component circuit;
and the power management component circuit receives the second control signal and responds to the second control signal to send an enabling signal to the first power supply circuit so as to enable the first power supply circuit to supply power to the processor again.
In the above scheme, the method further comprises:
the restart control circuit detects the voltage of a first pin of the power management component circuit; a first pin of the power management component circuit receives a voltage signal output by a first pin of the processor;
determining that the processor has been powered down when it is detected that the voltage of the first pin of the power management component circuit is less than a first preset voltage.
The start control circuit and the method provided by the embodiment of the invention comprise the following steps: the power supply device comprises a first power supply circuit, a processor, a power management component circuit and a restart control circuit; the first power supply circuit is used for supplying power to the processor; the processor is used for receiving a remote restart instruction and responding to the restart instruction to output a first control signal; the restart instruction is used for instructing the processor to restart; the power management component circuit is used for responding to the first control signal and sending a de-enabling signal to the first power supply circuit so as to enable the first power supply circuit to stop supplying power to the processor; the restart control circuit is used for sending a second control signal to the power management component circuit after detecting that the processor is powered off; the power management component circuit is further configured to send an enable signal to the first power supply circuit in response to the second control signal, so that the first power supply circuit supplies power to the processor again. In the embodiment of the invention, a processor receives a restart instruction and outputs a first control signal to a power management component circuit, and the power management component circuit sends an enable signal to stop a first power supply circuit to supply power to the processor based on the first control signal; after the processor is powered off, the restarting control circuit sends a second control signal to the power management component circuit, and the power management component circuit sends an enabling signal based on the second control signal to enable the first power supply circuit to supply power to the processor again.
Drawings
Fig. 1 is a schematic structural diagram of a start control circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another start control circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a power management component circuit of a start control circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a voltage waveform in a start control circuit according to an embodiment of the present invention;
fig. 5 is a flowchart illustrating a start control method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
In a communication system, a master control card (also called a master control single disk) is the core of software and hardware of a control station, coordinates the software and hardware relationship and various control tasks in the control station, and can automatically complete various functions such as data acquisition, information processing, control operation and the like. The master control card manages a service control card (also called a service single disk), a fan control card (also called a fan single disk) and the like of the whole communication system, and the master control card can monitor and manage power supplies of other control cards, including power-off restart. However, in some special scenarios, the processor on the master control card needs to be powered on and restarted after being powered off, i.e. cold restart. The traditional cold restart mode needs manual operation; specifically, a power switch is arranged between a processor of the master control card and a power supply, and the power switch is manually operated to cut off the power switch and restart the power switch, or a power line plug connected with the processor is plugged in and out to complete the power-off restart of the processor.
The conventional cold restart method has some obvious defects, a person is required to perform relevant operations on site in a mode of manually operating the power switch to cut off the power switch and restart the power switch or in a mode of completing the power-off restart of the processor by plugging and unplugging a power line plug connected with the processor, the two modes are to forcibly power off the processor, and the processor hardly has time to store important information before power off.
On the basis, a scheme that a relay is connected in series with a circuit power supply circuit and the processor is restarted after power failure by controlling the relay is provided, however, in the scheme that the processor is restarted in a cold mode by connecting the relay in series, an additional control element is added to the power supply circuit, and the cost of the power supply circuit is increased. In addition, once the relay fails, the entire power supply system may also fail, and there is a great risk to the entire communication system.
Based on this, in various embodiments of the present invention, the processor receives the restart instruction, and outputs a first control signal to the power management component circuit, and the power management component circuit sends a disable signal to stop the first power supply circuit from supplying power to the processor based on the first control signal; when the processor is powered off, the restart control circuit sends a second control signal to the power management component circuit, the power management component circuit sends an enabling signal based on the second control signal to enable the first power supply circuit to supply power to the processor again, and the processor sends an instruction through software to realize remote cold start on the controller.
In the embodiment of the invention, the processor is powered off and restarted, the labor and material cost is saved, and the risk of the power supply system to the whole communication system can be reduced. In addition, a cold reboot of the controller can be achieved by remotely pairing the controller (also referred to as a processor) on the master control card, and based on an existing, more general power management chip (also referred to as a power management component circuit); the method plays a vital role in realizing cold restart of the controller for the unattended remote communication machine room.
As shown in fig. 1, the start control circuit 100 includes:
the first power supply circuit 110, the processor 120, the power management component circuit 130, and the restart control circuit 140; wherein the content of the first and second substances,
the first power supply circuit 110 is configured to supply power to the processor 120;
the processor 120 is configured to receive a remote restart instruction, and output a first control signal in response to the restart instruction; the restart instruction is used to instruct the processor 120 to restart;
the power management component circuit 130 is configured to send a disable signal to the first power supply circuit 110 in response to the first control signal, so that the first power supply circuit 110 stops supplying power to the processor 120;
the restart control circuit 140 is configured to send a second control signal to the power management component circuit 130 after detecting that the processor 120 is powered off;
the power management component circuit 130 is further configured to send an enable signal to the first power supply circuit 110 in response to the second control signal, so that the first power supply circuit 110 supplies power to the processor 120 again.
In the embodiment of the present invention, after the processor 120 receives a restart instruction sent by control software (which may be disposed on a control device) for controlling the processor 120 through a communication system, the voltage of the first pin of the processor 120 is adjusted to be low, so that the level state of the first pin of the processor 120 changes to be a low level state. Here, the high-low level division corresponds to a Transistor-Transistor Logic (TTL) circuit, and the high level is generally 2.4V-5.0V, and the low level is generally 0.0V-0.4V. Therefore, after the processor 120 receives the restart instruction, the voltage value of the first pin may be in the range of 0.0V-0.4V. It should be noted that the embodiments of the present invention are applicable to, but not limited to, TTL circuits.
In the following description, the operation of each circuit is described by taking a TTL circuit as an example.
The first pin of the power management component circuit 130 is connected to the first pin of the processor 120, and when the state of the first pin of the processor 120 changes to a low level, the voltage of the first pin of the power management component circuit 130 is also in a range of 0.0V to 0.4V and is in a low level state. Then, the power management component circuit 130 adjusts the voltage of the second pin thereof to be in the range of 0.0V-0.4V, so as to make it in a low level state.
Here, the second pin of the power management component circuit 130 is connected to an enable input terminal of the first power supply circuit 110, and when the first power supply circuit 110 receives a disable signal (i.e., a low-level voltage signal) sent by the second pin of the power management component circuit 130 through the enable input terminal, a level state of the enable input terminal of the first power supply circuit 110 is a low level, and at this time, the first power supply circuit 110 stops operating, i.e., stops outputting a voltage, thereby achieving disconnection of an electrical connection with the processor 120 and stopping power supply to the processor 120.
After detecting that the processor 120 is powered off, the restart control circuit 140 sends a second control signal to the power management component circuit 130, so as to increase the voltage of the first pin of the power management component circuit 130, and change the level state of the second pin of the power management component circuit 130 into a high level, when the first power supply circuit 110 receives an enable signal (i.e., a high level voltage signal) sent by the second pin of the power management component circuit 130, the level state of the enable input terminal of the first power supply circuit 110 is a high level, and at this time, the first power supply circuit 110 starts to operate, i.e., re-output the voltage, so as to implement the electrical connection with the processor 120 again, and further supply power to the processor 120.
Thus, the processor 120 completes the restart after the power failure, saves the cost of manpower and material resources, and can reduce the risk of the power supply system to the whole communication system. In addition, a cold reboot of the controller can be achieved by remotely pairing the controller (also referred to as a processor) on the master control card, and based on an existing, more general power management chip (also referred to as a power management component circuit); the method plays a vital role in realizing cold restart of the controller for the unattended remote communication machine room.
Here, the first pin of the processor 120 may be a General-purpose input/Output (GPIO) pin, the first pin of the power management component circuit 130 may be a General-purpose input (GPI) pin, the second pin of the power management component circuit 130 may be a General-purpose Output (GPO) pin, and the enable input terminal of the first power supply circuit 110 may be an enable control pin.
In an embodiment, in practical application, the restart control circuit 140 monitors the processor 120 to power off, and determines whether the processor 120 is powered off by detecting the voltage of the first pin of the power management component circuit 130 through the restart control circuit 140; specifically, the processor is determined to be powered off when the voltage of the first pin 130 of the power management component circuit is detected to be less than a first preset voltage. Here, the first preset voltage may be 0.4V, and the first pin of the power management component circuit 130 receives a voltage signal output from the first pin of the processor 120.
The present invention will be described in further detail with reference to the following application examples.
In this embodiment, as shown in fig. 2, the first power supply circuit 110 includes: a first voltage converter (i.e., DC-DC2 in fig. 2) having an EN pin (i.e., an enable input) disposed thereon; the processor 120 includes: the CPU is provided with GPIO pins and is also connected with a network interface 121; the restart control circuit 140 includes: a second power supply circuit 141 and a pull-up resistor 142 (i.e., a resistor R1 in fig. 2); the second power supply circuit 141 includes: a second voltage converter (i.e., DC-DC1 in fig. 2); the power management component circuitry 130 includes: the Power Management Integrated Circuit (PMIC) is provided with a GPI input pin and a GPO output pin.
In an embodiment, in order to implement the power-up of the processor 120 after power-off, a first terminal of the pull-up resistor 142 is connected to the second voltage converter, and a second terminal of the pull-up resistor 142 is connected to a GPI pin of the PMIC. When the voltage of the first pin of the PMIC is less than a first preset voltage, the voltage of the first pin is increased by the second voltage converter and the pull-up resistor 142, so that the power management component circuit 130 sends an enable signal to the first voltage converter.
In practical application, after the processor 120 is powered off, the GPIO pin of the processor 120 is released, and a high-level state is output to the outside, that is, the GPIO pin of the processor 120 is disconnected from the GPI pin of the PMIC, at this time, the GPI pin of the PMIC is connected to the second voltage converter through the pull-up resistor 142, and the voltage of the GPI pin of the PMIC may be pulled up to 2.4V or more and is in a high-level state. The voltage level of the GPO pin of the PMIC is changed to a high level, and when the first voltage converter receives an enable signal (i.e., a high-level voltage signal) sent by the GPO pin of the PMIC, the voltage level of the enable input terminal of the first voltage converter is a high level, and at this time, the first voltage converter is reconnected with the processor 120 and supplies power to the processor. In this manner, the processor 120 completes the reboot after the power off.
In an embodiment, the second voltage converter is further configured to supply power to the PMIC. Here, a second voltage converter may be connected at a power supply input of the PMIC. Therefore, the input of an additional power supply device can be reduced, and the second voltage converter can provide normally-on power.
In one embodiment, as shown in fig. 3, the power management component circuit 130 includes an and circuit 131 and a delay circuit 132; two input ends of the and-gate circuit 131 are both connected to a GPI pin of the PMIC, and an output end of the and-gate circuit 131 is connected to an input end of the delay circuit 132; the output end of the delay circuit 132 is connected with the GPO pin of the PMIC; a GPO pin of the PMIC is connected to an enable input of the first voltage converter.
In practical application, the two input terminals of the and circuit 131 are in the same level state as the GPI pin of the PMIC, so that when the level state of the GPI pin of the PMIC is high, the level state of the output terminal of the and circuit 131 is also high; when the level state of the GPI pin of the PMIC is low, the level state of the output terminal of the and circuit 131 is low.
The delay circuit 132 may adopt a delay circuit for delaying a signal sending time in the related art, and in order to ensure that the processor 120 has enough time to store important configuration information before power-off after receiving a restart instruction, the preset delay time of the delay circuit 132 may be set according to actual needs and the time for the processor 120 to store information, so that the processor 120 stores important configuration information within the preset delay time.
As shown in fig. 4, before the processor 120 is powered off, i.e., before the time period T1, the first pin (i.e., GPIO) of the processor 120 and the first pin (i.e., GPI) of the power management component circuit 130 are in the same level state and are in the high level state; the level state of the second pin (i.e., GPO) of the power management component circuit 130 is also a high level state, which is the same as the level state of the enable input (i.e., EN pin) of the first power supply circuit 110, and the power output (i.e., the output of 3V3 in fig. 4) of the first power supply circuit 110 is also a high level state. In an embodiment of the present invention, 3V3 represents a voltage of 3.3V.
When the processor 120 receives the restart instruction, that is, the start time of the time period T1, the GPIO pin of the processor 120 and the GPI pin of the power management component circuit 130 start to be in the low level state, and at this time, due to the existence of the delay circuit 132, after the time period T1 preset by the delay circuit 132, that is, the end time of the time period T1, and at the same time, the start time of the time period T2 of the power-off duration of the first power supply circuit 110, the level state of the GPO pin of the power management component circuit 130 and the level state of the EN pin of the first power supply circuit 110 both become the low level state, and the power output terminal of the first power supply circuit 110 also correspondingly becomes the low level state, and at this time, the first power supply circuit 110 stops supplying power to the processor 120.
When the processor 120 is powered off, the end time of the time period T1 is also the start time of the time period T2, the GPI pin of the power management component circuit is connected to the second power supply 141 through the pull-up resistor 142, and the level state of the GPI pin of the power management component circuit 130 starts to change to the high level at the start time of the time period T2 when the first power supply circuit 110 is powered off, at this time, due to the existence of the delay circuit 132, the high level signal of the GPI pin of the power management component circuit 130 can be sent to the GPO pin of the power management component circuit 130 after the delay time period T1 preset by the delay circuit 132, and the GPO pin of the power management component circuit 130 can send the enable signal to change the level state of the power output terminal of the first power supply circuit 110 into the high level, so that the first power supply circuit 110 supplies power to the processor 120 again. Therefore, the power-off duration T2 of the first power supply circuit is the same as the preset delay duration T1 of the delay circuit 132.
In one embodiment, the processor 120 is configured to obtain a remote restart instruction through the network interface 121. In practical applications, the network interface 121 may be a fiber-optic communication interface or a wireless network interface, such as a bluetooth module, a ZigBee module, or the like.
In an embodiment, the first voltage converter is further configured to perform voltage conversion on a dc voltage input from an external power source, and apply the converted voltage to the processor 120. In an embodiment, the second voltage converter is further configured to perform voltage conversion on a dc voltage input by an external power source, and output the converted voltage. In practice, a second voltage converter applies the converted voltage to the PMIC to power the PMIC.
In practical application, the CPU is located on the master control single disk, the power supply of the CPU is a common direct current-to-direct current (DC-DC) power supply chip, namely, the DC-DC2 outputs 3.3V voltage, the DC-DC2 has an enable control EN pin, and the control EN pin is used for controlling the high and low level state of the pin and further controlling the output of the DC-DC2 to be turned on or turned off.
The PMIC (also called as a PMIC chip) is generally used for detecting all power supplies of the whole master control single disk, has no processor inside, low power consumption and low cost, and is a commonly used monitoring chip in circuit design; the power supply of the PMIC is provided by a direct current-to-direct current normally-open power supply chip, namely DC-DC1 is a normally-open power supply, and the PMIC is the only chip which is kept to supply power all the time on the whole master control single disk.
A GPIO pin of the CPU is connected to a GPI pin of the PMIC chip, and the GPI pin is connected to the DC-DC1 through a pull-up resistor; the GPO pin of the PMIC is connected to the EN control pin of DC-DC 1.
The PMIC comprises an AND gate circuit and a delay unit, and the delay time of the delay unit can be set according to needs.
The CPU is connected to the network via a network interface (also referred to as a communication interface) through which a cold restart instruction to the controller CPU can be issued remotely.
When the CPU works normally, the DC-DC2 outputs 3.3V voltage to supply power to the PMIC, and the power consumption of the PMIC is small; the DC-DC1 outputs 3.3V voltage to supply power to the CPU, thereby ensuring the normal work of the CPU. At this time, as shown in fig. 4, the GPIO pin of the CPU outputs a high level, and the GPI pin input of the PMIC is also a high level. The level signal input of a GPI pin is converted to a GPO pin to be output by the PMIC through an AND gate circuit and a delay unit, the level state of the GPO pin of the PMIC is high level, the GPO pin outputs a high level signal (namely sending an enabling signal) to an EN pin of the DC-DC1, and after the DC-DC1 is enabled, 3.3V voltage is output to supply power to the CPU.
When the CPU needs to be remotely cold restarted, a cold restart instruction is sent to the CPU through a network interface; after receiving the cold restart instruction, the CPU starts to store the current important configuration information and simultaneously outputs a low level signal to a GPIO pin of the CPU; and after a GPI pin of the PMIC receives the low-level signal and outputs the low-level signal to a GPO pin of the PMIC through an internal AND gate circuit and a delay unit, the GPO pin of the PMIC outputs the low-level signal, and an EN pin of the DC-DC2 receives the low-level signal (namely, an enable-removing signal), the DC-DC2 stops voltage output, and at the moment, the electrical connection with the CPU is disconnected.
At this time, the CPU is powered off, the GPIO pin of the CPU is released, the external state is a high impedance state, which is equivalent to disconnection from an internal circuit of the controller CPU, the GPI pin of the PMIC is connected to the DC-DC1 due to a pull-up resistor at this time, the GPIO pin of the CPU is in a high impedance state, the GPI pin of the PMIC is pulled up to a high level state of 3.3V by the DC-DC1 and the pull-up resistor, a GPI pin high level signal is output to the GPO pin through the internal and gate circuit and the delay unit, a GPO pin high level signal (i.e., an enable signal) is output to the EN pin of the DC-DC2, and after the DC-DC2 is enabled, a voltage of 3.3V is output to power the controller CPU.
The time of the cold start may be set in advance by a delay unit of the PMIC, or may use a default setting value of the delay unit. As can be seen from the description of fig. 4 in the above embodiment, the values of the delay time period T1 of the delay unit and the CPU power-off time period T2 are equal, and are the set delay time periods of the delay unit.
Therefore, the controller CPU completes the power-off cold restart of the controller CPU through a remote restart instruction; and moreover, the labor and material cost is saved, and the risk of the power supply system to the whole communication system can be reduced. In addition, a cold reboot of the controller can be achieved by remotely pairing the controller (also referred to as a processor) on the master control card, and based on an existing, more general power management chip (also referred to as a power management component circuit); the method plays a vital role in realizing cold restart of the controller for the unattended remote communication machine room.
Based on the above circuit, an embodiment of the present invention further provides a start control method, applied to a master control card, as shown in fig. 5, where the start control method includes the following steps:
step 501: the processor of the starting control circuit receives a remote restarting instruction and responds to the restarting instruction to output a first control signal; the restart instruction is used for instructing the processor to restart;
step 502: the power management component circuit of the starting control circuit receives the first control signal and responds to the first control signal to send a de-enabling signal to the first power supply circuit of the starting control circuit so as to enable the first power supply circuit to stop supplying power to the processor;
step 503: after a restart control circuit of the starting control circuit detects that the processor is powered off, a second control signal is sent to the power management component circuit;
step 504: and the power management component circuit receives the second control signal and responds to the second control signal to send an enabling signal to the first power supply circuit so as to enable the first power supply circuit to supply power to the processor again.
Therefore, the processor of the master control card completes the power-off cold restart of the processor through the remote restart instruction; and moreover, the labor and material cost is saved, and the risk of the power supply system to the whole communication system can be reduced. In addition, a cold reboot of the controller can be achieved by remotely pairing the controller (also referred to as a processor) on the master control card, and based on an existing, more general power management chip (also referred to as a power management component circuit); the method plays a vital role in realizing cold restart of the controller for the unattended remote communication machine room.
In an embodiment, the method may further include:
the restart control circuit detects the voltage of a first pin of the power management component circuit; a first pin of the power management component circuit receives a voltage signal output by a first pin of the processor;
determining that the processor has been powered down when it is detected that the voltage of the first pin of the power management component circuit is less than a first preset voltage.
In an embodiment, the method may further include:
when the voltage of the first pin of the power management component circuit is smaller than a first preset voltage, the voltage of the first pin of the power management component circuit is increased through the second power supply circuit and a pull-up resistor, so that the power management component circuit sends an enabling signal to the first power supply circuit; the first end of the pull-up resistor is connected with the second power supply circuit, and the second end of the pull-up resistor is connected with the first pin of the power management component.
In an embodiment, the method may further include:
and supplying power to the power management component circuit through the second power supply circuit.
In an embodiment, the method may further include:
the processor obtains a remote restart instruction through the communication interface.
In an embodiment, the method may further include:
and converting the direct-current voltage input by the external power supply through the first power supply circuit, and applying the converted voltage to the processor.
In an embodiment, the method may further include:
and the second power supply circuit is also used for converting the voltage of the direct current voltage input by the external power supply and outputting the converted voltage.
By the method, the processor of the master control card can complete the power-off cold restart of the processor of the master control card through the remote restart instruction; and moreover, the labor and material cost is saved, and the risk of the power supply system to the whole communication system can be reduced. In addition, a cold reboot of the controller can be achieved by remotely pairing the controller (also referred to as a processor) on the master control card, and based on an existing, more general power management chip (also referred to as a power management component circuit); the method plays a vital role in realizing cold restart of the controller for the unattended remote communication machine room.
It should be noted that: "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In addition, the technical solutions described in the embodiments of the present invention may be arbitrarily combined without conflict.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims (10)

1. A start control circuit, set on a master control card, comprising: the power supply device comprises a first power supply circuit, a processor, a power management component circuit and a restart control circuit; wherein the content of the first and second substances,
the first power supply circuit is used for supplying power to the processor;
the processor is used for receiving a remote restart instruction and responding to the restart instruction to output a first control signal; the restart instruction is used for instructing the processor to restart;
the power management component circuit is used for responding to the first control signal and sending a de-enabling signal to the first power supply circuit so as to enable the first power supply circuit to stop supplying power to the processor;
the restart control circuit is used for sending a second control signal to the power management component circuit after detecting that the processor is powered off;
the power management component circuit is further configured to send an enable signal to the first power supply circuit in response to the second control signal, so that the first power supply circuit supplies power to the processor again.
2. The circuit of claim 1, wherein the restart control circuit is configured to:
detecting a voltage of a first pin of the power management component circuit; a first pin of the power management component circuit receives a voltage signal output by a first pin of the processor;
determining that the processor has been powered down when it is detected that the voltage of the first pin of the power management component circuit is less than a first preset voltage.
3. The circuit of claim 2, wherein the restart control circuit comprises: a second power supply circuit and a pull-up resistor; wherein the content of the first and second substances,
when the voltage of the first pin of the power management component circuit is smaller than a first preset voltage, the voltage of the first pin of the power management component circuit is increased through the second power supply circuit and a pull-up resistor, so that the power management component circuit sends an enabling signal to the first power supply circuit;
and the first end of the pull-up resistor is connected with the second power supply circuit, and the second end of the pull-up resistor is connected with the first pin of the power management component.
4. The circuit of claim 3,
the second power supply circuit is also used for supplying power to the power management component circuit.
5. The circuit of any of claims 1 to 4, wherein the power management component circuit comprises an AND gate circuit and a delay circuit;
two input ends of the AND gate circuit are connected with a first pin of the power management component circuit, and the output end of the AND gate circuit is connected with the input end of the delay circuit; the output end of the delay circuit is connected with a second pin of the power management component circuit; and the second pin of the power management component circuit is connected with the enabling input end of the first power supply circuit.
6. The circuit according to any one of claims 1 to 4,
and the processor is used for acquiring a remote restart instruction through the communication interface.
7. The circuit according to any one of claims 1 to 4,
the first power supply circuit is further configured to perform voltage conversion on a direct current voltage input by an external power supply, and apply the converted voltage to the processor.
8. The circuit of claim 3 or 4,
the second power supply circuit is also used for converting the direct current voltage input by the external power supply and outputting the converted voltage.
9. A start control method is applied to a master control card, and is characterized by comprising the following steps:
the processor of the starting control circuit receives a remote restarting instruction and responds to the restarting instruction to output a first control signal; the restart instruction is used for instructing the processor to restart;
the power management component circuit of the starting control circuit receives the first control signal and responds to the first control signal to send a de-enabling signal to the first power supply circuit of the starting control circuit so as to enable the first power supply circuit to stop supplying power to the processor;
after a restart control circuit of the starting control circuit detects that the processor is powered off, a second control signal is sent to the power management component circuit;
and the power management component circuit receives the second control signal and responds to the second control signal to send an enabling signal to the first power supply circuit so as to enable the first power supply circuit to supply power to the processor again.
10. The method of claim 9, further comprising:
the restart control circuit detects the voltage of a first pin of the power management component circuit; a first pin of the power management component circuit receives a voltage signal output by a first pin of the processor;
determining that the processor has been powered down when it is detected that the voltage of the first pin of the power management component circuit is less than a first preset voltage.
CN202010739701.2A 2020-07-28 2020-07-28 Start control circuit and method Active CN111966195B (en)

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CN113612472B (en) * 2021-07-01 2024-05-10 上海爻火微电子有限公司 Level conversion circuit and electronic equipment

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