CN111954931B - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents

Semiconductor device with a semiconductor device having a plurality of semiconductor chips Download PDF

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Publication number
CN111954931B
CN111954931B CN201980018090.8A CN201980018090A CN111954931B CN 111954931 B CN111954931 B CN 111954931B CN 201980018090 A CN201980018090 A CN 201980018090A CN 111954931 B CN111954931 B CN 111954931B
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layer
gate electrode
gate
semiconductor layer
semiconductor device
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CN111954931A (en
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奥田聪志
绵引达郎
斋藤尚史
村冈宏记
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H01L27/0738—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with resistors only
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
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    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates

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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
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  • Thyristors (AREA)

Abstract

The reliability of the gate resistor element during high-temperature operation is improved. The semiconductor device is provided with a drift layer (1), a base layer (5), an emitter layer (9), a gate insulating film (7), a gate electrode (6A), a gate pad electrode (13), a first resistance layer (200), and a first nitride layer (300), wherein the resistance of the first resistance layer has a negative temperature coefficient, the first resistance layer is formed of amorphous silicon doped with hydrogen, and the first nitride layer is formed of a silicon nitride layer or an aluminum nitride layer.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips
Technical Field
The technology disclosed in the present specification relates to a semiconductor device.
Background
Inverters used in various places around industrial equipment, automobiles, electric railways, and the like are controlled by power modules and the like equipped with semiconductor switching elements such as metal-oxide-semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors (insulated gate bipolar transistor, IGBTs). In the energy saving of such an inverter, a reduction in power loss in a semiconductor element responsible for power control is indispensable.
In MOS power semiconductor devices such as IGBTs and power MOSFETs, it is demanded to reduce both high-temperature operation and power loss. As a method for achieving this, a method of controlling the temperature characteristic of a gate resistor interposed between a gate electrode and a driving circuit of a MOS type power semiconductor device is known.
As a method of controlling the temperature characteristics of the gate resistance, for example, a method of combining a resistance element having a negative temperature characteristic with a resistance element having a positive temperature characteristic to reduce the temperature variation of the gate resistance is known (for example, refer to patent documents 1 and 2).
Here, as a resistor element having a negative temperature characteristic, for example, amorphous silicon or microcrystalline silicon in which hydrogen is added as an impurity is known (for example, refer to non-patent document 1).
Patent document 1: international publication No. 2017/029748
Patent document 2: japanese patent No. 4791700
Non-patent document 1: chen Qingdong et al, optik 127 (2016) 7312-7318, "Activation energy study of intrinsic microcrystalline silicon thin film prepared by VHF-PECVD"
Disclosure of Invention
Problems to be solved by the invention
In the case of using a MOS power semiconductor device having a built-in gate resistor at a high temperature, if amorphous silicon having hydrogen as an impurity is used as a gate resistor having a negative temperature characteristic, there are cases in which: when the high temperature operation is performed, hydrogen is separated from amorphous silicon, and the temperature characteristic or resistance value of the gate resistor is changed, so that the reliability of the gate resistor is lowered.
The present application has been made in order to solve the above-described problems, and an object of the present application is to provide a technique for improving the reliability of a gate resistance during high-temperature operation.
Solution for solving the problem
A first aspect of the technology disclosed in the present specification includes: a drift layer of the first conductivity type; a second conductivity type underlayer formed on a surface layer of the drift layer; an emitter layer of a first conductivity type selectively formed on a surface layer of the base layer; a gate insulating film formed to be in contact with the base layer sandwiched between the drift layer and the emitter layer; a gate electrode formed in contact with the gate insulating film; a gate pad electrode formed to be separated from the gate electrode; a first resistive layer electrically connecting the gate electrode and the gate pad electrode; and a first nitride layer formed to cover an upper surface of the first resistance layer, wherein a resistance of the first resistance layer has a negative temperature coefficient, the first resistance layer is formed of amorphous silicon doped with hydrogen, and the first nitride layer is formed of a silicon nitride layer or an aluminum nitride layer.
A second aspect of the technology disclosed in the present specification includes: a drift layer of the first conductivity type; a second conductivity type underlayer formed on a surface layer of the drift layer; an emitter layer of a first conductivity type selectively formed on a surface layer of the base layer; a trench formed to penetrate the emitter layer and the base layer from the upper surface of the drift layer and to reach the drift layer; a gate insulating film formed along a bottom surface and side surfaces of the trench; a first gate electrode formed in the trench surrounded by the gate insulating film; and a first nitride layer formed to cover at least an upper surface of the first gate electrode, wherein a resistance of the first gate electrode has a negative temperature coefficient, the first gate electrode is formed of amorphous silicon doped with hydrogen, at least a portion of the first gate electrode contains 1% or more of hydrogen in an atomic composition ratio, and the first nitride layer is formed of a silicon nitride layer or an aluminum nitride layer.
A third aspect of the technology disclosed in the present specification includes: a drift layer of the first conductivity type; a second conductivity type underlayer formed on a surface layer of the drift layer; an emitter layer of a first conductivity type selectively formed on a surface layer of the base layer; a first trench and a plurality of second trenches formed to penetrate the base layer from an upper surface of the drift layer and to reach the drift layer; a third trench formed to penetrate the emitter layer and the base layer from the upper surface of the drift layer and to reach the drift layer; a gate insulating film formed along bottom surfaces and side surfaces of the first, second, and third trenches; a first gate electrode formed in the first trench surrounded by the gate insulating film; a second gate electrode formed in the second trench surrounded by the gate insulating film and in the third trench surrounded by the gate insulating film; and a nitride layer formed so as to cover at least an upper surface of the first gate electrode, wherein the second gate electrode in the third trench and the first gate electrode in the second trench are connected to a gate terminal, a resistance of the first gate electrode has a negative temperature coefficient, the first gate electrode is formed of amorphous silicon doped with hydrogen, at least a portion of the first gate electrode contains 1% or more of hydrogen in an atomic composition ratio, and the nitride layer is formed of silicon nitride or aluminum nitride.
ADVANTAGEOUS EFFECTS OF INVENTION
A first aspect of the technology disclosed in the present specification includes: a drift layer of the first conductivity type; a second conductivity type underlayer formed on a surface layer of the drift layer; an emitter layer of a first conductivity type selectively formed on a surface layer of the base layer; a gate insulating film formed to be in contact with the base layer sandwiched between the drift layer and the emitter layer; a gate electrode formed in contact with the gate insulating film; a gate pad electrode formed to be separated from the gate electrode; a first resistive layer electrically connecting the gate electrode and the gate pad electrode; and a first nitride layer formed to cover an upper surface of the first resistance layer, wherein a resistance of the first resistance layer has a negative temperature coefficient, the first resistance layer is formed of amorphous silicon doped with hydrogen, and the first nitride layer is formed of a silicon nitride layer or an aluminum nitride layer. According to this structure, since the first nitride layer is formed on the upper surface of the first resistance layer of amorphous silicon to which hydrogen is added, the detachment of hydrogen from the first resistance layer of amorphous silicon is reduced even during high-temperature operation. Therefore, variations in temperature characteristics and resistance values of the gate resistor element are suppressed, and reliability of the gate resistor element can be improved.
A second aspect of the technology disclosed in the present specification includes: a drift layer of the first conductivity type; a second conductivity type underlayer formed on a surface layer of the drift layer; an emitter layer of a first conductivity type selectively formed on a surface layer of the base layer; a trench formed to penetrate the emitter layer and the base layer from the upper surface of the drift layer and to reach the drift layer; a gate insulating film formed along a bottom surface and side surfaces of the trench; a first gate electrode formed in the trench surrounded by the gate insulating film; and a first nitride layer formed to cover at least an upper surface of the first gate electrode, wherein a resistance of the first gate electrode has a negative temperature coefficient, the first gate electrode is formed of amorphous silicon doped with hydrogen, at least a portion of the first gate electrode contains 1% or more of hydrogen in an atomic composition ratio, and the first nitride layer is formed of a silicon nitride layer or an aluminum nitride layer. According to such a structure, the first gate electrode having a negative temperature coefficient is formed in the trench, whereby the gate resistance can be sensitively changed with respect to a temperature change of the element. Thus, the current concentration can be suppressed, and the temperature rise of the element can be alleviated. Therefore, both improvement of reliability of the gate resistance and reduction of power loss can be achieved. In addition, by forming the first nitride layer on the upper surface of the first gate electrode, hydrogen desorption from the first gate electrode can be reduced. Thereby, the long-term reliability of the gate resistance can be improved.
A third aspect of the technology disclosed in the present specification includes: a drift layer of the first conductivity type; a second conductivity type underlayer formed on a surface layer of the drift layer; an emitter layer of a first conductivity type selectively formed on a surface layer of the base layer; a first trench and a plurality of second trenches formed to penetrate the base layer from an upper surface of the drift layer and to reach the drift layer; a third trench formed to penetrate the emitter layer and the base layer from the upper surface of the drift layer and to reach the drift layer; a gate insulating film formed along bottom surfaces and side surfaces of the first, second, and third trenches; a first gate electrode formed in the first trench surrounded by the gate insulating film; a second gate electrode formed in the second trench surrounded by the gate insulating film and in the third trench surrounded by the gate insulating film; and a nitride layer formed so as to cover at least an upper surface of the first gate electrode, wherein the second gate electrode in the third trench and the first gate electrode in the second trench are connected to a gate terminal, a resistance of the first gate electrode has a negative temperature coefficient, the first gate electrode is formed of amorphous silicon doped with hydrogen, at least a portion of the first gate electrode contains 1% or more of hydrogen in an atomic composition ratio, and the nitride layer is formed of silicon nitride or aluminum nitride. With this configuration, the reliability of the gate resistance during high-temperature operation can be improved.
The objects, features, aspects and advantages associated with the technology disclosed in the present specification will become more apparent from the detailed description and drawings shown below.
Drawings
Fig. 1 is a schematic cross-sectional view showing an example of the structure of an active region of a semiconductor device according to the embodiment.
Fig. 2 is a schematic cross-sectional view showing an example of a peripheral structure of a gate resistance region built in a semiconductor chip.
Fig. 3 is a schematic cross-sectional view showing an example of a peripheral structure of a gate resistance region built in a semiconductor chip.
Fig. 4 is a schematic cross-sectional view showing an example of a peripheral structure of a gate resistance region incorporated in a semiconductor chip according to the embodiment.
Fig. 5 is a schematic cross-sectional view showing an example of a peripheral structure of a gate resistance region incorporated in a semiconductor chip according to the embodiment.
Fig. 6 is a schematic cross-sectional view showing an example of a peripheral structure of a gate resistance region incorporated in a semiconductor chip according to the embodiment.
Fig. 7 is a schematic cross-sectional view showing an example of the structure of an active region of a semiconductor device according to the embodiment.
Fig. 8 is a schematic cross-sectional view showing a modification of the structure of the active region of the semiconductor device according to the embodiment.
Fig. 9 is a schematic cross-sectional view showing an example of the structure of an active region of a semiconductor device according to the embodiment.
Fig. 10 is a schematic cross-sectional view showing a modification of the structure of the active region of the semiconductor device according to the embodiment.
Fig. 11 is a schematic plan view showing an example of the peripheral structure of the gate resistance region.
Fig. 12 is a schematic cross-sectional view showing an example of a peripheral structure of a gate resistance region incorporated in a semiconductor chip according to the embodiment.
Fig. 13 is a schematic cross-sectional view showing an example of the structure of an active region of a semiconductor device according to the embodiment.
(description of the reference numerals)
1: a drift layer; 2: a buffer layer; 3: a collector layer; 4: a collector electrode; 5: a base layer; 6,6a,6b,6c,6d,6i: a gate electrode; 7: a gate insulating film; 8: an interlayer insulating film; 9: an emitter layer; 10: a contact layer; 11: an emitter electrode; 12: a well layer; 13: a gate pad electrode; 14: a contact hole; 15: a gate terminal; 16: an emitter terminal; 20: a groove; 21: an active gate; 22: a dummy gate; 23: an active dummy gate; 30 30a,30b,30c,30d,30i: a built-in grid resistor; 100 100a,100b,100c,100d,100e,100f,100g,100h,100i,100j: a semiconductor device; 200 200B,200C,200D,200E,200F,200G,200H,200I,200J,200K,201, 201D,201G,201H,202, 202D,202G,202H: a semiconductor layer; 300 300b,300c,300d,300e,300f,300g,300h,300I,300j,301, 400I: a nitride layer.
Detailed Description
Hereinafter, embodiments will be described with reference to the drawings.
The drawings are schematically shown, and the structure is omitted or simplified for convenience of description. The interrelationship of the size and position of the structures and the like shown in the different drawings is not necessarily precisely described, and may be appropriately changed. In addition, in the drawings such as a plan view which is not a cross-sectional view, shading may be added to facilitate understanding of the contents of the embodiments.
In the description shown below, the same reference numerals are given to the same components, and the names and functions are the same. Accordingly, a detailed description thereof is sometimes omitted in order to avoid repetition.
In the following description, even when terms such as "upper", "lower", "left", "right", "side", "bottom", "front" and "back" are used to indicate specific positions and directions, these terms are used for the convenience of understanding the contents of the embodiments, and are not related to the directions in actual practice.
In the following description, even when ordinal numbers such as "first" and "second" are used, these terms are used for the convenience of understanding the contents of the embodiments, and are not limited to the order or the like which may be generated by these ordinal numbers.
In the following description, n and p each represent a conductivity type of a semiconductor. In addition, n -- Indicated by the impurity concentration being lower than n - Concentration n of (2) - The expression is that the impurity concentration is lower than n, n + The expression is a concentration of impurities higher than n. Similarly, p - The expression is that the impurity concentration is lower than the concentration of p + The expression is a concentration of impurities higher than p.
In the following description, a first direction in a forward direction, which is a lamination of semiconductor layers to be described later, is referred to as an upward direction, and a second direction, which is a reverse direction of the forward direction, is referred to as a downward direction. The surface facing upward is referred to as an upper surface, and the surface facing downward is referred to as a lower surface.
In addition, at the followingIn the following description, the first conductivity type is set to n, n - 、n -- Or n + And set the second conductivity type as p, p - Or p + Which are illustrated, but they may be reversed.
< first embodiment >
Hereinafter, a semiconductor device according to this embodiment will be described. In this embodiment, an IGBT as an example of a semiconductor device will be described.
< Structure relating to semiconductor device >
Fig. 1 is a schematic cross-sectional view showing an example of the structure of an active region of a semiconductor device according to this embodiment.
As in the example shown in fig. 1, the semiconductor device 100 includes n - Silicon substrate is used as n - A drift layer 1 of a type. And at n - The surface layer of the drift layer 1 is formed with a p-type underlayer 5.
And, n is selectively formed on the surface layer of the p-type underlayer 5 + Emitter layers 9 and p + A contact layer 10 of the type.
In addition, the trench 20 is formed from n - Through n from the upper surface of the drift layer 1 + An emitter layer 9 of the type and a base layer 5 of the p type and up to n - A drift layer 1 of a type. A gate insulating film 7 is formed along the bottom and side surfaces of the trench 20, and a gate electrode 6 is formed in the trench 20 surrounded by the gate insulating film 7. In the gate electrode 6, for example, low-resistance polysilicon is used.
The trench 20 is routed in the depth direction of fig. 1, and is connected to a gate pad electrode (not shown).
An interlayer insulating film 8 covering the trench 20 is formed, and an interlayer insulating film 8 and an exposed n are formed + Emitter layer 9 and p + Emitter electrode 11 of contact layer 10.
In addition, at n - An n-type buffer layer 2 is formed on the lower surface of the drift layer 1, and a p-type buffer layer 2 is formed on the lower surface of the n-type buffer layer 2 + Collector layer 3, p + Collector layer 3 A collector electrode 4 is formed on the lower surface of (a).
In addition, in order to adjust the switching speed of the IGBT, a gate resistance is used. Conventionally, a desired resistive element is externally mounted to each of a gate pad electrode and a gate driving circuit external to a semiconductor chip.
On the other hand, in order to reduce the number of components of the external component, a resistor element may be incorporated in the semiconductor chip. Fig. 2 is a schematic cross-sectional view showing an example of a peripheral structure of a gate resistance region built in a semiconductor chip.
The gate electrode 6 is routed from the trench 20 of the active region of the example shown in fig. 1, pulled up to n at the end of the semiconductor chip - The upper surface of the drift layer 1 of the model. A p-type well layer 12 is formed on the lower surface of the pulled gate electrode 6 through a gate insulating film 7. An interlayer insulating film 8 is formed on the upper surface of the pulled gate electrode 6.
The gate wiring lead-around region where the gate electrode 6 and the gate pad electrode 13 are electrically connected becomes the built-in gate resistor 30. By adjusting the length of the gate wiring routing region, the resistance value of the built-in gate resistor 30 can be controlled. Further, the gate pad electrode 13 is formed to be in contact with the upper surface of the gate electrode 6.
Fig. 11 is a schematic plan view showing an example of the peripheral structure of the gate resistance region. The trench 20 extending from the active region is pulled up to n via the contact hole 14 - The surface of the drift layer 1 of the model. At n - The upper surface of the drift layer 1 is formed with a built-in gate resistor 30. The built-in gate resistor 30 is also connected to the gate pad electrode 13.
IGBTs are sought to achieve both high temperature operation and power loss reduction. To achieve this, it is necessary to control the temperature characteristics of the gate resistance, and the following method is considered: the temperature characteristics of the gate resistor are controlled by connecting a member having a negative temperature coefficient, such as a thermistor, whose resistance decreases with a rise in temperature, between the gate pad electrode of the IGBT and the gate drive circuit.
However, when the components are externally provided to the semiconductor chip, an increase in the number of components of the module is incurred. Therefore, a method of applying a material having a negative temperature coefficient, in which the resistance decreases with an increase in temperature, to a part or the whole of the internal gate resistor 30 is considered.
Accordingly, the oscillation of the off voltage or the surge voltage can be suppressed by maintaining a resistance of a certain level at a low temperature, and the switching loss can be suppressed by reducing the gate resistance at a high temperature. In this method, since a material having a negative temperature coefficient is incorporated in the semiconductor chip, the number of components is not increased.
As for the arrangement of connecting a resistance element having a negative temperature coefficient to a gate electrode of a semiconductor switching element, there has been conventionally studied a direction in which a gate resistance value with respect to temperature is fixed by combining the resistance element having a positive temperature coefficient (for example, patent document 1 or patent document 2).
However, a method in which the gate resistance as a whole has a negative temperature coefficient has not been studied. As a material whose resistance shows a negative temperature coefficient, for example, amorphous silicon or microcrystalline silicon in which hydrogen is added as an impurity is known as an example shown in non-patent document 1.
Fig. 3 is a schematic cross-sectional view showing an example of a peripheral structure built in a gate resistance region of a semiconductor chip in the case where these materials are used as built-in gate resistances.
As in the example shown in fig. 3, the semiconductor device 100A includes n - A drift layer 1 formed on n - A trench 20, a gate insulating film 7, a gate electrode 6A, an interlayer insulating film 8, a semiconductor layer 200, a nitride layer 300, a p-type well layer 12, an emitter electrode 11, a gate pad electrode 13, an n-type buffer layer 2, and a p-type drift layer 1 + A collector layer 3 and a collector electrode 4.
The gate insulating film 7 is pulled up from the bottom surface of the trench 20 and is also formed on n - The upper surface of the drift layer 1 of the model. A gate electrode 6A formed on n via a gate insulating film 7 - A part of the upper surface of the drift layer 1 of the profile and inside the trench 20. For example, low-resistance polysilicon is used for the gate electrode 6A.
Interlayer insulationA film 8 is formed on the upper surface of the gate electrode 6A. The semiconductor layer 200 is formed on n via the gate insulating film 7 - Part of the upper surface of the drift layer 1.
The nitride layer 300 is formed to cover a portion of the upper surface of the interlayer insulating film 8, a portion of the upper surface of the gate electrode 6A, and a portion of the upper surface of the semiconductor layer 200.
A p-type well layer 12 formed on the n-type semiconductor substrate - The lower surface of the gate insulating film 7 on the upper surface of the drift layer 1. The emitter electrode 11 is formed on a part of the upper surface of the interlayer insulating film 8. The gate pad electrode 13 is formed to cover a portion of the upper surface of the semiconductor layer 200.
In addition, at n - An n-type buffer layer 2 is formed on the lower surface of the drift layer 1, and a p-type buffer layer 2 is formed on the lower surface of the n-type buffer layer 2 + Collector layer 3, p + A collector electrode 4 is formed on the lower surface of the collector layer 3.
The semiconductor layer 200 is amorphous silicon or microcrystalline silicon doped with hydrogen having a negative temperature coefficient. At least a part of the semiconductor layer 200 contains 1% or more of hydrogen in an atomic composition ratio.
The amorphous silicon containing no hydrogen contains a large number of unbound bonds (dangling bonds), and thus a large number of defect levels are formed. Therefore, the dangling bonds are terminated by adding hydrogen, whereby semiconductor properties can be imparted. In this case, the amount of hydrogen to be added is at least 1% by atomic composition, and particularly preferably 10% or more.
The semiconductor layer 200 is formed between the gate pad electrode 13 and the gate electrode 6A, and constitutes a part or all of the built-in gate resistor 30A. The semiconductor layer 200 electrically connects the gate pad electrode 13 and the gate electrode 6A. The resistance value of the built-in gate resistor 30A is determined according to the length of the lead-in gate resistor 30A or the specific resistance value of the semiconductor layer 200.
The specific resistance of the semiconductor layer 200 is adjusted by adding hydrogen, or impurities such as phosphorus, boron, or arsenic in the semiconductor layer 200 at an arbitrary concentration. With this structure, the built-in gate resistor having a negative temperature coefficient can be formed with an arbitrary resistance value.
In addition, the higher the crystallization rate of the semiconductor layer 200 is, the higher the activation energy is, and therefore the temperature dependence of the resistance is reduced. Therefore, the temperature dependence of the resistance can be designed based on the crystallization rate of the semiconductor layer 200.
Regarding such amorphous silicon or microcrystalline silicon, for example, by using silane (SiH 4 ) With Phosphine (PH) 3 ) The mixed gas is produced by a plasma chemical vapor deposition (chemical vapor deposition, i.e., CVD) method, and the doping concentration of hydrogen or phosphorus can be adjusted according to the flow rate ratio of the gas.
In this embodiment, as in the example shown in fig. 3, the gate electrode 6A made of doped polysilicon or the like is directly connected to the semiconductor layer 200.
According to this structure, since no stray capacitance is added to the gate electrode 6A, the built-in gate resistor having a negative temperature coefficient can be formed without increasing the charge amount required for charging and discharging the gate electrode 6A.
The hydrogen in the semiconductor layer 200 is desorbed from the semiconductor layer 200 and released into the atmosphere when exposed to high temperature during the manufacturing process or in use of the semiconductor device. In this case, the resistance of the semiconductor layer 200 fluctuates, and therefore, there is a problem that the long-term reliability of the IGBT element is lowered. In recent years, since the operation assurance temperature of an IGBT has increased, long-term reliability under high-temperature operation has been strongly demanded.
Therefore, in order to suppress the hydrogen from being separated from the semiconductor layer 200, the nitride layer 300 is formed to cover the semiconductor layer 200. Silicon nitride (SiN) or aluminum nitride (AlN) is used in the nitride layer 300. The thickness of the nitride layer 300 is 10nm or more, and particularly preferably 50nm or more.
With this structure, the internal gate resistor 30A can have a negative temperature coefficient, and hydrogen can be prevented from being separated from the semiconductor layer 200. This can reduce the switching loss caused by the gate resistance of the semiconductor device having a negative temperature coefficient, and can improve the long-term reliability of the gate resistance.
< second embodiment >
A semiconductor device according to this embodiment will be described. In the following description, the same reference numerals are given to the same components as those described in the above-described embodiments, and detailed description thereof is omitted appropriately.
< Structure relating to semiconductor device >
Fig. 4 is a schematic cross-sectional view showing an example of a peripheral structure of a gate resistance region incorporated in a semiconductor chip according to the present embodiment.
As in the example shown in fig. 4, the semiconductor device 100B is formed of the semiconductor layer 200B in part or in whole of the built-in gate resistor 30B, as in the case of the first embodiment. The semiconductor layer 200B is amorphous silicon or microcrystalline silicon doped with hydrogen having a negative temperature coefficient. In the semiconductor layer 200B, an impurity such as phosphorus, boron, or arsenic may be doped at an arbitrary concentration.
A nitride layer 300B is formed on the upper surface of the semiconductor layer 200B. The nitride layer 300B is formed of silicon nitride (SiN) or aluminum nitride (AlN). The nitride layer 300B is formed to cover a portion of the upper surface of the interlayer insulating film 8, a portion of the upper surface of the gate electrode 6B, and a portion of the upper surface of the semiconductor layer 200B. A gate electrode 6B formed on n via a gate insulating film 7 - A part of the upper surface of the drift layer 1 of the profile and inside the trench 20.
In the present embodiment, a nitride layer 301 is formed on the lower surface of the semiconductor layer 200B. The nitride layer 301 is formed on the upper surface of the p-type well layer 12 through the gate insulating film 7.
With this structure, the hydrogen can be prevented from being released from the semiconductor layer 200B to the gate insulating film 7. This can improve the long-term reliability of the built-in gate resistor 30B. In addition, deterioration of the performance of the semiconductor device due to entry of hydrogen atoms into the gate insulating film 7 can be suppressed. This suppresses variation in the resistance value of the built-in gate resistor 30B and improves the reliability of the gate insulating film 7, thereby providing a semiconductor device with high long-term reliability.
< third embodiment >
A semiconductor device according to this embodiment will be described. In the following description, the same reference numerals are given to the same components as those described in the above-described embodiments, and detailed description thereof is omitted appropriately.
< Structure relating to semiconductor device >
Fig. 5 is a schematic cross-sectional view showing an example of a peripheral structure of a gate resistance region incorporated in a semiconductor chip according to the present embodiment.
In the semiconductor device 100C of the present embodiment, the semiconductor layer 200C constituting the built-in gate resistor 30C is vertically separated into 2 layers and stacked on a semiconductor substrate.
As in the example shown in fig. 5, the semiconductor layer 200C is formed on the upper surface of the p-type well layer 12 through the gate insulating film 7. The semiconductor layer 200C includes a semiconductor layer 201 formed to be in contact with the gate insulating film 7, and a semiconductor layer 202 formed on the upper surface of the semiconductor layer 201.
The semiconductor layer 201 is formed of amorphous silicon doped with hydrogen. On the other hand, the semiconductor layer 202 is formed of amorphous silicon or microcrystalline silicon having a higher crystallinity than the semiconductor layer 201. At least a part of the semiconductor layer 201 and the semiconductor layer 202 contains 1% or more of hydrogen in an atomic composition ratio.
In addition, in the semiconductor layer 201 and the semiconductor layer 202, impurities such as phosphorus, boron, and arsenic may be doped at arbitrary concentrations.
And, the nitride layer 300C is formed to cover the semiconductor layer 202. Silicon nitride (SiN) or aluminum nitride (AlN) is used in the nitride layer 300C. The nitride layer 300C is formed to cover a portion of the upper surface of the interlayer insulating film 8, a portion of the upper surface of the gate electrode 6C, and a portion of the upper surface of the semiconductor layer 202. A gate electrode 6C formed on n via a gate insulating film 7 - A part of the upper surface of the drift layer 1 of the profile and inside the trench 20.
According to such a structure, the semiconductor layer 202 and the nitride layer 300C can suppress hydrogen from being separated from the semiconductor layer 201. Therefore, the change in the size of the built-in gate resistor 30C with time can be suppressed, and a semiconductor device with high long-term reliability can be provided.
< fourth embodiment >
A semiconductor device according to this embodiment will be described. In the following description, the same reference numerals are given to the same components as those described in the above-described embodiments, and detailed description thereof is omitted appropriately.
< Structure relating to semiconductor device >
Fig. 6 is a schematic cross-sectional view showing an example of a peripheral structure of a gate resistance region incorporated in a semiconductor chip according to the present embodiment.
In the semiconductor device 100D in this embodiment mode, the semiconductor layer 201D is covered with the semiconductor layer 202D.
As in the example shown in fig. 6, the semiconductor layer 200D includes a semiconductor layer 201D and a semiconductor layer 202D formed on the upper surface, the side surface, and the lower surface of the semiconductor layer 201D.
The semiconductor layer 201D is formed of amorphous silicon doped with hydrogen. On the other hand, the semiconductor layer 202D is formed of amorphous silicon or microcrystalline silicon having a higher crystallinity than the semiconductor layer 201D. At least a part of the semiconductor layer 201D and the semiconductor layer 202D contains 1% or more of hydrogen in an atomic composition ratio.
In addition, in the semiconductor layer 201D and the semiconductor layer 202D, impurities such as phosphorus, boron, and arsenic may be doped at an arbitrary concentration.
And, the nitride layer 300D is formed to cover the semiconductor layer 202D. Silicon nitride (SiN) or aluminum nitride (AlN) is used in the nitride layer 300D. The nitride layer 300D is formed to cover a part of the upper surface of the interlayer insulating film 8, a part of the upper surface of the gate electrode 6D, and a part of the upper surface of the semiconductor layer 202D. A gate electrode 6D formed on n via a gate insulating film 7 - A part of the upper surface of the drift layer 1 of the profile and inside the trench 20.
In the case of manufacturing the structure of the example shown in fig. 6, first, the semiconductor layer 202D is formed in a region to become the built-in gate resistor 30D. Then, using a photolithography method, the semiconductor layer 201D is formed only in a partial region of the upper surface of the semiconductor layer 202D. Thereafter, the semiconductor layer 202D is formed again over the entire region where the gate resistor 30D is built.
With such a structure, hydrogen can be further prevented from being separated from the semiconductor layer 201D. In addition, the size of the built-in gate resistor 30D can be suppressed from varying with time. Thus, a semiconductor device with high long-term reliability can be provided.
As a modification of the structure according to the present embodiment, the semiconductor layer 202D may be formed only on the upper portion of the semiconductor layer 201D and the lower portion of the semiconductor layer 201D. In this case as well, an effect of suppressing the hydrogen from being separated from the semiconductor layer 201D can be obtained.
< modification of the first to fourth embodiments >
In the above-described embodiment, the trench gate type IGBT is shown as an example of the switching element, but the above-described embodiment can be applied even to a planar type IGBT or MOSFET.
< fifth embodiment >
A semiconductor device according to this embodiment will be described. In the following description, the same reference numerals are given to the same components as those described in the above-described embodiments, and detailed description thereof is omitted appropriately.
< Structure relating to semiconductor device >
Fig. 7 is a schematic cross-sectional view showing an example of the structure of an active region of the semiconductor device according to the present embodiment.
In the semiconductor device 100E according to the present embodiment, a part or the whole of the gate electrode 6 buried in the trench 20 is replaced with the semiconductor layer 200E.
The peripheral structure of the gate resistance region of the semiconductor device according to the present embodiment may be any of the structures of the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment. That is, any configuration of examples shown in fig. 2, 3, 4, 5, and 6 may be used.
The semiconductor layer 200E is amorphous silicon or microcrystalline silicon doped with hydrogen having a negative temperature coefficient. In the semiconductor layer 200E, an impurity such as phosphorus, boron, or arsenic may be doped at an arbitrary concentration.
The semiconductor layer 200E is formed in the trench 20 surrounded by the gate insulating film 7. At least a part of the semiconductor layer 200E contains 1% or more of hydrogen in an atomic composition ratio.
A nitride layer 300E is formed on the upper surface of the semiconductor layer 200E in the trench 20. Silicon nitride (SiN) or aluminum nitride (AlN) is used in the nitride layer 300E.
The nitride layer 300E suppresses the hydrogen from being separated from the semiconductor layer 200E, and suppresses the long-term variation in the gate resistance.
In addition, during the switching operation of the IGBT, current is concentrated on the surface side of the switching element, and heat generation is likely to occur. By providing the semiconductor layer 200E having a negative temperature coefficient in the vicinity of such a portion where heat generation occurs, the gate resistance can be sensitively changed with respect to the heat generation of the semiconductor device.
In this structure, when a current deviation occurs in the surface of the semiconductor substrate and a current is concentrated at a specific portion, heat generation at the portion increases. Accordingly, the resistance of the semiconductor layer 200E decreases, and thus the switching speed of the cell region increases and the energization time decreases.
Thus, since current concentration is suppressed, element destruction due to excessive heat generation or current concentration of the element can be suppressed. Further, since the temperature rise of the switching element is suppressed, the switching loss and the conduction loss in the actual operation can be reduced.
As described above, according to the configuration of the present embodiment, the improvement of the long-term reliability of the semiconductor device 100E can be achieved together with the reduction of the power loss.
Fig. 8 is a schematic cross-sectional view showing a modification of the structure of the active region of the semiconductor device according to the present embodiment.
In the semiconductor device 100F, a part or the whole of the gate electrode 6 buried in the trench 20 is replaced with the semiconductor layer 200F.
The semiconductor layer 200F is amorphous silicon or microcrystalline silicon doped with hydrogen having a negative temperature coefficient. In the semiconductor layer 200F, an impurity such as phosphorus, boron, or arsenic may be doped at an arbitrary concentration.
A nitride layer 300F is formed on the upper surface, side surfaces, and bottom surface of the semiconductor layer 200F in the trench 20. Silicon nitride (SiN) or aluminum nitride (AlN) is used in the nitride layer 300F.
According to such a structure, the hydrogen can be prevented from being separated from the semiconductor layer 200F, and thus the long-term reliability of the gate resistance can be improved.
< sixth embodiment >
A semiconductor device according to this embodiment will be described. In the following description, the same reference numerals are given to the same components as those described in the above-described embodiments, and detailed description thereof is omitted appropriately.
< Structure relating to semiconductor device >
Fig. 9 is a schematic cross-sectional view showing an example of the structure of an active region of the semiconductor device according to the present embodiment.
In the semiconductor device 100G according to the present embodiment, a part or the whole of the gate electrode 6 buried in the trench 20 is replaced with the semiconductor layer 200G.
As in the example shown in fig. 9, the semiconductor layer 200G includes a semiconductor layer 201G and a semiconductor layer 202G formed on the upper surface of the semiconductor layer 201G.
The semiconductor layer 201G is formed of amorphous silicon doped with hydrogen. On the other hand, the semiconductor layer 202G is formed of amorphous silicon or microcrystalline silicon having a higher crystallinity than the semiconductor layer 201G. At least a part of the semiconductor layer 201G and the semiconductor layer 202G contains 1% or more of hydrogen in an atomic composition ratio.
In addition, in the semiconductor layer 201G and the semiconductor layer 202G, impurities such as phosphorus, boron, and arsenic may be doped at an arbitrary concentration.
A nitride layer 300G is formed on the upper surface of the semiconductor layer 202G in the trench 20. Silicon nitride (SiN) or aluminum nitride (AlN) is used in the nitride layer 300G.
The nitride layer 300G suppresses the hydrogen from being separated from the semiconductor layer 200G, and suppresses the long-term variation in the gate resistance.
According to such a structure, the semiconductor layer 202G formed on the upper surface of the semiconductor layer 201G suppresses the hydrogen from escaping from the semiconductor layer 201G, and thus the reliability of the built-in gate resistor is improved.
Fig. 10 is a schematic cross-sectional view showing a modification of the structure of the active region of the semiconductor device according to the present embodiment.
In the semiconductor device 100H, a part or the whole of the gate electrode 6 buried in the trench 20 is replaced with the semiconductor layer 200H.
As in the example shown in fig. 10, the semiconductor layer 200H includes a semiconductor layer 201H and a semiconductor layer 202H formed on the upper surface of the semiconductor layer 201H.
The semiconductor layer 201H is formed of amorphous silicon doped with hydrogen. On the other hand, the semiconductor layer 202H is formed of amorphous silicon or microcrystalline silicon having a higher crystallinity than the semiconductor layer 201H. At least a part of the semiconductor layer 201H and the semiconductor layer 202H contains 1% or more of hydrogen in an atomic composition ratio.
In addition, in the semiconductor layer 201H and the semiconductor layer 202H, impurities such as phosphorus, boron, and arsenic may be doped at an arbitrary concentration.
A nitride layer 300H is formed on the upper surface, side surfaces, and bottom surface of the semiconductor layer 200H in the trench 20. That is, the nitride layer 300H is formed so as to cover the upper surface and the side surfaces of the semiconductor layer 202H, and the side surfaces and the bottom surface of the semiconductor layer 201H. Silicon nitride (SiN) or aluminum nitride (AlN) is used in the nitride layer 300H.
According to such a structure, the hydrogen can be prevented from being separated from the semiconductor layer 200H, and thus the long-term reliability of the gate resistance can be improved.
< seventh embodiment >
A semiconductor device according to this embodiment will be described. In the following description, the same reference numerals are given to the same components as those described in the above-described embodiments, and detailed description thereof is omitted appropriately.
< Structure relating to semiconductor device >
Fig. 12 is a schematic cross-sectional view showing an example of a structure around a gate resistance region incorporated in a semiconductor chip according to the present embodiment.
As in the example shown in fig. 12, in the semiconductor device 100I, siO as the gate insulating film 7 is formed in a part or the whole of a region directly below the semiconductor layer 200I (first resistance layer) having a negative temperature coefficient and constituting the built-in gate resistance 30I 2 The film is removed, and a nitride layer 400I (second nitride layer) including a silicon nitride or aluminum nitride film is formed.
As in the example shown in fig. 12, the semiconductor layer 200I is formed on the upper surface of the p-type well layer 12 through the nitride layer 400I. That is, the nitride layer 400I is formed in direct contact with the upper surface of the p-type well layer 12.
The semiconductor layer 200I is amorphous silicon or microcrystalline silicon doped with hydrogen having a negative temperature coefficient. In the semiconductor layer 200I, phosphorus, boron, arsenic, or the like may be doped at an arbitrary concentration.
And, the nitride layer 300I is formed to cover the semiconductor layer 200I. Silicon nitride (SiN) or aluminum nitride (AlN) is used in the nitride layer 300I. The nitride layer 300I is formed to cover a portion of the upper surface of the interlayer insulating film 8, a portion of the upper surface of the gate electrode 6I, and a portion of the upper surface of the semiconductor layer 200I. A gate electrode 6I formed on n via a gate insulating film 7 - A part of the upper surface of the drift layer 1 of the profile and inside the trench 20.
Nitride has a silicon oxide with silicon oxide (SiO) 2 And a thermal conductivity of about one order to about two orders of magnitude higher than the phase. Therefore, heat generated in the active region efficiently reaches the semiconductor layer 200I through the nitride layer 400I, whereby a temperature difference between the active region and the resistive layer (semiconductor layer 200I) can be reduced.
This can improve the traceability of the resistance change of the resistance layer (semiconductor layer 200I) to the temperature change. In addition, the nitride layer 400I can suppress the hydrogen from being released from the resistive layer (the semiconductor layer 200I), and thus can also improve the long-term reliability of the gate resistance.
< eighth embodiment >
A semiconductor device according to this embodiment will be described. In the following description, the same reference numerals are given to the same components as those described in the above-described embodiments, and detailed description thereof is omitted appropriately.
< Structure relating to semiconductor device >
Fig. 13 is a schematic cross-sectional view showing an example of the structure of an active region of the semiconductor device according to the present embodiment.
As in the example shown in fig. 13, n is given to the semiconductor device 100J as the trench gate type semiconductor device - Silicon substrate is used as n - A drift layer 1 of a type. And at n - The surface layer of the drift layer 1 is formed with a p-type underlayer 5.
Here, trench gates in a trench gate type semiconductor device are classified into three types. The first is an active gate 21 (third trench) in which a channel is formed in a sidewall on one side or both sides. In fig. 13, an active gate 21 is connected to a gate terminal 15. The second is a dummy gate 22 (second trench) connected to the floating potential or the emitter potential without being connected to the gate electrode. In fig. 13, the dummy gate 22 is connected to the emitter terminal 16. The third is an active dummy gate 23 (first trench) connected to the gate electrode, but not forming a channel in the sidewall. In fig. 13, an active dummy gate 23 is connected to the gate terminal 15.
In the present embodiment, the gate electrode buried in the trench of the active dummy gate 23 is replaced with the semiconductor layer 200J (first gate electrode) and the nitride layer 300J on the upper surface of the semiconductor layer 200J.
The semiconductor layer 200J is amorphous silicon or microcrystalline silicon doped with hydrogen having a negative temperature coefficient. In the semiconductor layer 200J, phosphorus, boron, arsenic, or the like may be doped at an arbitrary concentration. At least a part of the semiconductor layer 200J contains 1% or more of hydrogen in an atomic composition ratio.
In addition, the nitride layer 300J is formed of silicon nitride or aluminum nitride.
On the other hand, a semiconductor layer 200K (second gate electrode) having a small resistance change with respect to temperature is embedded in the active gate electrode 21 and the dummy gate electrode 22. The semiconductor layer 200K is, for example, polysilicon doped with boron or phosphorus at a high concentration.
According to such a configuration, the resistance inside the active dummy gate 23 becomes smaller as the temperature increases. Therefore, the switching speed of the entire element increases. This can reduce switching loss at high temperatures.
On the other hand, the resistance inside the active gate 21 does not change depending on the temperature, and therefore the timing at which the channel is turned on or off does not depend on the temperature. If the semiconductor layer 200J having a negative temperature coefficient is applied to the internal electrode of the active gate electrode 21, in the case where heat is locally generated, since the channel of this region is preferentially turned on, current is concentrated, and there is a possibility that the element is broken.
On the other hand, according to the present embodiment, the switching speed of the active gate 21 is fixed independent of temperature. Thus, even at a high temperature, a current can be uniformly flowed in the active region, and thus the reliability of the semiconductor device can be improved.
< modification of the first to eighth embodiments >
In the above-described embodiments, n is - The material of the drift layer 1 envisages n - A silicon substrate of the type, but n - The material of the drift layer 1 is not limited to silicon, and may be, for example, gallium nitride, silicon carbide, aluminum nitride, diamond, gallium oxide, or other wide band gap semiconductor.
Here, the wide bandgap semiconductor generally means a semiconductor having a forbidden band width of about 2eV or more, and group III nitrides such as gallium nitride (GaN), group II oxides such as zinc oxide (ZnO), group II chalcogenides such as zinc selenide (ZnSe), diamond, silicon carbide, and the like are known.
In the above-described embodiment, the trench gate type IGBT is shown as an example of the switching element, but the above-described embodiment can be applied even to a vertical type MOS transistor, a reverse-conduction type IGBT (RC-IGBT), or the like.
< effects of the embodiments described above >
Next, an example of the effect produced by the above-described embodiment will be shown. In the following description, the effects are described based on the specific configuration of the example shown in the embodiment described above, but other specific configurations of the example shown in the description of the present application may be substituted within a range where the same effects are produced.
The substitution may be performed in a plurality of embodiments. That is, the same effects may be produced by combining the respective configurations of the examples shown in the different embodiments.
According to the above embodiment, the semiconductor device includes n - Drift layer 1 of type, underlayer 5 of type p, n + An emitter layer 9, a gate insulating film 7, a gate electrode 6A, a gate pad electrode 13, a first resistance layer, and a first nitride layer. Here, the first resistance layer corresponds to at least one of the semiconductor layer 200, the semiconductor layer 200B, the semiconductor layer 201, and the semiconductor layer 201D, for example. In addition, the first nitride layer corresponds to at least one of the nitride layer 300, the nitride layer 300B, the nitride layer 300C, and the nitride layer 300D, for example. A p-type base layer 5 formed on n - A surface layer of the drift layer 1. n is n + The emitter layer 9 of the type is selectively formed on the surface layer of the base layer 5 of the p-type. The gate insulating film 7 is formed as n-layer - Drift layers 1 and n + The p-type base layer 5 sandwiched by the emitter layers 9 of the type is in contact. The gate electrode 6A is formed in contact with the gate insulating film 7. The gate pad electrode 13 is formed separately from the gate electrode 6A. The semiconductor layer 200 electrically connects the gate electrode 6A and the gate pad electrode 13. The nitride layer 300 is formed to cover the upper surface of the semiconductor layer 200. Also, the resistance of the semiconductor layer 200 has a negative temperature coefficient. In addition, the semiconductor layer 200 is formed of amorphous silicon doped with hydrogen. In addition, the nitride layer 300 is formed of a silicon nitride layer or an aluminum nitride layer.
According to this structure, since the nitride layer 300 is formed on the upper surface of the amorphous silicon semiconductor layer 200 to which hydrogen is added, the detachment of hydrogen from the amorphous silicon semiconductor layer 200 is reduced even during high-temperature operation. Therefore, variations in the temperature characteristics and resistance value of the gate resistor are suppressed, and the reliability of the gate resistor can be improved.
In addition, other structures than those shown as examples in the present description can be omitted as appropriate. That is, the above-described effects can be produced by providing at least these structures.
However, even in the case where at least one of the other structures of the examples shown in the present specification is appropriately added to the structure described above, that is, in the case where other structures of the examples shown in the present specification, which are not mentioned as the structure described above, are appropriately added, the same effects can be produced.
In addition, according to the above-described embodiment, the semiconductor device includes the trench 20, and the trench 20 is formed from n - Through n from the upper surface of the drift layer 1 + Emitter layer 9 of the type and base layer 5 of the p type to n - A drift layer 1 of a type. The gate insulating film 7 is formed along the bottom and side surfaces of the trench 20. In addition, the gate electrode 6A is formed in the trench 20 surrounded by the gate insulating film 7. According to this structure, hydrogen is reduced from being separated from the semiconductor layer 200 which is amorphous silicon even in the high-temperature operation. Therefore, variations in the temperature characteristics and resistance value of the gate resistor are suppressed, and the reliability of the gate resistor can be improved.
In addition, according to the above-described embodiment, at least a part of the semiconductor layer 200 contains 1% or more of hydrogen in an atomic composition ratio. According to this structure, since the nitride layer 300 is formed on the upper surface of the amorphous silicon semiconductor layer 200 to which hydrogen is added, the detachment of hydrogen from the amorphous silicon semiconductor layer 200 is reduced even during high-temperature operation.
In addition, according to the above-described embodiment, the gate electrode 6A is formed of polysilicon. According to this structure, since the nitride layer 300 is formed on the upper surface of the amorphous silicon semiconductor layer 200 to which hydrogen is added, the detachment of hydrogen from the amorphous silicon semiconductor layer 200 is reduced even during high-temperature operation.
In addition, according to the above-described embodiment, the semiconductor device includes the second nitride layer formed so as to cover the lower surface of the semiconductor layer 200B. The second nitride layer corresponds here, for example, to nitride layer 301. With this structure, the hydrogen can be prevented from being released from the semiconductor layer 200B to the gate insulating film 7. This can improve the long-term reliability of the built-in gate resistor 30B. In addition, deterioration of the performance of the semiconductor device due to entry of hydrogen atoms into the gate insulating film 7 can be suppressed.
In addition, according to the above-described embodiment, the semiconductor device includes the second resistive layer formed on the upper surface of the semiconductor layer 201. Here, the second resistance layer corresponds to the semiconductor layer 202, for example. In addition, the nitride layer 300C is formed to cover the upper surface of the semiconductor layer 202. The semiconductor layer 201 and the semiconductor layer 202 contain 1% or more of hydrogen in an atomic composition ratio. In addition, the crystallization rate of the semiconductor layer 202 is higher than that of the semiconductor layer 201. According to such a structure, the semiconductor layer 202 and the nitride layer 300C can suppress hydrogen from being separated from the semiconductor layer 201. Therefore, the change in the size of the built-in gate resistor 30C with time can be suppressed, and a semiconductor device with high long-term reliability can be provided.
In addition, according to the above-described embodiment, the semiconductor device includes the second resistor layer formed on the upper surface, the side surface, and the lower surface of the semiconductor layer 201D. Here, the second resistance layer corresponds to the semiconductor layer 202D, for example. In addition, the nitride layer 300D is formed to cover the upper surface of the semiconductor layer 202D. The semiconductor layer 201D and the semiconductor layer 202D contain 1% or more of hydrogen in an atomic composition ratio. In addition, the crystallization rate of the semiconductor layer 202D is higher than that of the semiconductor layer 201D. According to such a structure, the semiconductor layer 202D and the nitride layer 300D can suppress hydrogen from being separated from the semiconductor layer 201D.
In addition, according to the embodiment described above, the first resistive layer is amorphous silicon containing 1% or more of hydrogen in an atomic composition ratio. The second resistive layer is microcrystalline silicon containing 1% or more of hydrogen in an atomic composition ratio. According to such a structure, the second resistive layer and the first nitride layer can suppress hydrogen from being separated from the first resistive layer.
In addition, according to the above-described embodiment, the semiconductor device includes n - Drift layer 1 of type, underlayer 5 of type p, n + An emitter layer 9, a trench 20, a gate insulating film 7, a first gate electrode, and a first nitride layer. Here, the first gate electrode corresponds to at least one of the semiconductor layer 200E, the semiconductor layer 200F, the semiconductor layer 201G, and the semiconductor layer 201H, for example. In addition, the first nitride layer corresponds to at least one of the nitride layer 300E, the nitride layer 300F, the nitride layer 300G, and the nitride layer 300H, for example. A p-type base layer 5 formed on n - A surface layer of the drift layer 1. n is n + The emitter layer 9 of the type is selectively formed on the surface layer of the base layer 5 of the p-type. The trench 20 is formed from n - Through n from the upper surface of the drift layer 1 + Emitter layer 9 of the type and base layer 5 of the p type to n - A drift layer 1 of a type. The gate insulating film 7 is formed along the bottom and side surfaces of the trench 20. The semiconductor layer 200E is formed in the trench 20 surrounded by the gate insulating film 7. The nitride layer 300E is formed to cover at least the upper surface of the semiconductor layer 200E. Further, the resistance of the semiconductor layer 200E has a negative temperature coefficient. In addition, the semiconductor layer 200E is formed of amorphous silicon doped with hydrogen. At least a part of the semiconductor layer 200E contains 1% or more of hydrogen in an atomic composition ratio. In addition, the nitride layer 300E is formed of a silicon nitride layer or an aluminum nitride layer. According to such a structure, the semiconductor layer 200E having a negative temperature coefficient is formed as a gate electrode in the trench 20, whereby the gate resistance can be sensitively changed with respect to a temperature change of the element. Thus, the current concentration can be suppressed, and the temperature rise of the element can be alleviated. Therefore, both improvement of reliability of the gate resistance and reduction of power loss can be achieved. In addition, by forming the nitride layer 300E on the upper surface of the semiconductor layer 200E, hydrogen desorption from the semiconductor layer 200E can be reduced. Thereby, the long-term reliability of the gate resistance can be improved.
In addition, other structures than those shown as examples in the present description can be omitted as appropriate. That is, the above-described effects can be produced by providing at least these structures.
However, even in the case where at least one of the other structures of the examples shown in the present specification is appropriately added to the structure described above, that is, in the case where other structures of the examples shown in the present specification, which are not mentioned as the structure described above, are appropriately added, the same effects can be produced.
In addition, according to the above-described embodiment, the nitride layer 300F is formed so as to cover the upper surface, the side surfaces, and the bottom surface of the semiconductor layer 200F. According to such a structure, the hydrogen can be prevented from being separated from the semiconductor layer 200F, and thus the long-term reliability of the gate resistance can be improved.
In addition, according to the above-described embodiment, the semiconductor device includes the second gate electrode formed on the upper surface of the first gate electrode. Here, the second gate electrode corresponds to at least one of the semiconductor layer 202G and the semiconductor layer 202H, for example. The nitride layer 300G is formed to cover at least the upper surface of the semiconductor layer 202G. The semiconductor layer 201G and the semiconductor layer 202G contain 1% or more of hydrogen in an atomic composition ratio. In addition, the crystallization rate of the semiconductor layer 202G is higher than that of the semiconductor layer 201G. According to such a structure, the semiconductor layer 202G formed on the upper surface of the semiconductor layer 201G suppresses the hydrogen from escaping from the semiconductor layer 201G, and thus the reliability of the built-in gate resistor is improved.
In addition, according to the above embodiment, the semiconductor layer 201G is amorphous silicon containing 1% or more of hydrogen in an atomic composition ratio. The semiconductor layer 202G is microcrystalline silicon containing 1% or more of hydrogen in an atomic composition ratio. According to such a structure, the semiconductor layer 202G formed on the upper surface of the semiconductor layer 201G suppresses the hydrogen from escaping from the semiconductor layer 201G, and thus the reliability of the built-in gate resistor is improved.
In addition, according to the above-described embodiment, the nitride layer 300H is formed so as to cover the upper surface and the side surface of the semiconductor layer 202H, and the side surface and the bottom surface of the semiconductor layer 201H. According to such a structure, the outer peripheries of the semiconductor layer 201H and the semiconductor layer 202H are covered with the nitride layer 300H, whereby the hydrogen can be prevented from being separated from the semiconductor layer 200H, and thus the long-term reliability of the gate resistance can be improved.
In addition, according to the above-described embodiment, the semiconductor device includes the gate pad electrode 13, the resistive layer, and the second nitride layer. Here, the resistive layer corresponds to at least one of the semiconductor layer 200, the semiconductor layer 200B, the semiconductor layer 201, and the semiconductor layer 201D, for example. In addition, the second nitride layer corresponds to at least one of the nitride layer 300, the nitride layer 300B, the nitride layer 300C, and the nitride layer 300D, for example. The gate pad electrode 13 is formed separately from the semiconductor layer 200E. The semiconductor layer 200 electrically connects the semiconductor layer 200E and the gate pad electrode 13. The nitride layer 300 is formed to cover the upper surface of the semiconductor layer 200. Also, the resistance of the semiconductor layer 200 has a negative temperature coefficient. In addition, the semiconductor layer 200 is formed of amorphous silicon doped with hydrogen. In addition, the nitride layer 300 is formed of a silicon nitride layer or an aluminum nitride layer. According to this structure, since the nitride layer 300 is formed on the upper surface of the amorphous silicon semiconductor layer 200 to which hydrogen is added, the detachment of hydrogen from the amorphous silicon semiconductor layer 200 is reduced even during high-temperature operation. Therefore, variations in the temperature characteristics and resistance value of the gate resistor are suppressed, and the reliability of the gate resistor can be improved.
< modification of the above-described embodiment >
In the above-described embodiments, the materials, dimensions, shapes, relative arrangement relationships, implementation conditions, and the like of the respective constituent elements are described in some cases, but these are examples in all respects, and are not limited to what is described in the present specification.
Accordingly, numerous modifications and equivalents not shown are conceivable within the scope of the technology disclosed in the present specification. For example, the case where at least one component is deformed, added or omitted, and the case where at least one component of at least one embodiment is extracted and combined with components of other embodiments are included.
Each of the structural elements in the above-described embodiments is a conceptual unit, and the present application includes a case where one structural element is constituted by a plurality of structures, a case where one structural element corresponds to a part of a certain structure, and a case where a plurality of structural elements are provided in a single structure within the scope of the technology disclosed in the present specification.
In the above-described embodiments, each of the structural elements includes structures having other structures or shapes as long as the same function is exhibited.
The description in the present specification is referred to for all the purposes related to the present technology, and should not be construed as conventional.
In the above-described embodiments, when the material name and the like are described without particular designation, other additives, for example, an alloy and the like are contained in the material unless contradiction occurs.

Claims (10)

1. A semiconductor device is provided with:
a drift layer of the first conductivity type;
a second conductivity type underlayer formed on a surface layer of the drift layer;
an emitter layer of a first conductivity type selectively formed on a surface layer of the base layer;
a gate insulating film formed to be in contact with the base layer sandwiched between the drift layer and the emitter layer;
a gate electrode formed in contact with the gate insulating film;
a gate pad electrode formed to be separated from the gate electrode;
a first resistive layer electrically connecting the gate electrode and the gate pad electrode; and
a first nitride layer formed to cover an upper surface of the first resistive layer,
wherein the resistance of the first resistive layer has a negative temperature coefficient,
the first resistive layer is formed of amorphous silicon doped with hydrogen,
The first nitride layer is formed of a silicon nitride layer or an aluminum nitride layer,
the semiconductor device further includes a second resistive layer formed on an upper surface of the first resistive layer,
the first nitride layer is formed to cover an upper surface of the second resistive layer,
the first resistance layer and the second resistance layer contain hydrogen in an atomic composition ratio of 1% or more,
the second resistive layer has a higher crystallinity than the first resistive layer.
2. The semiconductor device according to claim 1, wherein,
the second resistor layer is formed on the upper surface, the side surface and the lower surface of the first resistor layer.
3. The semiconductor device according to claim 1 or 2, wherein,
the second resistance layer is microcrystalline silicon containing 1% or more of hydrogen in an atomic composition ratio.
4. The semiconductor device according to claim 1 or 2, wherein,
the gate electrode is formed of polysilicon.
5. The semiconductor device according to claim 1 or 2, wherein,
a second nitride layer is further provided, and is formed so as to cover the lower surface of the first resistor layer.
6. The semiconductor device according to claim 5, wherein,
A second conductivity type well layer is formed in direct contact with a part or the whole of the lower surface of the second nitride layer.
7. The semiconductor device according to claim 1 or 2, wherein,
the gate electrode is in direct contact with the first resistive layer.
8. A semiconductor device is provided with:
a drift layer of the first conductivity type;
a second conductivity type underlayer formed on a surface layer of the drift layer;
an emitter layer of a first conductivity type selectively formed on a surface layer of the base layer;
a trench formed to penetrate the emitter layer and the base layer from the upper surface of the drift layer and to reach the drift layer;
a gate insulating film formed along a bottom surface and side surfaces of the trench;
a first gate electrode formed in the trench surrounded by the gate insulating film; and
a first nitride layer formed to cover at least an upper surface of the first gate electrode,
wherein the resistance of the first gate electrode has a negative temperature coefficient,
the first gate electrode is formed of amorphous silicon doped with hydrogen,
at least a part of the first gate electrode contains 1% or more of hydrogen in an atomic composition ratio,
The first nitride layer is formed of a silicon nitride layer or an aluminum nitride layer,
the semiconductor device further includes a second gate electrode formed on an upper surface of the first gate electrode,
the first nitride layer is formed to cover at least an upper surface of the second gate electrode,
the first gate electrode and the second gate electrode contain 1% or more of hydrogen in an atomic composition ratio,
the second gate electrode has a higher crystallinity than the first gate electrode.
9. The semiconductor device according to claim 8, wherein,
the first nitride layer is formed to cover upper surfaces, side surfaces, and bottom surfaces of the first gate electrode and the second gate electrode.
10. The semiconductor device according to claim 8 or 9, wherein,
the second gate electrode is microcrystalline silicon containing 1% or more of hydrogen in an atomic composition ratio.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103268888A (en) * 2013-05-13 2013-08-28 电子科技大学 IGBT device with emitter ballast resistor
CN104364907A (en) * 2012-05-30 2015-02-18 株式会社电装 Semiconductor device
JP2016058466A (en) * 2014-09-08 2016-04-21 三菱電機株式会社 Silicon carbide semiconductor device
WO2016181903A1 (en) * 2015-05-14 2016-11-17 三菱電機株式会社 Silicon carbide semiconductor device and method for manufacturing same
CN106233454A (en) * 2014-05-01 2016-12-14 松下知识产权经营株式会社 Semiconductor device and quasiconductor module
WO2017126167A1 (en) * 2016-01-19 2017-07-27 三菱電機株式会社 Semiconductor apparatus

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3100755B2 (en) * 1992-05-28 2000-10-23 松下電子工業株式会社 Vertical MOS field-effect transistor
JP4791700B2 (en) 2004-03-29 2011-10-12 株式会社リコー Semiconductor device, semiconductor device adjustment method, and electronic device
US20120256255A1 (en) * 2011-04-07 2012-10-11 Tieh-Chiang Wu Recessed trench gate structure and method of fabricating the same
JP2013065774A (en) 2011-09-20 2013-04-11 Toshiba Corp Semiconductor device and manufacturing method of the same
JP5696713B2 (en) * 2012-11-06 2015-04-08 株式会社デンソー Semiconductor device and inspection method thereof
US9871126B2 (en) * 2014-06-16 2018-01-16 Infineon Technologies Ag Discrete semiconductor transistor
JP6100233B2 (en) 2014-12-26 2017-03-22 株式会社東芝 Semiconductor device
WO2016114055A1 (en) * 2015-01-16 2016-07-21 富士電機株式会社 Silicon carbide semiconductor device and method for producing silicon carbide semiconductor device
WO2017029748A1 (en) 2015-08-20 2017-02-23 株式会社日立製作所 Semiconductor device, power module, power converter, vehicle, and train carriage

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104364907A (en) * 2012-05-30 2015-02-18 株式会社电装 Semiconductor device
CN103268888A (en) * 2013-05-13 2013-08-28 电子科技大学 IGBT device with emitter ballast resistor
CN106233454A (en) * 2014-05-01 2016-12-14 松下知识产权经营株式会社 Semiconductor device and quasiconductor module
JP2016058466A (en) * 2014-09-08 2016-04-21 三菱電機株式会社 Silicon carbide semiconductor device
WO2016181903A1 (en) * 2015-05-14 2016-11-17 三菱電機株式会社 Silicon carbide semiconductor device and method for manufacturing same
WO2017126167A1 (en) * 2016-01-19 2017-07-27 三菱電機株式会社 Semiconductor apparatus

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