JP2017017145A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can inhibit deterioration in an electrode.SOLUTION: A semiconductor device according to an embodiment includes a first conductivity type first semiconductor region, a second conductivity type second semiconductor region, a first electrode, a semi-insulating layer and an insulating layer. The first semiconductor region has a first region and a second region provided around the first region. The second semiconductor region is provided on the first region of the first semiconductor region. The first electrode includes metal and is provided on the second semiconductor region. The semi-insulating layer is provided on the second region. A part of the semi-insulating layer is located on the first electrode. At least a part of the insulating layer is provided between the semi-insulating layer and the first electrode.SELECTED DRAWING: Figure 2

Description

  Embodiments described herein relate generally to a semiconductor device.

  Semiconductor devices such as diodes, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and IGBTs (Insulated Gate Bipolar Transistors) are used for power control applications, for example. These semiconductor devices have a termination region provided around the element region in order to increase the breakdown voltage.

In order to suppress the fluctuation of the electric field distribution in the termination region, a semi-insulating layer may be provided in the termination region. In this case, in order to discharge the charge flowing into the semi-insulating layer, it can be considered that the semi-insulating layer is brought into contact with an electrode provided in the element region.
However, when this electrode contains a metal, reaction and diffusion may occur between the metal contained in the electrode and the material contained in the semi-insulating layer. When a reaction or diffusion occurs between the metal contained in the electrode and the material contained in the semi-insulating layer, the electrode may be deteriorated, resulting in disconnection or variation in electrical characteristics.

JP 2001-57426 A

  The problem to be solved by the present invention is to provide a semiconductor device capable of suppressing electrode deterioration.

The semiconductor device according to the embodiment includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a first electrode, a semi-insulating layer, and an insulating layer.
The first semiconductor region has a first region and a second region provided around the first region.
The second semiconductor region is provided on the first region of the first semiconductor region.
The first electrode includes a metal and is provided on the second semiconductor region.
The semi-insulating layer is provided on the second region. A part of the semi-insulating layer is located on the first electrode.
At least a part of the insulating layer is provided between the semi-insulating layer and the first electrode.

1 is a plan view of a semiconductor device according to a first embodiment. It is AA 'sectional drawing of FIG. It is process sectional drawing showing an example of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing showing an example of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing showing an example of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing showing a part of semiconductor device which concerns on the modification of 1st Embodiment. It is sectional drawing showing a part of semiconductor device which concerns on the modification of 2nd Embodiment. It is sectional drawing showing a part of semiconductor device which concerns on the modification of 3rd Embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
In addition, in the present specification and each drawing, elements having the same function or the same configuration as those already described are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.
In the description of each embodiment, an XYZ orthogonal coordinate system is used. Two directions parallel to the surface S1 of the semiconductor layer S and perpendicular to each other are defined as an X direction and a Y direction, and a direction perpendicular to both the X direction and the Y direction is defined as a Z direction.
In the following description, the notations of n ⁺ , n ^−, p ⁺ , and p represent relative levels of impurity concentration in each conductivity type. That is, n ⁺ indicates that the n-type impurity concentration is relatively higher than n ⁻ . p ⁺ indicates that the p-type impurity concentration is relatively higher than p.
About each embodiment described below, each embodiment may be implemented by inverting the p-type and n-type of each semiconductor region.

(First embodiment)
A semiconductor device 100 according to the first embodiment will be described with reference to FIGS. 1 and 2.
FIG. 1 is a plan view of the semiconductor device 100 according to the first embodiment.
2 is a cross-sectional view taken along the line AA ′ of FIG.
In FIG. 1, the insulating part 52 is omitted. In FIG. 1, the first region R1 and the second region R2 included in the n ⁻ -type semiconductor region 1 are represented by broken lines.

The semiconductor device 100 is, for example, a MOSFET.
As shown in FIGS. 1 and 2, the semiconductor device 100 includes a semiconductor layer S, a source electrode 31 (first electrode), a drain electrode 32, an EQPR electrode 33, a gate electrode pad 34, and a semi-insulating layer 41. And an insulating layer 42, an insulating layer 51, and an insulating portion 52.
The semiconductor layer S includes an n ^{+ -type} (first conductivity type) drain region 5, an n ⁻ -type semiconductor region 1 (first semiconductor region), and a p-type (second conductivity type) base region 2 (second semiconductor). Region), an n ^{+ -type} source region 3 (third semiconductor region), an n ^{+ -type} semiconductor region 4 (fourth semiconductor region), a gate electrode 21, and a gate insulating layer 22.

As shown in FIG. 1, the source electrode 31 and the gate electrode pad 34 are provided to be separated from each other and are surrounded by the semi-insulating layer 41. The n ⁻ -type semiconductor region 1 has a first region R1 and a second region R2 provided therearound, and the source electrode 31 and the gate electrode pad 34 are provided on the first region R1. . The semi-insulating layer 41 is provided on the second region R2. As shown in FIG. 2, a semi-insulating layer 41 is provided on the source electrode 31 on the boundary portion between the first region R1 and the second region R2.

As shown in FIG. 2, the semiconductor layer S has a front surface S1 and a back surface S2. A source electrode 31 is provided on the front surface S1, and a drain electrode 32 is provided on the back surface S2.
The n ⁺ -type drain region 5 is provided on the back surface S 2 side in the semiconductor layer S and is electrically connected to the drain electrode 32. The n ^{− type} semiconductor region 1 is provided on the n ^{+ type} drain region 5.

The p-type base region 2 is provided on the first region R1. A plurality of p-type base regions 2 are provided in the X direction, and each p-type base region 2 extends in the Y direction. The p-type base region 2 is surrounded by a part of the second region R2 along the XY plane.
The n ^{+ -type} source region 3 is selectively provided on the p-type base region 2. n ⁺ -type source region 3 is provided with a plurality in the X direction, each of the n ⁺ -type source region 3 extends in the Y direction.

The gate electrode 21 is provided in the semiconductor layer S. A plurality of gate electrodes 21 are provided in the X direction, and each gate electrode 21 extends in the Y direction.
n ^- respectively form the semiconductor region 1, p-type base region 2, and n ⁺ -type source region 3, a gate electrode 21, between the gate insulating layer 22 is provided.

The source electrode 31, n ⁺ is provided on the form over and gate electrode 21 of the source region 3 is n ⁺ -type source region 3 and electrically connected. An insulating layer is provided between the gate electrode 21 and the source electrode 31, and the gate electrode 21 is electrically separated from the source electrode 31.

The n ^{+ -type} semiconductor region 4 is provided on the second region R2 and surrounds the p-type base region 2.
The EQPR electrode 33 is provided on the n ^{+ type} semiconductor region 4 and surrounds the source electrode 31. The EQPR electrode 33 is electrically connected to the n ^{+ type} semiconductor region 4.
An insulating layer 51 is provided between the source electrode 31 and the EQPR electrode 33.

  The insulating layer 42 is provided on the second region R2, and the semi-insulating layer 41 is provided on the insulating layer 42. More specifically, the semi-insulating layer 41 and the insulating layer 42 are provided on part of the source electrode 31, on at least part of the EQPR electrode 33, and on the insulating layer 51. However, the insulating layer 42 may be selectively provided only between the semi-insulating layer 41 and the source electrode 31 and between the semi-insulating layer 41 and the EQPR electrode 33.

  An insulating portion 52 is provided on the source electrode 31 and the semi-insulating layer 41. However, a part (not shown) of the source electrode 31 is not covered with the insulating portion 52 for connection with other electrodes, and is exposed to the outside.

  By providing the semi-insulating layer 41 on the second region R2, fluctuations in the electric field distribution in the second region R2 caused by movement or polarization of ions contained in the insulating portion 52 are suppressed.

Here, an example of the material contained in each element will be described.
The semiconductor layer S includes silicon, silicon carbide, or gallium nitride.
The gate electrode 21 includes polycrystalline silicon.
The gate insulating layer 22 and the insulating layer 51 include silicon oxide.
The source electrode 31 and the drain electrode 32 include a metal such as aluminum or copper. The source electrode 31 and the drain electrode 32 may contain silicon in addition to these metals.
The insulating part 52 includes an insulating resin such as polyimide.

  The semi-insulating layer 41 includes silicon nitride. Alternatively, the semi-insulating layer 41 may include SIPOS (Semi-Insulating-Polycristaline-Silicon) in which the silicon grains are partially oxidized. The electric resistance of the semi-insulating layer 41 is higher than the electric resistance of the source electrode 31 and the electric resistance of the EQPR electrode 33.

  The insulating layer 42 similarly includes silicon nitride. Alternatively, the insulating layer 42 may include another nitride such as titanium nitride or an oxide such as tantalum oxide.

When the semi-insulating layer 41 and the insulating layer 42 contain silicon nitride, the ratio C1 _Si / C1 _N of the silicon content C1 _{Si to} the nitrogen content C1 _N in the semi-insulating layer 41 is the nitrogen content in the insulating layer 42 C2 higher than the rate _C2 Si / C2 _N content _{C2 Si} of silicon to _N.

The ratio _C2 Si / C2 _N in the insulating layer 42, than the ratio _C1 Si / C1 _N in the semi-insulating layer 41, close to the stoichiometric ratio of silicon nitride (3/4). For this reason, the electrical resistance of the insulating layer 42 is higher than the electrical resistance of the semi-insulating layer 41.
Is C1 _Si / C1 _N, for example, 1.0 or more and 1.5 or _{less, C2} Si / C2 _N, for example, 0.65 or more, and preferably 0.85 or less.
When the semi-insulating layer 41 and the insulating layer 42 have such a composition, the refractive index of the semi-insulating layer 41 is, for example, 2.3 or more and 2.7 or less, and the refractive index of the insulating layer 42 is, for example, 1.9 or more. 2.1 or less.

Next, an example of a method for manufacturing the semiconductor device 100 according to the first embodiment will be described with reference to FIGS.
3 to 5 are process cross-sectional views illustrating an example of a manufacturing process of the semiconductor device 100 according to the first embodiment.

First, the n ⁻ -type semiconductor region 1 is formed by epitaxially growing an n ⁻ -type semiconductor layer on the n ^{+ -type} semiconductor substrate 5a. Subsequently, a plurality of trenches are formed in the n ⁻ -type semiconductor region 1 using photolithography and RIE. Subsequently, a silicon oxide layer 22a is formed on the surface of the n ⁻ -type semiconductor region 1 and the inner wall of the trench using a thermal oxidation method. The situation at this time is shown in FIG.

Next, a polysilicon layer is deposited on the silicon oxide layer 22a using a CVD method. By etching back the polysilicon layer, the gate electrode 21 is formed. Subsequently, a silicon oxide layer 51a is formed on the n ⁻ -type semiconductor region 1 and the gate electrode 21 by using the CVD method. The state at this time is shown in FIG.

Next, the silicon oxide layer 22a and the silicon oxide layer 51a are patterned. By this step, the gate insulating layer 22 and the insulating layer 51 are formed. Subsequently, a p-type base region 2 is formed by ion-implanting p-type impurities into a part of the surface of the n ⁻ -type semiconductor region 1. Subsequently, n-type impurities are ion-implanted into another part of the surface of the n ⁻ -type semiconductor region 1 and part of the surface of the p-type base region 2. By this step, the n ^{+ type} semiconductor region 4 and the n ^{+ type} source region 3 are formed. The situation at this time is shown in FIG.

  Next, a metal layer is formed on these semiconductor regions and on the insulating layer 51, and this metal layer is patterned to form the source electrode 31, the EQPR electrode 33, and the gate electrode pad. The situation at this time is shown in FIG.

Next, an insulating layer covering these electrodes is formed by a plasma CVD method using a silicon-containing gas and a nitrogen-containing gas. Subsequently, a semi-insulating layer is formed on the insulating layer again by a plasma CVD method using a silicon-containing gas and a nitrogen-containing gas. At this time, the semi-insulating layer and the insulating layer are formed so that the ratio of the silicon content to the nitrogen content in the semi-insulating layer is higher than the ratio of the silicon content to the nitrogen content in the insulating layer. .
Subsequently, the insulating layer and the semi-insulating layer are patterned to form the semi-insulating layer 41 and the insulating layer 42 as shown in FIG.

Next, the back surface of the substrate 5a is polished until the substrate 5a has a predetermined thickness. By this step, the n ⁺ -type drain region 5 is formed. Subsequently, the drain electrode 32 is formed under the n ⁺ -type drain region 5.
Thereafter, by forming an insulating portion 52 that covers the source electrode 31, the gate electrode pad 34, and the semi-insulating layer 41, the semiconductor device 100 shown in FIGS. 1 and 2 is obtained.

In the example of the manufacturing method described above, the gate electrode 21 and the gate insulating layer 22 may be formed after the p-type base region 2, the n ^{+ -type} source region 3 and the n ^{+ -type} semiconductor region 4 are formed.

Next, the operation and effect of this embodiment will be described.
According to the present embodiment, the insulating layer 42 is provided between the source electrode 31 and the semi-insulating layer 41. By providing the insulating layer 42, reaction and diffusion between the metal included in the source electrode 31 and the material included in the semi-insulating layer 41 can be suppressed. For this reason, it is possible to suppress the deterioration of the source electrode 31 and to suppress the occurrence of disconnection in the source electrode 31 and the variation in the electrical characteristics of the source electrode 31.

  Such a problem becomes more prominent when the source electrode 31 contains aluminum, the semi-insulating layer 41 contains silicon nitride, and the semi-insulating layer 41 is in direct contact with the source electrode 31. This is because a phenomenon occurs in which aluminum contained in the source electrode 31 and silicon contained in the semi-insulating layer 41 diffuse to each other, and aluminum is deposited in a portion where the silicon atoms are removed in the semi-insulating layer 41. . That is, when the source electrode 31 and the semi-insulating layer 41 contain these materials, the source electrode 31 is deteriorated, the semi-insulating layer 41 is deteriorated, and the breakdown voltage of the semiconductor device can be reduced. Therefore, this embodiment is particularly effective when the source electrode 31 and the semi-insulating layer 41 include the above-described materials.

  A similar problem occurs when the semi-insulating layer 41 is provided on the EQPR electrode 33. Therefore, when the semiconductor device 100 has the EQPR electrode 33 and a part of the semi-insulating layer 41 is also provided on the EQPR electrode 33, the insulating layer is also provided between the EQPR electrode 33 and the semi-insulating layer 41. 42 is preferably provided.

  In addition, the semi-insulating layer 41 and the insulating layer 42 are formed after the electrodes such as the source electrode 31 and the EQPR electrode 33 are formed. For this reason, when forming the semi-insulating layer 41 and the insulating layer 42, it is desirable to suppress the temperature rise of these electrodes. When silicon nitride is used as the material of the semi-insulating layer 41 and the insulating layer 42, these layers can be formed by a plasma CVD method. By using the plasma CVD method, it is possible to suppress the temperature rise of the electrode when the semi-insulating layer 41 and the insulating layer 42 are formed.

  Note that the insulating layer 42 has a film thickness between the source electrode 31 and the semi-insulating layer 41 while suppressing reaction and diffusion between the metal contained in the source electrode 31 and the material contained in the semi-insulating layer 41. It is desirable to set so that a tunnel current flows. Specifically, the thickness of the insulating layer 42 is desirably 10 nm or less.

  The insulating layer 42 preferably includes silicon nitride. The insulating layer 42 containing silicon nitride can also function as a passivation layer. For this reason, when the insulating layer 42 contains silicon nitride, the movement of impurities and ions contained in the insulating portion 52 to the insulating layer 51 and the semiconductor layer S is suppressed, and the breakdown voltage of the semiconductor device can be improved.

  The semiconductor device 100 illustrated in FIGS. 1 to 5 has a trench type gate structure in which the gate electrode 21 is provided in the semiconductor layer S. In the present embodiment, the gate insulation is formed on the surface S1. The present invention can also be applied to a planar gate structure in which a gate electrode is provided through a layer.

(Modification)
A semiconductor device 110 according to a modification of the first embodiment will be described with reference to FIG.
FIG. 6 is a cross-sectional view illustrating a part of a semiconductor device 110 according to a modification of the first embodiment.
The semiconductor device 110 is different from the semiconductor device 100 in that a silicon nitride layer 43 is provided instead of the semi-insulating layer 41 and the insulating layer 42. The configuration other than the silicon nitride layer 43 included in the semiconductor device 110 can be the same as that of the semiconductor device 100.

As shown in FIG. 6, the silicon nitride layer 43 has a first portion 431 and a second portion 432. The first portion 431 is provided on part of the source electrode 31, on at least part of the EQPR electrode 33, and on the insulating layer 51. The second portion 432 is provided between the first portion 431 and each of the source electrode 31, at least a portion of the EQPR electrode 33, and the insulating layer 51.
However, the second portion 432 may be selectively provided only between the source electrode 31 and the first portion 431 and between the EQPR electrode 33 and the first portion 431.

Ratio _C1 Si / C1 _N content _{C1 Si} of the silicon with respect to the content C1 _N of nitrogen in the first portion 431, the ratio of the content _{C2 Si} of the silicon with respect to the content C2 _N of nitrogen in the second portion 432 _{C2 Si} / C2 higher than the _N.
Is C1 _Si / C1 _N, for example, 1.0 or more and 1.5 or _{less, C2} Si / C2 _N, for example, 0.65 or more, and preferably 0.85 or less.

  The silicon nitride layer 43 can be formed by, for example, a plasma CVD method using a silicon-containing gas and a nitrogen-containing gas after the step shown in FIG. At this time, the silicon nitride layer 43 having the first portion 431 and the second portion 432 can be formed by depositing silicon nitride while increasing the amount of the silicon-containing gas with respect to the amount of the nitrogen-containing gas.

  Also in the present modification, as in the first embodiment, since the second portion 432 is provided between the first portion 431 and each electrode, it is possible to suppress deterioration of the electrode.

(Second Embodiment)
A semiconductor device 200 according to the second embodiment will be described with reference to FIG.
FIG. 7 is a cross-sectional view illustrating a part of the semiconductor device 200 according to the second embodiment.

The semiconductor device 200 is, for example, a diode.
As shown in FIG. 7, the semiconductor device 200 includes a semiconductor layer S, an anode electrode 31, a cathode electrode 32, an EQPR electrode 33, a semi-insulating layer 41, an insulating layer 42, an insulating layer 51, and an insulating portion. 52.
The semiconductor layer S includes an n ^{+ -type} (first conductivity type) cathode region 5, an n ⁻ -type semiconductor region 1 (first semiconductor region), and a p-type (second conductivity type) semiconductor region 2 (second semiconductor). Region), an n ^{+ type} semiconductor region 4 (fourth semiconductor region), and a p ^{+ type} anode region 6.

The p ^{+ -type} anode region 6 is selectively provided on the p-type semiconductor region 2. The anode electrode 31 is provided on the p ⁺ -type anode region 6 is connected p ⁺ -type anode region 6 and electrically.

  Also in the present embodiment, it is possible to suppress the deterioration of the anode electrode 31 as in the first embodiment.

(Third embodiment)
A semiconductor device 300 according to the third embodiment will be described with reference to FIG.
FIG. 8 is a cross-sectional view illustrating a part of the semiconductor device 300 according to the third embodiment.

The semiconductor device 300 is, for example, an IGBT.
As shown in FIG. 8, the semiconductor device 300 includes a semiconductor layer S, an emitter electrode 31, a collector electrode 32, an EQPR electrode 33, a semi-insulating layer 41, an insulating layer 42, an insulating layer 51, and an insulating portion. 52. Similar to the semiconductor device 100, the semiconductor device 300 further includes a gate pad electrode (not shown).
The semiconductor layer S includes a p ^{+ -type} (second conductivity type) collector region 7, an n ^{+ -type} (first conductivity type) semiconductor region 5, an n ⁻ -type semiconductor region 1 (first semiconductor region), p A base region 2 (second semiconductor region), an n ⁺ -type emitter region 3 (third semiconductor region), an n ^{+ -type} semiconductor region 4 (fourth semiconductor region), a gate electrode 21, and a gate insulating layer 22. Have.

The p ^{+ -type} collector region 7 is provided under the n-type semiconductor region 5, and the collector electrode 32 is electrically connected to the p ^{+ -type} collector region 7.

  Also in the present embodiment, it is possible to suppress the deterioration of the emitter electrode 31 as in the first embodiment.

  The relative level of the impurity concentration between the semiconductor regions in each of the embodiments described above can be confirmed using, for example, an SCM (scanning capacitance microscope). The carrier concentration in each semiconductor region can be regarded as being equal to the impurity concentration activated in each semiconductor region. Therefore, the relative level of the carrier concentration between the semiconductor regions can also be confirmed using the SCM.

  For the silicon content and the nitrogen content in the semi-insulating layer 41, the insulating layer 42, and the silicon nitride layer 43, XPS (X-ray photoelectron spectroscopy), GD-OES (glow discharge emission spectrometry), or It can be confirmed by SIMS (secondary ion mass spectrometry) or the like.

As mentioned above, although several embodiment of this invention was illustrated, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, changes, and the like can be made without departing from the spirit of the invention. For example, an n ^{+ -type} semiconductor region 5, an n ^{− -type} semiconductor region 1, a p-type semiconductor region 2, an n ^{+ -type} semiconductor region 3, an n ^{+ -type} semiconductor region 4, a p ^{+ -type} semiconductor region 6 and p included in the embodiment. The specific configuration of each element such as the ^{+ -type} semiconductor region 7, the gate electrode 21, the gate insulating layer 22, the electrodes 31 to 33, and the gate electrode pad 34 can be appropriately selected by those skilled in the art from known techniques. It is. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and equivalents thereof. Further, the above-described embodiments can be implemented in combination with each other.

100,110,200,300 ... semiconductor device 1 ... n ^- type semiconductor region 2 ... p-type semiconductor regions 3 ... ^{n +} type semiconductor region 4 ... ^{n +} type semiconductor region 5 ... ^{n +} type semiconductor region 6 ... ^{p +} -type semiconductor Region 7 ... p ^{+ type} semiconductor region 21 ... Gate electrode 22 ... Gate insulating layer 31, 32, 33 ... Electrode 41 ... Semi-insulating layer 42 ... Insulating layer 43 ... Silicon nitride layer

Claims (5)

A first semiconductor region of a first conductivity type having a first region and a second region provided around the first region;
A second semiconductor region of a second conductivity type provided on the first region;
A first electrode provided on the second semiconductor region and including a metal;
A semi-insulating layer provided on the second region and partially located on the first electrode;
An insulating layer at least partially provided between the semi-insulating layer and the first electrode;
A semiconductor device comprising: The metal is aluminum;
The semiconductor device according to claim 1, wherein the semi-insulating layer and the insulating layer include silicon nitride. The ratio of the silicon content to the nitrogen content in the semi-insulating layer is 1.0 or more and 1.5 or less,
The semiconductor device according to claim 2, wherein a ratio of a silicon content to a nitrogen content in the insulating layer is 0.65 or more and 0.85 or less. A first semiconductor region of a first conductivity type having a first region and a second region provided around the first region;
A second semiconductor region of a second conductivity type provided on the first region;
A first electrode including a metal provided on the second semiconductor region;
A first portion provided on the second region, a portion of which is located on the first electrode;
A second part provided between the first electrode and the first part, wherein the ratio of the silicon content to the nitrogen content is higher than the ratio of the silicon content to the nitrogen content in the first part; ,
A silicon nitride layer having
A semiconductor device comprising: A first semiconductor region;
A second semiconductor region of a second conductivity type provided on a part of the first semiconductor region and surrounded by another part of the first semiconductor region;
A first electrode provided on the second semiconductor region and including a metal;
A semi-insulating layer provided on the other part of the first semiconductor region, a part of which is located on the first electrode;
An insulating layer at least partially provided between the semi-insulating layer and the first electrode;
A semiconductor device comprising:

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