JP2019134149A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2019134149A
JP2019134149A JP2018086469A JP2018086469A JP2019134149A JP 2019134149 A JP2019134149 A JP 2019134149A JP 2018086469 A JP2018086469 A JP 2018086469A JP 2018086469 A JP2018086469 A JP 2018086469A JP 2019134149 A JP2019134149 A JP 2019134149A
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semiconductor region
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JP7123613B2 (en
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俊史 西口
Toshifumi Nishiguchi
俊史 西口
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Toshiba Electronic Devices and Storage Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

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Abstract

To provide a semiconductor device capable of reducing an on-resistance.SOLUTION: A semiconductor device according to an embodiment comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, and a conductive unit. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The gate electrode faces a part of the first semiconductor region, the second semiconductor region, and the third semiconductor region via a gate insulation layer in a second direction perpendicular to a first direction heading from the second semiconductor region to the third semiconductor region. The conductive unit comprises a first portion and a second portion. The first portion is aligned with a part of the second semiconductor region in the second direction. The second portion is aligned with at least a part of the third semiconductor region in the second direction. A length in a second direction of the first portion is longer than a length in a second direction of the second portion. The conductive part is electrically connected to the second semiconductor region and the third semiconductor region.SELECTED DRAWING: Figure 1

Description

本発明の実施形態は、半導体装置に関する。   Embodiments described herein relate generally to a semiconductor device.

ＭＯＳＦＥＴ(Metal Oxide Semiconductor Field Effect Transistor)やＩＧＢＴ(Insulated Gate Bipolar Transistor)などの半導体装置は、スイッチング装置として用いられる。半導体装置における消費電力を低減するためには、半導体装置のオン抵抗が低いことが望ましい。   Semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are used as switching devices. In order to reduce power consumption in the semiconductor device, it is desirable that the on-resistance of the semiconductor device is low.

特許第５２４６３０２号公報Japanese Patent No. 5246302

本発明が解決しようとする課題は、オン抵抗を低減できる半導体装置を提供することである。   The problem to be solved by the present invention is to provide a semiconductor device capable of reducing on-resistance.

実施形態に係る半導体装置は、第１導電形の第１半導体領域と、第２導電形の第２半導体領域と、第１導電形の第３半導体領域と、ゲート電極と、導電部と、を有する。前記第２半導体領域は、前記第１半導体領域の上に設けられている。前記第３半導体領域は、前記第２半導体領域の上に設けられている。前記ゲート電極は、前記第２半導体領域から前記第３半導体領域に向かう第１方向に対して垂直な第２方向において、前記第１半導体領域の一部、前記第２半導体領域、及び前記第３半導体領域とゲート絶縁層を介して対向する。前記導電部は、第１部分及び第２部分を有する。前記第１部分は、前記第２半導体領域の一部と前記第２方向において並ぶ。前記第２部分は、前記第３半導体領域の少なくとも一部と前記第２方向において並ぶ。前記第１部分の前記第２方向における長さは、前記第２部分の前記第２方向における長さよりも長い。前記導電部は、前記第２半導体領域及び前記第３半導体領域と電気的に接続されている。   The semiconductor device according to the embodiment includes a first semiconductor region having a first conductivity type, a second semiconductor region having a second conductivity type, a third semiconductor region having a first conductivity type, a gate electrode, and a conductive portion. Have. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The gate electrode includes a part of the first semiconductor region, the second semiconductor region, and the third semiconductor region in a second direction perpendicular to the first direction from the second semiconductor region to the third semiconductor region. Opposite the semiconductor region through the gate insulating layer. The conductive portion has a first portion and a second portion. The first portion is aligned with a part of the second semiconductor region in the second direction. The second portion is aligned with at least a part of the third semiconductor region in the second direction. The length of the first portion in the second direction is longer than the length of the second portion in the second direction. The conductive portion is electrically connected to the second semiconductor region and the third semiconductor region.

実施形態に係る半導体装置の一部を表す斜視断面図である。It is a perspective sectional view showing a part of semiconductor device concerning an embodiment. 図１の一部を拡大した断面図である。It is sectional drawing to which a part of FIG. 1 was expanded. 実施形態に係る半導体装置の製造工程を表す工程断面図である。It is process sectional drawing showing the manufacturing process of the semiconductor device which concerns on embodiment. 実施形態に係る半導体装置の製造工程を表す工程断面図である。It is process sectional drawing showing the manufacturing process of the semiconductor device which concerns on embodiment. 実施形態に係る半導体装置の製造工程を表す工程断面図である。It is process sectional drawing showing the manufacturing process of the semiconductor device which concerns on embodiment. 参考例に係る半導体装置の一部を表す断面図である。It is sectional drawing showing a part of semiconductor device which concerns on a reference example. 実施形態の変形例に係る半導体装置の一部を表す断面図である。It is sectional drawing showing a part of semiconductor device which concerns on the modification of embodiment. 実施形態の変形例に係る半導体装置の一部を表す断面図である。It is sectional drawing showing a part of semiconductor device which concerns on the modification of embodiment. 実施形態の変形例に係る半導体装置の一部を表す斜視断面図である。It is a perspective sectional view showing a part of a semiconductor device concerning a modification of an embodiment.

以下に、本発明の各実施形態について図面を参照しつつ説明する。
なお、図面は模式的または概念的なものであり、各部分の厚みと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。また、同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
また、本願明細書と各図において、既に説明したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。
以下の説明及び図面において、ｎ＋、ｎ、ｎ−及びｐ＋、ｐの表記は、各導電形における不純物濃度の相対的な高低を表す。すなわち、「＋」が付されている表記は、「＋」及び「−」のいずれも付されていない表記よりも不純物濃度が相対的に高く、「−」が付されている表記は、いずれも付されていない表記よりも不純物濃度が相対的に低いことを示す。
以下で説明する各実施形態について、各半導体領域のｐ形とｎ形を反転させて各実施形態を実施してもよい。 Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
In the present specification and each drawing, the same elements as those already described are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.
In the following description and drawings, the notations n + , n, n − and p + , p represent the relative levels of the impurity concentration in each conductivity type. That is, the notation marked with “+” has a relatively higher impurity concentration than the notation marked with neither “+” nor “−”, and the notation marked with “−” It shows that the impurity concentration is relatively lower than the notation.
About each embodiment described below, each embodiment may be implemented by inverting the p-type and n-type of each semiconductor region.

図１は、実施形態に係る半導体装置の一部を表す斜視断面図である。
図１に表したように、実施形態に係る半導体装置１００は、ｎ−形（第１導電形）ドリフト領域１（第１半導体領域）、ｐ形（第２導電形）ベース領域２（第２半導体領域）、ｎ＋形ソース領域３（第３半導体領域）、ｐ＋形コンタクト領域４（第４半導体領域）、ｎ＋形ドレイン領域５（第６半導体領域）、導電部１０、ゲート電極２０、ゲート絶縁層２１、絶縁層２５、ドレイン電極３１（第１電極）、及びソース電極３２（第２電極）を有する。 FIG. 1 is a perspective cross-sectional view illustrating a part of the semiconductor device according to the embodiment.
As illustrated in FIG. 1, the semiconductor device 100 according to the embodiment includes an n − type (first conductivity type) drift region 1 (first semiconductor region), a p type (second conductivity type) base region 2 (second Semiconductor region), n + -type source region 3 (third semiconductor region), p + -type contact region 4 (fourth semiconductor region), n + -type drain region 5 (sixth semiconductor region), conductive portion 10, and gate electrode 20 , A gate insulating layer 21, an insulating layer 25, a drain electrode 31 (first electrode), and a source electrode 32 (second electrode).

実施形態の説明では、ＸＹＺ直交座標系を用いる。ｐ形ベース領域２からｎ＋形ソース領域３に向かう方向をＺ方向（第１方向）とする。Ｚ方向に対して垂直であり、相互に直交する２方向をＸ方向（第２方向）及びＹ方向（第３方向）とする。また、説明のために、ｐ形ベース領域２からｎ＋形ソース領域３に向かう方向を「上」と言い、その反対方向を「下」と言う。これらの方向は、ｐ形ベース領域２とｎ＋形ソース領域３との相対的な位置関係に基づき、重力の方向とは無関係である。 In the description of the embodiment, an XYZ orthogonal coordinate system is used. A direction from the p-type base region 2 toward the n + -type source region 3 is defined as a Z direction (first direction). Two directions perpendicular to the Z direction and orthogonal to each other are defined as an X direction (second direction) and a Y direction (third direction). For the sake of explanation, the direction from the p-type base region 2 to the n + -type source region 3 is referred to as “up”, and the opposite direction is referred to as “down”. These directions are based on the relative positional relationship between the p-type base region 2 and the n + -type source region 3, and are independent of the direction of gravity.

ｎ＋形ドレイン領域５は、ドレイン電極３１の上に設けられ、ドレイン電極３１と電気的に接続されている。ｎ−形ドリフト領域１は、ｎ＋形ドレイン領域５の上に設けられている。ｐ形ベース領域２は、ｎ−形ドリフト領域１の一部の上に設けられている。ｎ＋形ソース領域３は、ｐ形ベース領域２の上に設けられている。図１に表した例では、ｐ形ベース領域２の上に、複数のｎ＋形ソース領域３が設けられている。 The n + -type drain region 5 is provided on the drain electrode 31 and is electrically connected to the drain electrode 31. The n − type drift region 1 is provided on the n + type drain region 5. The p-type base region 2 is provided on a part of the n − -type drift region 1. The n + -type source region 3 is provided on the p-type base region 2. In the example shown in FIG. 1, a plurality of n + -type source regions 3 are provided on the p-type base region 2.

ゲート電極２０は、Ｘ方向において、ｎ−形ドリフト領域１の一部、ｐ形ベース領域２、及びｎ＋形ソース領域３の少なくとも一部と、ゲート絶縁層２１を介して対向している。絶縁層２５は、ゲート電極２０の上及びｎ＋形ソース領域３の一部の上に設けられている。 The gate electrode 20 is opposed to at least a part of the n − -type drift region 1, the p-type base region 2, and the n + -type source region 3 through the gate insulating layer 21 in the X direction. The insulating layer 25 is provided on the gate electrode 20 and a part of the n + -type source region 3.

導電部１０の一部は、ｐ形ベース領域２、ｎ＋形ソース領域３、及びｐ＋形コンタクト領域４に囲まれ、これらの半導体領域と電気的に接続されている。導電部１０の別の一部は、ｎ＋形ソース領域３よりも上方に設けられ、Ｘ方向において絶縁層２５と並んでいる。ｐ＋形コンタクト領域４は、ｐ形ベース領域２と導電部１０との間及びｎ＋形ソース領域３と導電部１０との間に設けられている。ソース電極３２は、導電部１０及び絶縁層２５の上に設けられ、導電部１０と電気的に接続されている。 A part of the conductive portion 10 is surrounded by the p-type base region 2, the n + -type source region 3, and the p + -type contact region 4, and is electrically connected to these semiconductor regions. Another part of the conductive portion 10 is provided above the n + -type source region 3 and is aligned with the insulating layer 25 in the X direction. The p + -type contact region 4 is provided between the p-type base region 2 and the conductive portion 10 and between the n + -type source region 3 and the conductive portion 10. The source electrode 32 is provided on the conductive portion 10 and the insulating layer 25 and is electrically connected to the conductive portion 10.

ｐ形ベース領域２、ｎ＋形ソース領域３、導電部１０、及びゲート電極２０のそれぞれは、例えば、Ｘ方向において複数設けられ、Ｙ方向に延びている。 Each of the p-type base region 2, the n + -type source region 3, the conductive portion 10, and the gate electrode 20 is provided in plural in the X direction, for example, and extends in the Y direction.

導電部１０は、第１部分１１、第２部分１２、第３部分１３、及び第４部分１４を有する。第１部分１１は、Ｘ方向においてｐ形ベース領域２の一部と並んでいる。第２部分１２は、Ｘ方向においてｎ＋形ソース領域３と並んでいる。第３部分１３は、ｎ＋形ソース領域３よりも上方に位置し、Ｘ方向において絶縁層２５と並んでいる。第４部分１４は、第１部分１１と第２部分１２との間に位置し、Ｘ方向においてｎ＋形ソース領域３と並んでいる。導電部１０には、ボイドＶが設けられていても良い。ボイドＶの少なくとも一部は、第１部分１１中に設けられる。 The conductive portion 10 includes a first portion 11, a second portion 12, a third portion 13, and a fourth portion 14. The first portion 11 is aligned with a part of the p-type base region 2 in the X direction. The second portion 12 is aligned with the n + -type source region 3 in the X direction. The third portion 13 is located above the n + -type source region 3 and is aligned with the insulating layer 25 in the X direction. The fourth portion 14 is located between the first portion 11 and the second portion 12 and is aligned with the n + -type source region 3 in the X direction. A void V may be provided in the conductive portion 10. At least a part of the void V is provided in the first portion 11.

図２は、図１の一部を拡大した断面図である。
図２に表したように、第１部分１１のＸ方向における長さＬ１は、第２部分１２のＸ方向における長さＬ２よりも長い。第３部分１３のＸ方向における長さＬ３は、長さＬ２よりも長い。長さＬ３は、長さＬ１よりも長くても良いし、短くても良い。第４部分１４のＸ方向における長さＬ４は、長さＬ２よりも長い。 FIG. 2 is an enlarged cross-sectional view of a part of FIG.
As illustrated in FIG. 2, the length L1 of the first portion 11 in the X direction is longer than the length L2 of the second portion 12 in the X direction. The length L3 in the X direction of the third portion 13 is longer than the length L2. The length L3 may be longer or shorter than the length L1. The length L4 in the X direction of the fourth portion 14 is longer than the length L2.

長さＬ１は、長さＬ２の１．０倍より大きく２．５倍以下であることが望ましい。第１部分１１のＸ方向における長さおよび第２部分１２のＸ方向における長さがＺ方向において変化している場合、第１部分１１の最も長いＸ方向における長さが、第２部分１２の最も短いＸ方向における長さの１．０倍より大きく３．０倍以下であることが望ましい。   The length L1 is desirably greater than 1.0 times and less than or equal to 2.5 times the length L2. When the length of the first portion 11 in the X direction and the length of the second portion 12 in the X direction are changed in the Z direction, the length of the first portion 11 in the X direction is the length of the second portion 12. It is desirable that it is greater than 1.0 times and not more than 3.0 times the length in the shortest X direction.

ｐ＋形コンタクト領域４は、第１領域４ａを有する。第１領域４ａは、Ｘ方向において第１部分１１とゲート電極２０との間に位置する。ｐ＋形コンタクト領域４は、導電部１０に沿って設けられている。このため、例えば、第１領域４ａのＸ方向における長さＬ５は、第１領域４ａのＺ方向における長さＬ６よりも短い。 The p + -type contact region 4 has a first region 4a. The first region 4a is located between the first portion 11 and the gate electrode 20 in the X direction. The p + -type contact region 4 is provided along the conductive portion 10. Therefore, for example, the length L5 in the X direction of the first region 4a is shorter than the length L6 in the Z direction of the first region 4a.

ｐ形ベース領域２は、Ｘ方向において第１部分１１と並ぶ第２領域２ｂを有する。第２領域２ｂは、Ｘ方向において第１部分１１とゲート電極２０との間に位置する。ｎ＋形ソース領域３は、Ｘ方向において第２部分１２と並ぶ第３領域３ｃを有する。第３領域３ｃの少なくとも一部は、例えば、Ｘ方向において第２部分１２とゲート電極２０との間に位置する。第３領域３ｃのＸ方向における長さＬ８は、第２領域２ｂのＸ方向における長さＬ７よりも長い。また、長さＬ５は、長さＬ７よりも短い。 The p-type base region 2 has a second region 2b aligned with the first portion 11 in the X direction. The second region 2b is located between the first portion 11 and the gate electrode 20 in the X direction. The n + -type source region 3 has a third region 3c aligned with the second portion 12 in the X direction. At least a part of the third region 3c is located, for example, between the second portion 12 and the gate electrode 20 in the X direction. The length L8 in the X direction of the third region 3c is longer than the length L7 in the X direction of the second region 2b. Further, the length L5 is shorter than the length L7.

ｐ形ベース領域２におけるｐ形不純物濃度は、例えば、１．０×１０１７ａｔｏｍｓ／ｃｍ３以上、１．０×１０１８ａｔｏｍｓ／ｃｍ３以下である。ｐ＋形コンタクト領域４におけるｐ形不純物濃度は、例えば、１．０×１０１９ａｔｏｍｓ／ｃｍ３以上、５．０×１０２１ａｔｏｍｓ／ｃｍ３以下である。これらの半導体領域がｎ形不純物とｐ形不純物を含んでいる場合は、例えば、ｐ形の不純物濃度からｎ形の不純物濃度を減じた値が上記の範囲内にある。 The p-type impurity concentration in the p-type base region 2 is, for example, 1.0 × 10 17 atoms / cm 3 or more and 1.0 × 10 18 atoms / cm 3 or less. The p-type impurity concentration in the p + -type contact region 4 is, for example, 1.0 × 10 19 atoms / cm 3 or more and 5.0 × 10 21 atoms / cm 3 or less. When these semiconductor regions contain an n-type impurity and a p-type impurity, for example, a value obtained by subtracting the n-type impurity concentration from the p-type impurity concentration is within the above range.

半導体装置１００の動作を説明する。
ソース電極３２に対してドレイン電極３１に正電圧が印加された状態で、ゲート電極２０に閾値以上の電圧が印加されると、ｐ形ベース領域２のゲート絶縁層２１近傍にチャネル（反転層）が形成される。これにより、半導体装置１００がオン状態となる。電子は、チャネルを通ってソース電極３２からドレイン電極３１へ流れる。その後、ゲート電極２０に印加される電圧が閾値よりも低くなると、ｐ形ベース領域２におけるチャネルが消滅し、半導体装置１００がオフ状態になる。 The operation of the semiconductor device 100 will be described.
When a positive voltage or higher is applied to the gate electrode 20 with a positive voltage applied to the drain electrode 31 with respect to the source electrode 32, a channel (inversion layer) is formed in the vicinity of the gate insulating layer 21 in the p-type base region 2. Is formed. As a result, the semiconductor device 100 is turned on. Electrons flow from the source electrode 32 to the drain electrode 31 through the channel. Thereafter, when the voltage applied to the gate electrode 20 becomes lower than the threshold value, the channel in the p-type base region 2 disappears, and the semiconductor device 100 is turned off.

各構成要素の材料の一例を説明する。
ｎ−形ドリフト領域１、ｐ形ベース領域２、ｎ＋形ソース領域３、ｐ＋形コンタクト領域４、及びｎ＋形ドレイン領域５は、半導体材料として、シリコン、炭化シリコン、窒化ガリウム、またはガリウムヒ素を含む。半導体材料としてシリコンが用いられる場合、ｎ形不純物として、ヒ素、リン、またはアンチモンを用い、ｐ形不純物として、ボロンを用いることができる。
導電部１０は、チタンまたはタングステンなどの金属を含む。
ゲート電極２０は、ポリシリコンなどの導電材料を含む。
ゲート絶縁層２１及び絶縁層２５は、酸化シリコンなどの絶縁材料を含む。
ドレイン電極３１及びソース電極３２は、アルミニウムなどの金属を含む。 An example of the material of each component will be described.
The n − -type drift region 1, the p-type base region 2, the n + -type source region 3, the p + -type contact region 4, and the n + -type drain region 5 are made of silicon, silicon carbide, gallium nitride, or gallium as a semiconductor material. Contains arsenic. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity, and boron can be used as the p-type impurity.
The conductive portion 10 includes a metal such as titanium or tungsten.
The gate electrode 20 includes a conductive material such as polysilicon.
The gate insulating layer 21 and the insulating layer 25 include an insulating material such as silicon oxide.
The drain electrode 31 and the source electrode 32 include a metal such as aluminum.

図３〜図５を参照して、実施形態に係る半導体装置の製造方法の一例を説明する。
図３〜図５は、実施形態に係る半導体装置の製造工程を表す工程断面図である。 An example of a method for manufacturing a semiconductor device according to the embodiment will be described with reference to FIGS.
3 to 5 are process cross-sectional views illustrating the manufacturing process of the semiconductor device according to the embodiment.

まず、ｎ＋形半導体領域５ｍと、ｎ＋形半導体領域５ｍの上に設けられたｎ形半導体領域１ｍと、を有するシリコン製の半導体基板Ｓを用意する。ｎ形半導体領域１ｍの上面に、フォトリソグラフィ法及びＲＩＥ(Reactive Ion Etching)法を用いて、複数の開口ＯＰ１を形成する。半導体基板Ｓを熱酸化し、開口ＯＰ１の内壁及びｎ形半導体領域１ｍの上面に沿って絶縁層２１ｍを形成する。絶縁層２１ｍの上に、ＣＶＤ(Chemical Vapor Deposition)法を用いて、図３（ａ）に表したように、導電層２０ｍを形成する。複数の開口ＯＰ１は、導電層２０ｍにより埋め込まれる。 First, a silicon semiconductor substrate S having an n + -type semiconductor region 5m and an n-type semiconductor region 1m provided on the n + -type semiconductor region 5m is prepared. A plurality of openings OP1 are formed on the upper surface of the n-type semiconductor region 1m by using a photolithography method and an RIE (Reactive Ion Etching) method. The semiconductor substrate S is thermally oxidized to form an insulating layer 21m along the inner wall of the opening OP1 and the upper surface of the n-type semiconductor region 1m. A conductive layer 20m is formed on the insulating layer 21m as shown in FIG. 3A by using a CVD (Chemical Vapor Deposition) method. The plurality of openings OP1 are filled with the conductive layer 20m.

ＣＭＰ(Chemical Mechanical Polishing)法を用いて、導電層２０ｍの上面を後退させる。これにより、開口ＯＰ１内に設けられた導電層２０ｍ同士が分離され、複数のゲート電極２０が形成される。ｐ形不純物（例えばボロン）を、ゲート電極２０同士の間のｎ形半導体領域１ｍにイオン注入し、ｐ形半導体領域２ｍを形成する。ｎ形不純物（例えばリン）を、ｐ形半導体領域２ｍの表面にイオン注入し、図３（ｂ）に表したように、ｎ＋形半導体領域３ｍを形成する。 The upper surface of the conductive layer 20m is retreated using a CMP (Chemical Mechanical Polishing) method. Thereby, the conductive layers 20m provided in the opening OP1 are separated from each other, and a plurality of gate electrodes 20 are formed. A p-type impurity (for example, boron) is ion-implanted into the n-type semiconductor region 1m between the gate electrodes 20 to form the p-type semiconductor region 2m. An n-type impurity (for example, phosphorus) is ion-implanted into the surface of the p-type semiconductor region 2m to form an n + -type semiconductor region 3m as shown in FIG.

絶縁層２１ｍの一部を除去し、ｎ＋形半導体領域３ｍの上面を露出させる。残った絶縁層２１ｍは、ゲート絶縁層２１に対応する。ゲート電極２０及びｎ＋形半導体領域３ｍを覆う絶縁層２５ｍを形成する。図３（ｃ）に表したように、絶縁層２５ｍをＺ方向に貫通し、ｎ＋形半導体領域３ｍに達する開口ＯＰ２を形成する。 A part of the insulating layer 21m is removed, and the upper surface of the n + -type semiconductor region 3m is exposed. The remaining insulating layer 21 m corresponds to the gate insulating layer 21. An insulating layer 25m is formed to cover the gate electrode 20 and the n + -type semiconductor region 3m. As shown in FIG. 3C, an opening OP2 that penetrates the insulating layer 25m in the Z direction and reaches the n + -type semiconductor region 3m is formed.

開口ＯＰ２の内壁及び絶縁層２５ｍの上面に沿って保護層２６を形成する。保護層２６は、開口ＯＰ２を埋め込まないように形成される。保護層２６は、例えば、窒化シリコンなどを含む。図３（ｄ）に表したように、開口ＯＰ２底面の保護層２６を除去し、ｎ＋形半導体領域３ｍを露出させる。 A protective layer 26 is formed along the inner wall of the opening OP2 and the upper surface of the insulating layer 25m. The protective layer 26 is formed so as not to fill the opening OP2. The protective layer 26 includes, for example, silicon nitride. As shown in FIG. 3D, the protective layer 26 on the bottom surface of the opening OP2 is removed to expose the n + -type semiconductor region 3m.

保護層２６をマスクとして用いて、異方性エッチングと等方性エッチングを交互に行い、ｐ形半導体領域２ｍの一部及びｎ＋形半導体領域３ｍの一部を除去する。これにより、図４（ａ）に表したように、開口ＯＰ２に連なる開口ＯＰ３が形成される。開口ＯＰ３の幅（Ｘ方向における寸法）は、開口ＯＰ２の幅よりも広い。異方性エッチングとしては、ハロゲン元素（例えば臭素）を含むガスを使用したＲＩＥが用いられる。等方性エッチングとしては、ハロゲン元素を含むガスを使用したＣＤＥ(Chemical Dry Etching)、または水酸化カリウムなどを使用したウェットエッチングが用いられる。 Using the protective layer 26 as a mask, anisotropic etching and isotropic etching are alternately performed to remove a part of the p-type semiconductor region 2m and a part of the n + -type semiconductor region 3m. As a result, as shown in FIG. 4A, an opening OP3 continuous with the opening OP2 is formed. The width of the opening OP3 (the dimension in the X direction) is wider than the width of the opening OP2. As the anisotropic etching, RIE using a gas containing a halogen element (for example, bromine) is used. As the isotropic etching, CDE (Chemical Dry Etching) using a gas containing a halogen element, or wet etching using potassium hydroxide or the like is used.

保護層２６を除去する。図４（ｂ）に表したように、ｐ形不純物を含む不純物層２７を、開口ＯＰ３の内壁に沿って形成する。不純物層２７は、さらに、開口ＯＰ２の内壁及び絶縁層２５の上面に沿って形成されても良い。不純物層２７は、例えば、開口ＯＰ２及び開口ＯＰ３を埋め込まないように形成される。不純物層２７は、例えば、ＢＳＧ(Boron-Silicate Glass)を含む。   The protective layer 26 is removed. As shown in FIG. 4B, an impurity layer 27 containing a p-type impurity is formed along the inner wall of the opening OP3. The impurity layer 27 may be further formed along the inner wall of the opening OP2 and the upper surface of the insulating layer 25. For example, the impurity layer 27 is formed so as not to fill the opening OP2 and the opening OP3. The impurity layer 27 includes, for example, BSG (Boron-Silicate Glass).

熱処理を行うことで、不純物層２７に含まれるｐ形不純物（ボロン）が、ｐ形半導体領域２ｍ及びｎ＋形半導体領域３ｍに拡散する。これにより、図４（ｃ）に表したように、ｐ形半導体領域２ｍの不純物層２７と接する部分にｐ＋形コンタクト領域４が形成される。ｐ＋形コンタクト領域４は、さらに、ｎ＋形半導体領域３ｍの不純物層２７と接する部分の少なくとも一部に形成されても良い。このとき、ｎ＋形半導体領域３ｍの下部のｎ形不純物濃度は、ｎ＋形半導体領域３ｍの上部のｎ形不純物濃度よりも低い。このため、例えば、ｎ＋形半導体領域３ｍでは、不純物層２７と接する部分の下部の導電形が、ｎ形からｐ形に反転する。ｐ＋形コンタクト領域４以外のｐ形半導体領域２ｍ及びｎ＋形半導体領域３ｍは、それぞれ、ｐ形ベース領域２及びｎ＋形ソース領域３に対応する。 By performing the heat treatment, the p-type impurity (boron) contained in the impurity layer 27 diffuses into the p-type semiconductor region 2m and the n + -type semiconductor region 3m. As a result, as shown in FIG. 4C, the p + -type contact region 4 is formed in the portion of the p-type semiconductor region 2m in contact with the impurity layer 27. The p + -type contact region 4 may be further formed in at least a part of a portion in contact with the impurity layer 27 of the n + -type semiconductor region 3m. At this time, the n-type impurity concentration of the bottom of the n + type semiconductor region 3m is lower than the n-type impurity concentration of the upper part of the n + type semiconductor region 3m. Therefore, for example, in the n + -type semiconductor region 3m, the conductivity type below the portion in contact with the impurity layer 27 is inverted from the n-type to the p-type. The p-type semiconductor region 2m and the n + -type semiconductor region 3m other than the p + -type contact region 4 correspond to the p-type base region 2 and the n + -type source region 3, respectively.

不純物層２７を除去する。フォトリソグラフィ法及びＲＩＥ法を用いて絶縁層２５ｍの一部を除去し、図４（ｄ）に表したように、開口ＯＰ２の幅を広げる。図５（ａ）に表したように、開口ＯＰ２の内壁及び開口ＯＰ３の内壁に沿って、チタン層１０ａ、窒化チタン層１０ｂ、及びタングステン層１０ｃを順次積層させ、これらの層を含む導電層１０ｍを形成する。図５（ｂ）に表したように、絶縁層２５ｍの上に設けられた導電層１０ｍの一部を除去する。残った導電層１０ｍは、導電部１０に対応する。   The impurity layer 27 is removed. A part of the insulating layer 25m is removed by photolithography and RIE, and the width of the opening OP2 is increased as shown in FIG. As shown in FIG. 5A, a titanium layer 10a, a titanium nitride layer 10b, and a tungsten layer 10c are sequentially stacked along the inner wall of the opening OP2 and the inner wall of the opening OP3, and the conductive layer 10m including these layers is stacked. Form. As shown in FIG. 5B, a part of the conductive layer 10m provided on the insulating layer 25m is removed. The remaining conductive layer 10 m corresponds to the conductive portion 10.

絶縁層２５ｍの上に、導電層１０ｍと接するソース電極３２を形成する。図５（ｃ）に表したように、ｎ＋形半導体領域５ｍの厚み（Ｚ方向における長さ）が所定の値になるまで、半導体基板Ｓの裏面を研削する。残ったｎ＋形半導体領域５ｍは、ｎ＋形ドレイン領域５に対応する。図５（ｄ）に表したように、研削後の半導体基板Ｓの裏面にドレイン電極３１を形成する。以上の工程により、図１及び図２に表した実施形態に係る半導体装置１００が製造される。 A source electrode 32 in contact with the conductive layer 10m is formed on the insulating layer 25m. As shown in FIG. 5C, the back surface of the semiconductor substrate S is ground until the thickness of the n + -type semiconductor region 5m (length in the Z direction) reaches a predetermined value. The remaining n + -type semiconductor region 5 m corresponds to the n + -type drain region 5. As shown in FIG. 5D, the drain electrode 31 is formed on the back surface of the semiconductor substrate S after grinding. Through the above steps, the semiconductor device 100 according to the embodiment shown in FIGS. 1 and 2 is manufactured.

実施形態の効果を、図６を参照しつつ説明する。
図６は、参考例に係る半導体装置の一部を表す断面図である。
図６に表した半導体装置１００ｒでは、第１部分１１のＸ方向における長さＬ１ａと第２部分１２のＸ方向における長さＬ２ａが同じである。また、ｐ＋形コンタクト領域４は、第１部分１１下部の周りに設けられている。 The effects of the embodiment will be described with reference to FIG.
FIG. 6 is a cross-sectional view illustrating a part of a semiconductor device according to a reference example.
In the semiconductor device 100r illustrated in FIG. 6, the length L1a in the X direction of the first portion 11 and the length L2a in the X direction of the second portion 12 are the same. The p + -type contact region 4 is provided around the lower portion of the first portion 11.

半導体装置のオン電流を増大させるためには、ゲート電極２０同士の間のＸ方向における距離Ｄ１（ｐ形ベース領域２の幅）が短いことが望ましい。距離Ｄ１を短くすることで、より多くのゲート電極２０を形成できる。この結果、半導体装置のオン状態において、より多くのチャネルが形成され、オン抵抗を低減できる。
また、ｎ＋形ソース領域３と導電部１０との間の電気抵抗を低減するためには、ｎ＋形ソース領域３と導電部１０との接触面積が大きいことが望ましい。接触面積を増加させるためには、第３部分１３のＸ方向における長さＬ３ａが長さＬ２ａ以上であることが望ましい。
一方、第３部分１３とゲート電極２０との間のＸ方向における距離Ｄ２が短いと、半導体装置の製造工程において、ｎ＋形ソース領域３とゲート電極２０とが導通する可能性がある。従って、図６に表した半導体装置１００ｒにおいて、距離Ｄ２を保ちつつ距離Ｄ１を短くするためには、長さＬ１ａ及び長さＬ２ａを短くする必要がある。
しかし、長さＬ２ａを短くすると、ｐ形ベース領域２（ｐ＋形コンタクト領域４）と導電部１０との接触面積が減少し、ｐ形ベース領域２から導電部１０へ正孔が排出され難くなる。正孔が排出され難いと、半導体装置がアバランシェ状態の際、ｐ形ベース領域２の電位が上昇し易くなる。この結果、ｎ−形ドリフト領域１、ｐ形ベース領域２、及びｎ＋形ソース領域３から構成される寄生ＮＰＮトランジスタが動作し易くなり、半導体装置の破壊が生じる可能性が高まる。 In order to increase the on-current of the semiconductor device, it is desirable that the distance D1 (width of the p-type base region 2) in the X direction between the gate electrodes 20 is short. More gate electrodes 20 can be formed by shortening the distance D1. As a result, more channels are formed in the on state of the semiconductor device, and the on-resistance can be reduced.
Further, in order to reduce the electrical resistance between the n + -type source region 3 and the conductive portion 10, contact area between the n + -type source region 3 and the conductive portion 10 is large is desirable. In order to increase the contact area, it is desirable that the length L3a in the X direction of the third portion 13 is not less than the length L2a.
On the other hand, if the distance D2 in the X direction between the third portion 13 and the gate electrode 20 is short, there is a possibility that the n + -type source region 3 and the gate electrode 20 are electrically connected in the manufacturing process of the semiconductor device. Therefore, in the semiconductor device 100r shown in FIG. 6, in order to shorten the distance D1 while maintaining the distance D2, it is necessary to shorten the length L1a and the length L2a.
However, if the length L2a is shortened, the contact area between the p-type base region 2 (p + -type contact region 4) and the conductive portion 10 decreases, and holes are not easily discharged from the p-type base region 2 to the conductive portion 10. Become. If holes are not easily discharged, the potential of the p-type base region 2 is likely to rise when the semiconductor device is in an avalanche state. As a result, the parasitic NPN transistor composed of the n − -type drift region 1, the p-type base region 2, and the n + -type source region 3 becomes easy to operate, and the possibility that the semiconductor device is broken increases.

実施形態に係る半導体装置１００では、第１部分１１のＸ方向における長さＬ１が、第２部分１２のＸ方向における長さＬ２よりも長い。このため、距離Ｄ１を短くするために長さＬ２を短くした場合でも、ｐ形ベース領域２から導電部１０へ正孔が効率的に排出される。従って、実施形態によれば、半導体装置における寄生トランジスタの動作を抑制しつつ、半導体装置のオン抵抗を低減できる。   In the semiconductor device 100 according to the embodiment, the length L1 of the first portion 11 in the X direction is longer than the length L2 of the second portion 12 in the X direction. For this reason, even when the length L2 is shortened in order to shorten the distance D1, holes are efficiently discharged from the p-type base region 2 to the conductive portion 10. Therefore, according to the embodiment, the on-resistance of the semiconductor device can be reduced while suppressing the operation of the parasitic transistor in the semiconductor device.

また、距離Ｄ１を短くした際に、ｐ＋形コンタクト領域４とゲート絶縁層２１との間の距離が短くなると、半導体装置をターンオンさせるためのゲート電圧の閾値が変動する可能性がある。ゲート電圧の閾値が変動すると、半導体装置の動作が不安定となる。
半導体装置１００では、ｐ＋形コンタクト領域４は、図２に表したように第１部分１１に沿って設けられている。例えば、ｐ＋形コンタクト領域４の第１領域４ａのＸ方向における長さＬ５は、第１領域４ａのＺ方向における長さＬ６よりも短い。この構成によれば、ｐ＋形コンタクト領域４とゲート絶縁層２１との間のＸ方向における距離の短縮を抑制しつつ、距離Ｄ１を短くできる。すなわち、動作の安定性の低下を抑制しつつ、半導体装置のオン抵抗を低減できる。 Further, when the distance D1 is shortened, if the distance between the p + -type contact region 4 and the gate insulating layer 21 is shortened, the threshold value of the gate voltage for turning on the semiconductor device may change. When the threshold value of the gate voltage fluctuates, the operation of the semiconductor device becomes unstable.
In the semiconductor device 100, the p + -type contact region 4 is provided along the first portion 11 as shown in FIG. For example, the length L5 in the X direction of the first region 4a of the p + -type contact region 4 is shorter than the length L6 in the Z direction of the first region 4a. According to this configuration, the distance D1 can be shortened while suppressing the shortening of the distance in the X direction between the p + -type contact region 4 and the gate insulating layer 21. That is, the on-resistance of the semiconductor device can be reduced while suppressing a decrease in operational stability.

ｐ＋形コンタクト領域４は、ｐ形ベース領域２と導電部１０との間だけでなく、ｎ＋形ソース領域３と導電部１０との間にも設けられていることが望ましい。ｐ＋形コンタクト領域４の一部がｎ＋形ソース領域３と導電部１０との間に設けられていることで、ｐ＋形コンタクト領域４と導電部１０との接触面積をさらに増加できる。これにより、アバランシェ状態において正孔がソース電極３２へより排出され易くなり、寄生トランジスタがより動作し難くなる。 The p + -type contact region 4 is preferably provided not only between the p-type base region 2 and the conductive portion 10 but also between the n + -type source region 3 and the conductive portion 10. Since a part of the p + -type contact region 4 is provided between the n + -type source region 3 and the conductive portion 10, the contact area between the p + -type contact region 4 and the conductive portion 10 can be further increased. Accordingly, holes are more easily discharged to the source electrode 32 in the avalanche state, and the parasitic transistor becomes more difficult to operate.

第１部分１１には、図１及び図２に表したように、ボイドＶが設けられていることが望ましい。ボイドＶが設けられることで、第１部分１１の体積が減少する。第１部分１１の体積が減少すると、温度変化による第１部分１１の体積の変化が小さくなる。この結果、第１部分１１の体積変化により、第１部分１１の下方に位置する、ｎ−形ドリフト領域１とｐ形ベース領域２とのｐｎ接合面に加わる応力を低減できる。ｐｎ接合面に加わる応力が低減されることで、ｐｎ接合面における結晶欠陥の発生を抑制でき、リーク電流の発生を抑制できる。 As shown in FIGS. 1 and 2, the first portion 11 is preferably provided with a void V. By providing the void V, the volume of the first portion 11 is reduced. When the volume of the first portion 11 is reduced, the change in the volume of the first portion 11 due to the temperature change is reduced. As a result, the stress applied to the pn junction surface between the n − -type drift region 1 and the p-type base region 2 located below the first portion 11 due to the volume change of the first portion 11 can be reduced. By reducing the stress applied to the pn junction surface, generation of crystal defects on the pn junction surface can be suppressed, and generation of leakage current can be suppressed.

また、ｎ＋形ソース領域３と導電部１０との接触面積を増加させるためには、図２に表した長さＬ３は、長さＬ２以上であることが望ましい。より望ましくは、長さＬ３は、長さＬ２よりも長い。 Further, in order to increase the contact area between the n + -type source region 3 and the conductive portion 10, the length L3 shown in FIG. 2 is desirably equal to or longer than the length L2. More desirably, the length L3 is longer than the length L2.

図７及び図８は、実施形態の変形例に係る半導体装置の一部を表す断面図である。
図７（ａ）に表した半導体装置１１０では、ｐ＋形コンタクト領域４が、ｐ形ベース領域２と導電部１０との間にのみ設けられ、ｎ＋形ソース領域３と導電部１０との間に設けられていない。
図７（ｂ）に表した半導体装置１２０では、導電部１０が、第４部分１４を有していない。すなわち、第１部分１１よりもＸ方向における長さが短い第２部分１２が、Ｘ方向において、ｎ＋形ソース領域３の全体と並んでいる。 7 and 8 are cross-sectional views illustrating a part of a semiconductor device according to a modified example of the embodiment.
In the semiconductor device 110 shown in FIG. 7A, the p + -type contact region 4 is provided only between the p-type base region 2 and the conductive portion 10, and the n + -type source region 3 and the conductive portion 10 are It is not provided in between.
In the semiconductor device 120 illustrated in FIG. 7B, the conductive portion 10 does not have the fourth portion 14. That is, the second portion 12 having a shorter length in the X direction than the first portion 11 is aligned with the entire n + -type source region 3 in the X direction.

図８（ａ）に表した半導体装置１３０では、第１部分１１の形状が、半導体装置１００と異なる。半導体装置１００では、第１部分１１のＸ方向における長さは、Ｚ方向において略一様である。半導体装置１３０では、第１部分１１のＸ方向における長さは、下方に向かうほど増加した後、減少している。
図８（ｂ）に表した半導体装置１４０では、第１部分１１の上部のＸ方向における長さが、第１部分１１の下部のＸ方向における長さと異なる。具体的には、第１部分１１の上部のＸ方向における長さが、第１部分１１の下部のＸ方向における長さよりも長い。または、第１部分１１の下部のＸ方向における長さが、第１部分１１の上部のＸ方向における長さよりも長くても良い。 In the semiconductor device 130 illustrated in FIG. 8A, the shape of the first portion 11 is different from that of the semiconductor device 100. In the semiconductor device 100, the length of the first portion 11 in the X direction is substantially uniform in the Z direction. In the semiconductor device 130, the length in the X direction of the first portion 11 increases and then decreases as it goes downward.
In the semiconductor device 140 illustrated in FIG. 8B, the length of the upper portion of the first portion 11 in the X direction is different from the length of the lower portion of the first portion 11 in the X direction. Specifically, the length of the upper portion of the first portion 11 in the X direction is longer than the length of the lower portion of the first portion 11 in the X direction. Alternatively, the length of the lower portion of the first portion 11 in the X direction may be longer than the length of the upper portion of the first portion 11 in the X direction.

このように、第１部分１１の少なくとも一部のＸ方向における長さが、第２部分１２の少なくとも一部のＸ方向における長さよりも長ければ、導電部１０の具体的な形状は適宜変更可能である。   Thus, if the length in the X direction of at least a part of the first part 11 is longer than the length in the X direction of at least a part of the second part 12, the specific shape of the conductive part 10 can be changed as appropriate. It is.

図９は、実施形態の変形例に係る半導体装置の一部を表す斜視断面図である。
図９に表した半導体装置１５０は、ＩＧＢＴ(Insulated Gate Bipolar Transistor)である。半導体装置１５０は、ｎ＋形ドレイン領域５に代えて、ｐ＋形コレクタ領域６（第５半導体領域）及びｎ形バッファ領域７を有する。また、半導体装置１５０において、電極３１はコレクタ電極として機能し、電極３２はエミッタ電極として機能する。ｎ＋形ソース領域３は、エミッタ領域として機能する。ｐ＋形コレクタ領域６は、コレクタ電極３１と電気的に接続されている。ｎ形バッファ領域７は、ｐ＋形コレクタ領域６とｎ−形ドリフト領域１との間に設けられている。 FIG. 9 is a perspective sectional view showing a part of a semiconductor device according to a modification of the embodiment.
The semiconductor device 150 shown in FIG. 9 is an IGBT (Insulated Gate Bipolar Transistor). The semiconductor device 150 includes a p + -type collector region 6 (fifth semiconductor region) and an n-type buffer region 7 instead of the n + -type drain region 5. In the semiconductor device 150, the electrode 31 functions as a collector electrode, and the electrode 32 functions as an emitter electrode. The n + -type source region 3 functions as an emitter region. The p + -type collector region 6 is electrically connected to the collector electrode 31. The n-type buffer region 7 is provided between the p + -type collector region 6 and the n − -type drift region 1.

ＩＧＢＴである半導体装置１５０においても、第１部分１１のＸ方向における長さを、第２部分１２のＸ方向における長さよりも長くすることで、半導体装置における寄生トランジスタの動作を抑制しつつ、半導体装置のオン抵抗を低減できる。
また、半導体装置１５０において、導電部１０の具体的な形状は、図７及び図８に表した例と同様に、適宜変更可能である。 Also in the semiconductor device 150 that is an IGBT, the length of the first portion 11 in the X direction is made longer than the length of the second portion 12 in the X direction, thereby suppressing the operation of the parasitic transistor in the semiconductor device. The on-resistance of the device can be reduced.
Further, in the semiconductor device 150, the specific shape of the conductive portion 10 can be appropriately changed as in the example shown in FIGS.

以上で説明した各実施形態における、各半導体領域の間の不純物濃度の相対的な高低については、例えば、ＳＣＭ（走査型静電容量顕微鏡）を用いて確認することが可能である。なお、各半導体領域におけるキャリア濃度は、各半導体領域において活性化している不純物濃度と等しいものとみなすことができる。従って、各半導体領域の間のキャリア濃度の相対的な高低についても、ＳＣＭを用いて確認することができる。
また、各半導体領域における不純物濃度については、例えば、ＳＩＭＳ（二次イオン質量分析法）により測定することが可能である。 The relative level of the impurity concentration between the semiconductor regions in each of the embodiments described above can be confirmed using, for example, an SCM (scanning capacitance microscope). The carrier concentration in each semiconductor region can be regarded as being equal to the impurity concentration activated in each semiconductor region. Therefore, the relative level of the carrier concentration between the semiconductor regions can also be confirmed using the SCM.
The impurity concentration in each semiconductor region can be measured by, for example, SIMS (secondary ion mass spectrometry).

以上、本発明のいくつかの実施形態を例示したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更などを行うことができる。これら実施形態やその変形例は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。また、前述の各実施形態は、相互に組み合わせて実施することができる。   As mentioned above, although several embodiment of this invention was illustrated, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, changes, and the like can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and equivalents thereof. Further, the above-described embodiments can be implemented in combination with each other.

１ ｎ−形ドリフト領域、 １ｍ ｎ−形半導体領域、 ２ ｐ形ベース領域、 ２ｂ 第２領域、 ２ｍ ｐ形半導体領域、 ３ ｎ＋形ソース領域、 ３ｃ 第３領域、 ３ｍ ｎ＋形半導体領域、 ４ ｐ＋形コンタクト領域、 ４ａ 第１領域、 ５ ｎ＋形ドレイン領域、 ５ｍ ｎ＋形半導体領域、 ６ ｐ＋形コレクタ領域、 ７ ｎ形バッファ領域、 １０ 導電部、 １０ａ チタン層、 １０ｂ 窒化チタン層、 １０ｃ タングステン層、 １０ｍ 導電層、 １１ 第１部分、 １２ 第２部分、 １３ 第３部分、 １４ 第４部分、 ２０ ゲート電極、 ２０ｍ 導電層、 ２１ ゲート絶縁層、 ２１ｍ、２５、２５ｍ 絶縁層、 ２６ 保護層、 ２７ 不純物層、 ３１ ドレイン電極、 ３２ ソース電極、 １００〜１４０、１００ｒ 半導体装置、 ＯＰ１〜ＯＰ３ 開口、 Ｓ 半導体基板、 Ｖ ボイド 1 n − type drift region, 1 m n − type semiconductor region, 2 p type base region, 2b second region, 2m p type semiconductor region, 3 n + type source region, 3c third region, 3m n + type semiconductor region, 4 p + type contact region, 4a first region, 5 n + type drain region, 5m n + type semiconductor region, 6 p + type collector region, 7 n type buffer region, 10 conductive part, 10a titanium layer, 10b titanium nitride Layer, 10c tungsten layer, 10m conductive layer, 11 first part, 12 second part, 13 third part, 14 fourth part, 20 gate electrode, 20m conductive layer, 21 gate insulating layer, 21m, 25, 25m insulating layer , 26 protective layer, 27 impurity layer, 31 drain electrode, 32 source electrode, 100 to 140, 100r semiconductor device, OP1 to OP3 opening, S semiconductor Plate, V void

Claims (11)

第１導電形の第１半導体領域と、
前記第１半導体領域の上に設けられた第２導電形の第２半導体領域と、
前記第２半導体領域の上に設けられた第１導電形の第３半導体領域と、
前記第２半導体領域から前記第３半導体領域に向かう第１方向に対して垂直な第２方向において、前記第１半導体領域の一部、前記第２半導体領域、及び前記第３半導体領域とゲート絶縁層を介して対向するゲート電極と、
前記第２半導体領域の一部と前記第２方向において並ぶ第１部分と、前記第３半導体領域の少なくとも一部と前記第２方向において並ぶ第２部分と、を有し、前記第１部分の前記第２方向における長さは前記第２部分の前記第２方向における長さよりも長く、前記第２半導体領域及び前記第３半導体領域と電気的に接続された導電部と、
を備えた半導体装置。 A first semiconductor region of a first conductivity type;
A second semiconductor region of a second conductivity type provided on the first semiconductor region;
A third semiconductor region of a first conductivity type provided on the second semiconductor region;
In a second direction perpendicular to the first direction from the second semiconductor region to the third semiconductor region, a part of the first semiconductor region, the second semiconductor region, and the third semiconductor region and gate insulation A gate electrode facing through the layer;
A first portion aligned with the second semiconductor region in the second direction; a second portion aligned with the at least a portion of the third semiconductor region in the second direction; A length in the second direction is longer than a length in the second direction of the second portion, and a conductive part electrically connected to the second semiconductor region and the third semiconductor region;
A semiconductor device comprising: 前記導電部は、前記第３半導体領域よりも上方に位置する第３部分をさらに有し、
前記第３部分の前記第２方向における長さは、前記第２部分の前記長さ以上である請求項１記載の半導体装置。 The conductive portion further includes a third portion located above the third semiconductor region,
The semiconductor device according to claim 1, wherein a length of the third portion in the second direction is equal to or longer than the length of the second portion. 前記第２半導体領域と前記導電部との間に設けられた第２導電形の第４半導体領域をさらに備え、
前記第４半導体領域における第２導電形の不純物濃度は、前記第２半導体領域における第２導電形の不純物濃度よりも高い請求項１または２に記載の半導体装置。 A fourth semiconductor region of a second conductivity type provided between the second semiconductor region and the conductive portion;
3. The semiconductor device according to claim 1, wherein an impurity concentration of the second conductivity type in the fourth semiconductor region is higher than an impurity concentration of the second conductivity type in the second semiconductor region. 前記第４半導体領域は、前記第３半導体領域と前記導電部との間にさらに設けられた請求項３記載の半導体装置。   The semiconductor device according to claim 3, wherein the fourth semiconductor region is further provided between the third semiconductor region and the conductive portion. 前記第４半導体領域は、前記第２方向において前記第２半導体領域と前記第１部分との間に位置する第１領域を有し、
前記第１領域の前記第２方向における長さは、前記第１領域の前記第１方向における長さよりも短い請求項３または４に記載の半導体装置。 The fourth semiconductor region has a first region located between the second semiconductor region and the first portion in the second direction;
5. The semiconductor device according to claim 3, wherein a length of the first region in the second direction is shorter than a length of the first region in the first direction. 前記導電部中には、ボイドが設けられ、
前記ボイドの少なくとも一部は、前記第１部分中に設けられた請求項１〜５のいずれか１つに記載の半導体装置。 In the conductive part, a void is provided,
The semiconductor device according to claim 1, wherein at least a part of the void is provided in the first portion. 前記第２半導体領域は、前記第２方向において前記第１部分と並ぶ第２領域を有し、
前記第３半導体領域は、前記第２方向において前記第２部分と並ぶ第３領域を有し、
前記第３領域の前記第２方向における長さは、前記第２領域の前記第２方向における長さよりも長い請求項１〜６のいずれか１つに記載の半導体装置。 The second semiconductor region has a second region aligned with the first portion in the second direction;
The third semiconductor region includes a third region aligned with the second portion in the second direction;
7. The semiconductor device according to claim 1, wherein a length of the third region in the second direction is longer than a length of the second region in the second direction. 前記導電部は、前記第１方向において前記第１部分と前記第２部分との間に位置する第４部分をさらに有し、
前記第４部分は、前記第２方向において前記第３半導体領域の一部と並び、
前記第４部分の前記第２方向における長さは、前記第２部分の前記長さよりも長い請求項１〜７のいずれか１つに記載の半導体装置。 The conductive portion further includes a fourth portion located between the first portion and the second portion in the first direction,
The fourth portion is aligned with a portion of the third semiconductor region in the second direction;
8. The semiconductor device according to claim 1, wherein a length of the fourth portion in the second direction is longer than the length of the second portion. 前記第１部分の少なくとも一部の前記第２方向における長さは、前記第２部分の少なくとも一部の前記第２方向における長さの、１．０倍より大きく、２．５倍以下である請求項１〜８のいずれか１つに記載の半導体装置。   The length of at least a part of the first part in the second direction is greater than 1.0 times and not more than 2.5 times the length of the at least part of the second part in the second direction. The semiconductor device according to claim 1. 前記第１半導体領域と電気的に接続された第１電極と、
前記導電部と電気的に接続された第２電極と、
をさらに備えた請求項１〜９のいずれか１つに記載の半導体装置。 A first electrode electrically connected to the first semiconductor region;
A second electrode electrically connected to the conductive portion;
The semiconductor device according to claim 1, further comprising: 前記第１電極と前記第１半導体領域との間に設けられた第２導電形の第５半導体領域をさらに備え、
前記第５半導体領域は、前記第１電極と電気的に接続され、
前記第５半導体領域における第２導電形の不純物濃度は、前記第２半導体領域における第２導電形の不純物濃度よりも高い請求項１０記載の半導体装置。 A fifth semiconductor region of a second conductivity type provided between the first electrode and the first semiconductor region;
The fifth semiconductor region is electrically connected to the first electrode;
The semiconductor device according to claim 10, wherein an impurity concentration of the second conductivity type in the fifth semiconductor region is higher than an impurity concentration of the second conductivity type in the second semiconductor region.
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63224260A (en) * 1987-03-12 1988-09-19 Nippon Denso Co Ltd Conductivity modulation type mosfet
JPH02181471A (en) * 1989-01-06 1990-07-16 Mitsubishi Electric Corp Insulation gate type bipolar transistor
JP2007531298A (en) * 2004-03-31 2007-11-01 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Trench type semiconductor device and manufacturing method thereof
JP2008530800A (en) * 2005-02-11 2008-08-07 アルファ アンド オメガ セミコンダクター インコーポレイテッド Power MOS device
JP2010103208A (en) * 2008-10-22 2010-05-06 Denso Corp Semiconductor device
JP2011204808A (en) * 2010-03-25 2011-10-13 Panasonic Corp Semiconductor device and method of manufacturing the same
CN103489785A (en) * 2013-09-03 2014-01-01 上海恺创电子有限公司 Cell structure of super junction semiconductor device and technology realizing method
JP2014067754A (en) * 2012-09-24 2014-04-17 Toshiba Corp Semiconductor device and method for manufacturing the same
JP2017034040A (en) * 2015-07-30 2017-02-09 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2018014392A (en) * 2016-07-20 2018-01-25 ローム株式会社 Semiconductor device and method for manufacturing the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006324488A (en) * 2005-05-19 2006-11-30 Nec Electronics Corp Semiconductor device and manufacturing method thereof
DE102007003812B4 (en) * 2007-01-25 2011-11-17 Infineon Technologies Ag Semiconductor device with trench gate and method of manufacture

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63224260A (en) * 1987-03-12 1988-09-19 Nippon Denso Co Ltd Conductivity modulation type mosfet
JPH02181471A (en) * 1989-01-06 1990-07-16 Mitsubishi Electric Corp Insulation gate type bipolar transistor
JP2007531298A (en) * 2004-03-31 2007-11-01 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Trench type semiconductor device and manufacturing method thereof
JP2008530800A (en) * 2005-02-11 2008-08-07 アルファ アンド オメガ セミコンダクター インコーポレイテッド Power MOS device
JP2010103208A (en) * 2008-10-22 2010-05-06 Denso Corp Semiconductor device
JP2011204808A (en) * 2010-03-25 2011-10-13 Panasonic Corp Semiconductor device and method of manufacturing the same
JP2014067754A (en) * 2012-09-24 2014-04-17 Toshiba Corp Semiconductor device and method for manufacturing the same
CN103489785A (en) * 2013-09-03 2014-01-01 上海恺创电子有限公司 Cell structure of super junction semiconductor device and technology realizing method
JP2017034040A (en) * 2015-07-30 2017-02-09 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2018014392A (en) * 2016-07-20 2018-01-25 ローム株式会社 Semiconductor device and method for manufacturing the same

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