CN111952409A - Preparation method of passivated contact battery with selective emitter structure - Google Patents
Preparation method of passivated contact battery with selective emitter structure Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 131
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 131
- 239000010703 silicon Substances 0.000 claims abstract description 131
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 58
- 239000002002 slurry Substances 0.000 claims abstract description 53
- 238000007639 printing Methods 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 41
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 29
- 239000001301 oxygen Substances 0.000 claims abstract description 29
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 29
- 229910052796 boron Inorganic materials 0.000 claims abstract description 22
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000012298 atmosphere Substances 0.000 claims abstract description 17
- 230000008569 process Effects 0.000 claims abstract description 9
- 238000001035 drying Methods 0.000 claims abstract description 6
- 239000007789 gas Substances 0.000 claims abstract description 6
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000012805 post-processing Methods 0.000 claims abstract description 6
- ILAHWRKJUDSMFH-UHFFFAOYSA-N boron tribromide Chemical compound BrB(Br)Br ILAHWRKJUDSMFH-UHFFFAOYSA-N 0.000 claims description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 30
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 24
- 238000009792 diffusion process Methods 0.000 claims description 22
- 238000002161 passivation Methods 0.000 claims description 19
- 230000005641 tunneling Effects 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 17
- 239000005388 borosilicate glass Substances 0.000 claims description 16
- 238000004140 cleaning Methods 0.000 claims description 16
- 238000000137 annealing Methods 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 14
- 238000001465 metallisation Methods 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 8
- XYFCBTPGUUZFHI-UHFFFAOYSA-N phosphine group Chemical group P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 8
- 238000005245 sintering Methods 0.000 claims description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000005234 chemical deposition Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 4
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims description 4
- 229910017604 nitric acid Inorganic materials 0.000 claims description 3
- 239000002105 nanoparticle Substances 0.000 claims 1
- 239000002131 composite material Substances 0.000 abstract description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 238000005215 recombination Methods 0.000 description 6
- 230000006798 recombination Effects 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000003513 alkali Substances 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/228—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
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Abstract
The invention relates to a preparation method of a passivated contact cell with a selective emitter structure, which comprises the following steps: printing boron doping slurry on the front surface of the textured N-type silicon wafer, and drying at the temperature of 100-200 ℃ for 5-15min in the atmosphere of nitrogen and/or oxygen to solidify the boron doping slurry on the silicon wafer and remove organic components in the boron doping slurry; the printing area of the boron-doped slurry corresponds to the metalized area, and the width of the printing area of the boron-doped slurry is larger than that of the metalized area; carrying out high-temperature propulsion on the boron doped slurry printed on the front side of the silicon wafer in a furnace tube so as to prepare an emitter with a selective structure on the front side of the silicon wafer; introducing nitrogen-oxygen mixed gas into the furnace tube in the process of introducing the silicon wafer into the furnace tube, and controlling the operating temperature to be lower than 800 ℃ so as to remove organic components in the boron-doped slurry; and (5) post-processing the silicon wafer. The preparation method of the boron-doped selective emitter can obviously reduce the composite current on the surface of the emitter and improve the battery efficiency by more than 0.2 percent.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a preparation method of a passivated contact cell with a selective emitter structure.
Background
The n-type cell adopts n-type silicon as a substrate material, has good metal impurity pollution resistance, a minority carrier and a long diffusion length, has the advantages of no light attenuation, higher cell efficiency and the like compared with the traditional p-type cell, and is favored by the market at present. The n-type passivated contact battery is a novel n-type battery structure, and the tunneling passivation layer provides good surface passivation for an n + surface, so that metal contact recombination is greatly reduced, and the open-circuit voltage and the short-circuit current of the battery are improved. The cell efficiency of the structure is far higher than that of the traditional crystal silicon cell product, so that the photovoltaic power generation cost is more favorably reduced.
The existing n-type passivated contact battery structure solves the passivation of an n surface, but the recombination of the surface of an emitter is still higher, which becomes the bottleneck of improving the efficiency, and the two factors of passivation and contact resistance need to be considered for reducing the recombination of the surface of the emitter.
Compared with a phosphorus-doped emitter, because the activation difficulty of boron is much higher than that of phosphorus, the selective doping of boron is a world problem at present, and a mass-producible selective emitter preparation method with both efficiency and yield is not available, for example, the laser doping which is mature in the aspect of the phosphorus selective doping at present is not mature in the aspect of the boron doping.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a preparation method of a passivated contact battery with a selective emitter structure.
The invention discloses a preparation method of a passivated contact battery with a selective emitter structure, which adopts the technical scheme that: the method comprises the following steps:
(1) printing boron doped slurry on the front surface of the textured N-type silicon wafer, and drying for 5-15min at the temperature of 100-200 ℃ in the nitrogen and/or oxygen atmosphere; the printing area of the boron-doped slurry corresponds to the metalized area, and the width of the printing area of the boron-doped slurry is larger than that of the metalized area;
(2) carrying out high-temperature propulsion on the boron-doped slurry printed on the front side of the silicon wafer so as to prepare an emitter with a selective structure on the front side of the silicon wafer; introducing nitrogen-oxygen mixed gas into the furnace tube in the process of introducing the silicon wafer into the furnace tube, and controlling the operating temperature to be lower than 800 ℃ so as to remove organic components in the boron-doped slurry;
(3) and post-processing the silicon wafer.
The invention provides a preparation method of a passivated contact battery with a selective emitter structure, which also comprises the following subsidiary technical scheme:
in the step (2), the step of performing high-temperature propulsion on the boron-doped slurry printed on the front surface of the silicon wafer in the furnace tube to prepare the emitter with the selective structure on the front surface of the silicon wafer comprises the following steps:
(2.11) putting the silicon wafer into a diffusion furnace tube, and introducing nitrogen and oxygen to make the silicon wafer advance at high temperature in the atmosphere of nitrogen and oxygen to form a P + + region; the high-temperature propulsion temperature is 950-;
(2.12) putting the silicon wafer into a hydrofluoric acid solution for cleaning to remove the borosilicate glass layer in the P + + region;
(2.13) putting the silicon wafer into the diffusion furnace tube again, and introducing nitrogen, oxygen and boron tribromide to ensure that the silicon wafer is propelled at high temperature in the atmosphere of the nitrogen, the oxygen and the boron tribromide to form a P + region; the high-temperature propulsion temperature is 980-;
and (2.14) putting the silicon wafer into a hydrofluoric acid solution for cleaning to remove the borosilicate glass layer in the P + region.
Wherein, prior to step (2.12), the method further comprises:
and (3) marking a laser mark on the silicon chip, wherein the laser mark is used as a reference point of a printing area of the metallization paste in a subsequent step.
In the step (2), the step of performing high-temperature propulsion on the boron-doped slurry printed on the front surface of the silicon wafer in the furnace tube to prepare the emitter with the selective structure on the front surface of the silicon wafer comprises the following steps:
(2.21) putting the silicon wafer into a diffusion furnace tube, and introducing nitrogen, oxygen and boron tribromide, so that the silicon wafer is propelled at high temperature in the atmosphere of the nitrogen, the oxygen and the boron tribromide, and a P + area and a P + + area are formed at the same time; the high-temperature propulsion temperature is 980-;
and (2.22) putting the silicon wafer into a hydrofluoric acid solution for cleaning to remove the borosilicate glass layer in the P + region and the borosilicate glass layer in the P + + region.
Wherein, prior to step (2.22), the method further comprises:
and (3) marking a laser mark on the silicon chip, wherein the laser mark is used as a reference point of a printing area of the metallization paste in a subsequent step.
Wherein the sheet resistance of the P + region is 90-200 omega/sq, and the surface peak concentration is 5E18-1.5E19cm-3The depth of the junction is 0.5-1 um; the sheet resistance of the P + + region is 30-70 omega/sq, and the surface peak concentration is 1E19-3E19cm-3The depth of the junction is 0.8-1.5 um.
Wherein the sheet resistance of the P + region is 90-200 omega/sq, and the surface peak concentration is 5E18-1.5E19cm-3The depth of the junction is 0.5-1 um; the sheet resistance of the P + + region is 30-70 omega/sq, and the surface peak concentration is 1E19-3E19cm-3The depth of the junction is 0.7-1 um.
Wherein, in the step (1), the printing width of the printing area of the boron-doped slurry is 40-200 um.
Wherein, in the step (3), the post-processing of the silicon wafer comprises:
(3.1) preparing a tunneling oxide layer on the back surface of the silicon wafer, and preparing a phosphorus-doped polycrystalline silicon layer on the tunneling oxide layer;
(3.2) preparing a silicon nitride antireflection layer on the phosphorus-doped polycrystalline silicon layer on the back surface of the silicon wafer;
(3.3) preparing an aluminum oxide passivation layer on the front surface of the silicon wafer;
(3.4) preparing a silicon nitride antireflection layer on the aluminum oxide passivation layer on the front surface of the silicon wafer;
and (3.5) printing the metallization slurry on the front surface and the back surface of the silicon wafer, and sintering.
In the step (3.1), the preparing a tunneling oxide layer on the back surface of the silicon wafer, and the preparing a phosphorus-doped polysilicon layer on the tunneling oxide layer includes:
(3.11) by thermal oxidation, HNO3Oxidation, O3Preparing a tunneling oxide layer by an oxidation or atomic layer deposition method; the thickness of the tunneling oxide layer is 0.5-3 nm, and the manufacturing material is silicon dioxide;
(3.12) preparing a polycrystalline silicon layer by adopting a low-pressure chemical deposition method; the deposition temperature is 550-650 ℃, and the thickness of the polycrystalline silicon layer is 50-400 nm;
(3.13) doping the polycrystalline silicon layer by adopting an ion implantation method, and annealing to form a phosphorus-doped polycrystalline silicon layer; the doping source is phosphine or red phosphorus, and the doping amount is 2e15-8e15cm-2(ii) a The annealing temperature is 750-900 ℃, the annealing time is 20-80min, and the doping sheet resistance is 20-100 omega/sq.
The implementation of the invention comprises the following technical effects:
according to the invention, the boron-doped slurry is printed in the metalized area, and the emitter with the selective structure is prepared after the boron-doped slurry is dried, so that the novel preparation method of the boron-doped selective emitter is simple and effective, has low cost, is compatible with the existing equipment and process, and is suitable for mass production; in addition, the preparation method can obviously reduce the composite current on the surface of the emitter and improve the efficiency of the n-type passivated contact battery by more than 0.2 percent.
Drawings
Fig. 1 is a schematic cross-sectional view of a cell structure after step (1) of a method for manufacturing a laser-doped passivated contact cell with a selective emitter structure according to an embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a cell structure after step (2.11) of a method for manufacturing a laser-doped passivated contact cell with a selective emitter structure according to an embodiment of the invention.
Fig. 3 is a schematic cross-sectional view of a cell structure after step (2.12) of a method for manufacturing a laser-doped passivated contact cell with a selective emitter structure according to an embodiment of the invention.
Fig. 4 is a schematic cross-sectional view of a cell structure after step (2.13) and step (2.21) of a method for manufacturing a laser-doped passivated contact cell with a selective emitter structure according to an embodiment of the invention.
Fig. 5 is a schematic cross-sectional view of a cell structure after step (3.13) of a method for manufacturing a laser-doped passivated contact cell with a selective emitter structure according to an embodiment of the invention.
Fig. 6 is a schematic cross-sectional view of a cell structure after step (3.2) of a method for manufacturing a laser-doped passivated contact cell with a selective emitter structure according to an embodiment of the invention.
Fig. 7 is a schematic cross-sectional view of a cell structure after step (3.3) of a method for manufacturing a laser-doped passivated contact cell with a selective emitter structure according to an embodiment of the invention.
Fig. 8 is a schematic cross-sectional view of a cell structure after step (3.4) of a method for manufacturing a laser-doped passivated contact cell with a selective emitter structure according to an embodiment of the invention.
Fig. 9 is a schematic cross-sectional view of a cell structure after step (3.5) of a method for manufacturing a laser-doped passivated contact cell with a selective emitter structure according to an embodiment of the invention.
In the figure, 1-N type silicon chip, 2-boron doped slurry, 3-P + + region, 4-borosilicate glass layer, 5-P + region, 6-tunneling oxide layer, 7-phosphorus doped polysilicon layer, 8-silicon nitride antireflection layer, 9-aluminum oxide passivation layer, 10-silicon nitride antireflection layer and 11-metallization slurry.
Detailed Description
The present invention will be described in detail with reference to examples.
The present invention is not limited to the above-described embodiments, and those skilled in the art can make modifications to the embodiments without any inventive contribution as required after reading the present specification, but only protected within the scope of the appended claims.
The invention discloses a preparation method of a passivated contact battery with a selective emitter structure, which comprises the following steps:
(1) printing boron doping slurry on the front surface of the textured N-type silicon wafer, and drying at the temperature of 100-200 ℃ for 5-15min in the atmosphere of nitrogen and/or oxygen to solidify the boron doping slurry on the silicon wafer and remove organic components in the boron doping slurry; the printing area of the boron-doped slurry corresponds to the metalized area, and the width of the printing area of the boron-doped slurry is larger than that of the metalized area;
in this step, the effective component in the boron-doped slurry is a compound containing a boron element. The invention takes the equipment precision and the process error into consideration, so the width of the printing area of the boron-doped slurry is larger than that of the metalized area, and the product failure caused by the fact that the metalized area exceeds the printing area of the boron-doped slurry is prevented.
(2) Carrying out high-temperature propulsion on the boron doped slurry printed on the front side of the silicon wafer in a furnace tube so as to prepare an emitter with a selective structure on the front side of the silicon wafer; introducing nitrogen-oxygen mixed gas into the furnace tube in the process of introducing the silicon wafer into the furnace tube, and controlling the operating temperature to be lower than 800 ℃ so as to remove organic components in the boron-doped slurry;
(3) and post-processing the silicon wafer.
In one embodiment, in the step (2), the performing high-temperature propelling on the boron-doped slurry printed on the front surface of the silicon wafer in the furnace tube to prepare the emitter with the selective structure on the front surface of the silicon wafer comprises:
(2.11) putting the silicon wafer into a diffusion furnace tube, and introducing nitrogen and oxygen to make the silicon wafer advance at high temperature in the atmosphere of nitrogen and oxygen to form a P + + region; the high-temperature propulsion temperature is 950-;
(2.12) putting the silicon wafer into a hydrofluoric acid solution for cleaning to remove the borosilicate glass layer in the P + + region;
(2.13) putting the silicon wafer into the diffusion furnace tube again, and introducing nitrogen, oxygen and boron tribromide to ensure that the silicon wafer is propelled at high temperature in the atmosphere of the nitrogen, the oxygen and the boron tribromide to form a P + region; the high-temperature propulsion temperature is 980-;
and (2.14) putting the silicon wafer into a hydrofluoric acid solution for cleaning to remove the borosilicate glass layer in the P + region.
In this embodiment, a P + + region and a P + region are respectively prepared on the front surface of the silicon wafer by means of step-by-step diffusion, so that the P + + region and the P + region can be respectively adjusted and optimized, and thus the P + + region can realize higher surface concentration and larger junction depth, thereby reducing contact resistance and contact recombination; the P + region can realize lower surface concentration and shallower junction depth, thereby reducing surface recombination and improving short-wave response; moreover, experiments show that the junction depth of the P + + region formed by adopting a step-by-step diffusion mode is deeper, and contact recombination can be effectively reduced.
In one embodiment, prior to step (2.12), the method further comprises:
and (3) marking a laser mark on the silicon chip, wherein the laser mark is used as a reference point of a printing area of the metallization paste in a subsequent step.
In this embodiment, since the P + + region formed by the paste printing diffusion may not be identified by naked eyes after cleaning, which may affect the alignment accuracy of subsequent metal printing, in this embodiment, after the P + + region of the silicon wafer is diffused and before cleaning, a laser mark is marked on the silicon wafer, and the laser mark is used as a reference point of the metalized paste printing region in the subsequent step, so that the alignment accuracy may be improved.
In one embodiment, in the step (2), the performing high-temperature propelling on the boron-doped slurry printed on the front surface of the silicon wafer in the furnace tube to prepare the emitter with the selective structure on the front surface of the silicon wafer comprises:
(2.21) putting the silicon wafer into a diffusion furnace tube, and introducing nitrogen, oxygen and boron tribromide, so that the silicon wafer is propelled at high temperature in the atmosphere of the nitrogen, the oxygen and the boron tribromide, and a P + area and a P + + area are formed at the same time; the high-temperature propulsion temperature is 980-;
and (2.22) putting the silicon wafer into a hydrofluoric acid solution for cleaning, wherein the borosilicate glass layer in the P + region and the borosilicate glass layer in the P + + region are formed on the silicon wafer.
In this embodiment, the P + + region and the P + region are simultaneously prepared on the front surface of the silicon wafer by a one-step diffusion method, so as to reduce the process flow and the cost, and experiments show that the P + + region formed by the one-step diffusion method can maintain a higher surface concentration, thereby reducing the contact resistance.
In one embodiment, prior to step (2.22), the method further comprises:
and (3) marking a laser mark on the silicon chip, wherein the laser mark is used as a reference point of a printing area of the metallization paste in a subsequent step.
In this embodiment, since the P + + region formed by the paste printing diffusion may not be identified by naked eyes after cleaning, which may affect the alignment accuracy of subsequent metal printing, in this embodiment, after the P + + region of the silicon wafer is diffused and before cleaning, a laser mark is marked on the silicon wafer, and the laser mark is used as a reference point of the metalized paste printing region in the subsequent step, so that the alignment accuracy may be improved.
In one embodiment, the sheet resistance of the P + region is 90-200 Ω/sq, and the surface peak concentration is 5E18-1.5E19cm-3The depth of the junction is 0.5-1 um; the sheet resistance of the P + + region is 30-70 omega/sq, and the surface peak concentration is 1E19-3E19cm-3The depth of the junction is 0.8-1.5 um.
In one embodiment, the sheet resistance of the P + region is 90-200 Ω/sq, and the surface peak concentration is 5E18-1.5E19cm-3The depth of the junction is 0.5-1 um; the sheet resistance of the P + + region is 30-70 omega/sq, and the surface peak concentration is 1E19-3E19cm-3The depth of the junction is 0.7-1 um.
In one embodiment, in step (1), the printing width of the printing region of the boron-doped paste is 40-200 um.
In one embodiment, in step (3), the post-processing of the silicon wafer comprises:
(3.1) preparing a tunneling oxide layer on the back surface of the silicon wafer, and preparing a phosphorus-doped polycrystalline silicon layer on the tunneling oxide layer;
(3.2) preparing a silicon nitride antireflection layer on the phosphorus-doped polycrystalline silicon layer on the back surface of the silicon wafer;
(3.3) preparing an aluminum oxide passivation layer on the front surface of the silicon wafer;
(3.4) preparing a silicon nitride antireflection layer on the aluminum oxide passivation layer on the front surface of the silicon wafer;
and (3.5) printing the metallization slurry on the front surface and the back surface of the silicon wafer, and sintering.
In one embodiment, in step (3.1), the preparing a tunnel oxide layer on the back surface of the silicon wafer and preparing a phosphorus-doped polysilicon layer on the tunnel oxide layer includes:
(3.11) by thermal oxidation, HNO3Oxidation, O3Preparing a tunneling oxide layer by an oxidation or atomic layer deposition method; the thickness of the tunneling oxide layer is 0.5-3 nm, and the manufacturing material is silicon dioxide;
(3.12) preparing a polycrystalline silicon layer by adopting a low-pressure chemical deposition method; the deposition temperature is 550-650 ℃, and the thickness of the polycrystalline silicon layer is 50-400 nm;
(3.13) doping the polycrystalline silicon layer by adopting an ion implantation method, and annealing to form a phosphorus-doped polycrystalline silicon layer; the doping source is phosphine or red phosphorus, and the doping amount is 2e15-8e15cm-2(ii) a The annealing temperature is 750-900 ℃, the annealing time is 20-80min, and the doping sheet resistance is 20-100 omega/sq.
In one embodiment, silicon nitride is prepared on the back surface of the silicon wafer by adopting a plasma enhanced chemical vapor deposition mode, and the thickness of the silicon nitride is 50-150 nm; and preparing an aluminum oxide passivation layer on the front surface of the silicon wafer by adopting modes of ALD or PECVD and the like, wherein the thickness of the aluminum oxide passivation layer is 1-10 nm.
It should be noted that, in the present invention, the P + + region is a P heavily doped region, and the P + region is a P lightly doped region.
The production process of the invention will be described in detail below with specific examples.
Example 1
(1) Printing boron doping slurry 2 on the front surface of an N-type silicon wafer 1 subjected to alkali texturing by adopting a screen printing mode, and drying at 130 ℃ for 10min in a nitrogen atmosphere to solidify the boron doping slurry on the silicon wafer and remove organic components in the boron doping slurry; the printing area of the boron-doped slurry corresponds to the metalized area, and the width of the printing area of the boron-doped slurry 2 is 120 um; wherein the silicon wafer has a resistivity of 1 Ω · cm and a thickness of 160 μm. The cell structure after this step is completed is shown in fig. 1.
(2.11) putting the silicon wafer into a diffusion furnace tube, and introducing nitrogen and oxygen to make the silicon wafer advance at high temperature in the atmosphere of nitrogen and oxygen to form a P + + region 3; the high-temperature propelling temperature is 985 ℃, the time is 65min, and after the high-temperature propelling is finished, the silicon wafer is taken out of the diffusion furnace tube; introducing nitrogen-oxygen mixed gas into the furnace tube in the process of introducing the silicon wafer into the furnace tube, and controlling the operating temperature to be 750 ℃ so as to remove organic components in the boron-doped slurry; the cell structure after this step is completed is shown in fig. 2.
(2.12) putting the silicon wafer into a hydrofluoric acid solution for cleaning to remove the borosilicate glass layer 4 in the P + + region 3; the cell structure after this step is completed is shown in fig. 3.
(2.13) putting the silicon wafer into the diffusion furnace tube again, and introducing nitrogen, oxygen and boron tribromide to ensure that the silicon wafer is propelled at high temperature in the atmosphere of the nitrogen, the oxygen and the boron tribromide to form a P + region 5; the high-temperature propelling temperature is 1000 ℃, the time is 120min, and after the high-temperature propelling is finished, the silicon wafer is taken out of the diffusion furnace tube; the cell structure after this step is completed is shown in fig. 4.
After the step is finished, the sheet resistance of the P + region 5 is 140 omega/sq, and the surface peak concentration is 8E18-cm-3The junction depth is 0.8 um; the sheet resistance of the P + + region 3 is 55 omega/sq, and the surface peak concentration is 1.1E19cm-3The junction depth is 1.3 um.
And (2.14) putting the silicon wafer into a hydrofluoric acid solution for cleaning to remove the borosilicate glass layer in the P + area 5. (3.11) preparing a tunneling oxide layer 6 on the back surface of the silicon wafer by adopting a thermal oxidation method; the thickness of the tunneling oxide layer is 0.5-3 nm, and the manufacturing material is silicon dioxide;
(3.12) preparing a polycrystalline silicon layer by adopting a low-pressure chemical deposition method; the deposition temperature is 600 ℃, and the thickness of the polycrystalline silicon layer is 150 nm;
(3.13) by ion implantationDoping the polysilicon layer, and annealing to form a phosphorus-doped polysilicon layer 7; the doping source is phosphine, and the doping amount is 3e15cm-2(ii) a The annealing temperature is 850 ℃, the annealing time is 80min, and the doping sheet resistance is 50 omega/sq. The cell structure after this step is completed is shown in fig. 5.
And (3.2) preparing a silicon nitride antireflection layer 8 on the back of the silicon wafer by adopting a plasma enhanced chemical vapor deposition mode, wherein the thickness of the silicon nitride antireflection layer 8 is 80 nm. The cell structure after this step is completed is shown in fig. 6.
And (3.3) preparing an aluminum oxide passivation layer 9 on the front surface of the silicon wafer by adopting an ALD mode, wherein the thickness of the aluminum oxide passivation layer 9 is 2 nm. The cell structure after this step is completed is shown in fig. 7.
(3.4) preparing a silicon nitride antireflection layer 10 on an aluminum oxide passivation layer on the front surface of the silicon wafer by adopting a plasma enhanced chemical vapor deposition mode; the cell structure after this step is completed is shown in fig. 8.
(3.5) printing metallization paste 11 on the front side and the back side of the silicon wafer in a screen printing mode, and sintering, wherein the width of a grid line is 40 microns, and the sintering peak temperature is 700 ℃; the cell structure after this step is completed is shown in fig. 9.
Example 2
(1) Printing boron doping slurry 2 on the front surface of an N-type silicon wafer 1 subjected to alkali texturing by adopting a screen printing mode, drying for 10min at the temperature of 130 ℃ in the atmosphere of nitrogen and oxygen to solidify the boron doping slurry on the silicon wafer and remove organic components in the boron doping slurry; the printing area of the boron-doped slurry corresponds to the metalized area, and the width of the printing area of the boron-doped slurry 2 is 120 um; wherein the silicon wafer has a resistivity of 1 Ω · cm and a thickness of 160 μm. The cell structure after this step is completed is shown in fig. 1.
(2.21) putting the silicon wafer into a diffusion furnace tube, and introducing nitrogen, oxygen and boron tribromide, so that the silicon wafer is propelled at high temperature in the atmosphere of the nitrogen, the oxygen and the boron tribromide, and a P + area 5 and a P + + area 3 are formed at the same time; the high-temperature propelling temperature is 1000 ℃, the time is 120min, and after the high-temperature propelling is finished, the silicon wafer is taken out of the diffusion furnace tube; introducing nitrogen-oxygen mixed gas into the furnace tube in the process of introducing the silicon wafer into the furnace tube, and controlling the operating temperature to be 750 ℃ so as to remove organic components in the boron-doped slurry; the cell structure after this step is completed is shown in fig. 4.
And (2.22) putting the silicon wafer into a hydrofluoric acid solution for cleaning to remove the borosilicate glass layer 4 in the P + + region 3.
After the step is finished, the sheet resistance of the P + region 5 is 140 omega/sq, and the surface peak concentration is 8E18-cm-3The junction depth is 0.8 um; the sheet resistance of the P + + region 3 is 65 omega/sq, and the surface peak concentration is 1.1E19cm-3The junction depth is 0.8 um.
(3.11) preparing a tunneling oxide layer 6 on the back surface of the silicon wafer by adopting a thermal oxidation method; the thickness of the tunneling oxide layer is 1nm, and the manufacturing material is silicon dioxide;
(3.12) preparing a polycrystalline silicon layer by adopting a low-pressure chemical deposition method; the deposition temperature is 600 ℃, and the thickness of the polycrystalline silicon layer is 150 nm;
(3.13) doping the polycrystalline silicon layer by adopting an ion implantation method, and annealing to form a phosphorus-doped polycrystalline silicon layer 7; the doping source is red phosphorus, and the doping amount is 3e15cm-2(ii) a The annealing temperature is 850 ℃, the annealing time is 80min, and the doping sheet resistance is 50 omega/sq. The cell structure after this step is completed is shown in fig. 5.
And (3.2) preparing a silicon nitride antireflection layer 8 on the back of the silicon wafer by adopting a plasma enhanced chemical vapor deposition mode, wherein the thickness of the silicon nitride antireflection layer 8 is 80 nm. The cell structure after this step is completed is shown in fig. 6.
And (3.3) preparing an aluminum oxide passivation layer 9 on the front surface of the silicon wafer by adopting an ALD mode, wherein the thickness of the aluminum oxide passivation layer 9 is 2 nm. The cell structure after this step is completed is shown in fig. 7.
And (3.4) preparing a silicon nitride antireflection layer 10 on the aluminum oxide passivation layer on the front surface of the silicon wafer by adopting a plasma enhanced chemical vapor deposition mode, wherein the thickness of the silicon nitride antireflection layer 10 is 80 nm. The cell structure after this step is completed is shown in fig. 8.
(3.5) printing metallization paste 11 on the front side and the back side of the silicon wafer in a screen printing mode, and sintering, wherein the width of a grid line is 40 microns, and the sintering peak temperature is 700 ℃; the cell structure after this step is completed is shown in fig. 9.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the protection scope of the present invention, although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.
Claims (10)
1. A method for preparing a passivated contact cell with a selective emitter structure is characterized in that: the method comprises the following steps:
(1) printing boron doped slurry on the front surface of the textured N-type silicon wafer, and drying for 5-15min at the temperature of 100-200 ℃ in the nitrogen and/or oxygen atmosphere; the printing area of the boron-doped slurry corresponds to the metalized area, and the width of the printing area of the boron-doped slurry is larger than that of the metalized area;
(2) carrying out high-temperature propulsion on the boron-doped slurry printed on the front side of the silicon wafer so as to prepare an emitter with a selective structure on the front side of the silicon wafer; introducing nitrogen-oxygen mixed gas in the process of introducing the silicon wafer into the furnace tube, and controlling the operating temperature to be lower than 800 ℃ so as to remove organic components in the boron-doped slurry;
(3) and post-processing the silicon wafer.
2. The preparation method of claim 1, wherein in the step (2), the step of performing high-temperature propelling on the boron doped slurry printed on the front surface of the silicon wafer in the furnace tube to prepare the emitter with the selective structure on the front surface of the silicon wafer comprises the following steps:
(2.11) putting the silicon wafer into a diffusion furnace tube, and introducing nitrogen and oxygen to make the silicon wafer advance at high temperature in the atmosphere of nitrogen and oxygen to form a P + + region; the high-temperature propulsion temperature is 950-;
(2.12) putting the silicon wafer into a hydrofluoric acid solution for cleaning to remove the borosilicate glass layer in the P + + region;
(2.13) putting the silicon wafer into the diffusion furnace tube again, and introducing nitrogen, oxygen and boron tribromide to ensure that the silicon wafer is propelled at high temperature in the atmosphere of the nitrogen, the oxygen and the boron tribromide to form a P + region; the high-temperature propulsion temperature is 980-;
and (2.14) putting the silicon wafer into a hydrofluoric acid solution for cleaning to remove the borosilicate glass layer in the P + region.
3. The method of claim 2, wherein prior to step (2.12), the method further comprises:
and (3) marking a laser mark on the silicon chip, wherein the laser mark is used as a reference point of a printing area of the metallization paste in a subsequent step.
4. The preparation method of claim 1, wherein in the step (2), the step of performing high-temperature driving on the boron-doped slurry printed on the front surface of the silicon wafer to prepare the emitter with the selective structure on the front surface of the silicon wafer comprises the following steps:
(2.21) putting the silicon wafer into a diffusion furnace tube, and introducing nitrogen, oxygen and boron tribromide, so that the silicon wafer is propelled at high temperature in the atmosphere of the nitrogen, the oxygen and the boron tribromide, and a P + area and a P + + area are formed at the same time; the high-temperature propulsion temperature is 980-;
and (2.22) putting the silicon wafer into a hydrofluoric acid solution for cleaning, wherein the borosilicate glass layer in the P + region and the borosilicate glass layer in the P + + region are formed on the silicon wafer.
5. The method of claim 4, wherein prior to step (2.22), the method further comprises:
and (3) marking a laser mark on the silicon chip, wherein the laser mark is used as a reference point of a printing area of the metallization paste in a subsequent step.
6. The method of claim 2 or 3, wherein the P + regionThe sheet resistance of the nano-particles is 90-200 omega/sq, and the surface peak concentration is 5E18-1.5E19cm-3The depth of the junction is 0.5-1 um; the sheet resistance of the P + + region is 30-70 omega/sq, and the surface peak concentration is 1E19-3E19cm-3The depth of the junction is 0.8-1.5 um.
7. The method according to claim 4 or 5, wherein the sheet resistance of the P + region is 90 to 200. omega./sq, and the surface peak concentration is 5E18 to 1.5E19cm-3The depth of the junction is 0.5-1 um; the sheet resistance of the P + + region is 30-70 omega/sq, and the surface peak concentration is 1E19-3E19cm-3The depth of the junction is 0.7-1 um.
8. The production method according to any one of claims 1 to 5, wherein in the step (1), the printing width of the printing region of the boron-doped paste is 40 to 200 um.
9. The production method according to any one of claims 1 to 5, wherein in the step (3), the post-treatment of the silicon wafer comprises:
(3.1) preparing a tunneling oxide layer on the back surface of the silicon wafer, and preparing a phosphorus-doped polycrystalline silicon layer on the tunneling oxide layer;
(3.2) preparing a silicon nitride antireflection layer on the phosphorus-doped polycrystalline silicon layer on the back surface of the silicon wafer;
(3.3) preparing an aluminum oxide passivation layer on the front surface of the silicon wafer;
(3.4) preparing a silicon nitride antireflection layer on the aluminum oxide passivation layer on the front surface of the silicon wafer;
and (3.5) printing the metallization slurry on the front surface and the back surface of the silicon wafer, and sintering.
10. The method of claim 9, wherein in step (3.1), the step of preparing a tunnel oxide layer on the back surface of the silicon wafer and preparing a phosphorus-doped polysilicon layer on the tunnel oxide layer comprises:
(3.11) by thermal oxidation, HNO3Oxidation, O3Preparing a tunneling oxide layer by an oxidation or atomic layer deposition method; the thickness of the tunneling oxide layer is 0.5-3 nm, and the manufacturing material is silicon dioxide;
(3.12) preparing a polycrystalline silicon layer by adopting a low-pressure chemical deposition method; the deposition temperature is 550-650 ℃, and the thickness of the polycrystalline silicon layer is 50-400 nm;
(3.13) doping the polycrystalline silicon layer by adopting an ion implantation method, and annealing to form a phosphorus-doped polycrystalline silicon layer; the doping source is phosphine or red phosphorus, and the doping amount is 2e15-8e15cm-2(ii) a The annealing temperature is 750-900 ℃, the annealing time is 20-80min, and the doping sheet resistance is 20-100 omega/sq.
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