CN111933692B - Wafer back sealing structure and manufacturing method thereof - Google Patents

Wafer back sealing structure and manufacturing method thereof Download PDF

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Publication number
CN111933692B
CN111933692B CN202011084965.5A CN202011084965A CN111933692B CN 111933692 B CN111933692 B CN 111933692B CN 202011084965 A CN202011084965 A CN 202011084965A CN 111933692 B CN111933692 B CN 111933692B
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layer
oxide layer
substrate
epitaxial
cavity
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CN111933692A (en
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朱红波
金起準
吴佳特
王厚有
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Jingxincheng Beijing Technology Co Ltd
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Jingxincheng Beijing Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides

Abstract

The invention provides a wafer back seal structure and a manufacturing method thereof, comprising the following steps: providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged; forming an epitaxial layer on the first surface; forming a laminated structure on the epitaxial layer and the second surface; the laminated structure comprises a first oxide layer, a polycrystalline silicon layer and a second oxide layer; removing the second oxide layer on the epitaxial layer by dry etching to expose the polysilicon layer on the first surface; removing the polysilicon layer on the epitaxial layer by wet etching to expose the first oxide layer on the first surface; and removing the first oxide layer on the epitaxial layer and the second oxide layer on the second surface by wet etching. The manufacturing method of the wafer back sealing structure provided by the invention has a simple process.

Description

Wafer back sealing structure and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductors, in particular to a wafer back sealing structure and a manufacturing method thereof.
Background
At present, an epitaxially deposited silicon wafer such as an image sensor and a power device is a heavily doped substrate, and in order to prevent dopant escape and high-temperature autodoping, a back sealing material is deposited on the back surface of the wafer, and then the surface polishing and epitaxial layer (EPI) are performed on the silicon substrate. However, before the subsequent process, polishing and cleaning are required to be performed on the silicon substrate on which the back sealing material film and the epitaxial layer grow or reworking and cleaning of the cushion layer silicon dioxide and silicon nitride are required to be performed on the active region, the back sealing material film is damaged due to the high corrosion rate of the back sealing low-temperature oxide layer, and meanwhile, in the subsequent process, the back sealing material film may be completely removed, so that the heavy doping ions of the substrate are separated out, and cross contamination is caused; meanwhile, the performance of subsequent tests is influenced, and the difference of the back seal possibly influences the furnace tube load effect and the back temperature detection of the thermal annealing process.
Disclosure of Invention
In view of the above-mentioned defects of the prior art, the present invention provides a method for manufacturing a wafer back seal structure to reduce the damage to the oxide layer, prevent the doped ions from being precipitated, and reduce the influence on the subsequent test.
To achieve the above and other objects, the present invention provides a method for manufacturing a wafer backside seal structure, comprising:
providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged;
forming an epitaxial layer on the first surface;
forming a laminated structure on the epitaxial layer and the second surface; the laminated structure comprises a first oxide layer, a polycrystalline silicon layer and a second oxide layer;
removing the second oxide layer on the epitaxial layer by dry etching to expose the polysilicon layer on the first surface;
removing the polysilicon layer on the epitaxial layer by wet etching to expose the first oxide layer on the first surface;
and removing the first oxide layer on the epitaxial layer and the second oxide layer on the second surface by wet etching to expose the epitaxial layer and the polysilicon layer on the second surface.
Further, the step of forming the first oxide layer includes:
placing the substrate in a first cavity;
and introducing a silicon-containing precursor into the first cavity, and raising the temperature in the first cavity to 550-620 ℃.
Further, the step of forming the polysilicon layer includes:
placing the substrate in a second cavity;
introducing silane into the second cavity, and raising the temperature in the second cavity to 590-670 ℃.
Further, the step of forming the second oxide layer includes:
placing the substrate within a third chamber;
and introducing a silicon-containing precursor into the third cavity, and raising the temperature in the third cavity to 570-650 ℃.
Further, soaking the substrate by using an alkaline solution to remove the polycrystalline silicon layer; wherein the volume ratio of ammonia water, hydrogen peroxide and deionized water in the alkaline solution is 5:2: 500.
Further, the second oxide layer on the second surface is etched while the polysilicon layer is removed, and the etching rate of the polysilicon layer is greater than that of the second oxide layer.
Further, the first oxide layer on the epitaxial layer and the second oxide layer on the second surface are etched by using a dilute hydrofluoric acid solution, wherein the volume ratio of hydrofluoric acid to deionized water in the dilute hydrofluoric acid solution is 1:200-1: 500.
Further, the thickness of the first oxide layer and the second oxide layer is 800-1000 angstroms, and the thickness of the polysilicon layer is 600-1000 angstroms.
Further, the substrate is in a rotated state when the laminated structure is formed.
Further, the present invention provides a wafer back sealing structure, including:
a substrate comprising a first surface and a second surface disposed opposite;
an epitaxial layer on the first surface;
a first oxide layer on the second surface of the substrate;
and the polycrystalline silicon layer is positioned on the first oxidation layer.
In summary, the present invention provides a wafer back seal structure and a method for manufacturing the same, wherein an epitaxial layer is formed on a substrate, and a doping concentration of the substrate is greater than a doping concentration of the epitaxial layer; the epitaxial layer is positioned on the first surface of the substrate, and then a laminated structure is formed on the epitaxial layer and the second surface of the substrate, wherein the laminated structure comprises a first oxide layer, a polycrystalline silicon layer and a second oxide layer; and then, the first oxide layer and the polycrystalline silicon layer positioned on the second surface of the substrate are reserved through an etching process, the polycrystalline silicon layer can protect the first oxide layer and prevent the influence of the subsequent process on the first oxide layer, and the second surface of the substrate is provided with the first oxide layer and the polycrystalline silicon layer, so that the separation of doped ions in the substrate can be avoided. Meanwhile, when the substrate is annealed, because the polycrystalline silicon layer is exposed on the surface and is close to the material structure of the substrate, the temperature close to the substrate can be obtained by measuring the temperature of the polycrystalline silicon layer, so that the temperature of the substrate is easier to monitor, and the temperature of an annealing chamber is convenient to control; the invention adopts alkaline solution with high selection ratio to etch the polysilicon, adopts acid solution to etch the oxide layer, uses acid and alkali wet etching in combination, and is processed by the alkaline solution tank and the acid solution tank at one time, thus having low cost.
Drawings
FIG. 1: the method for manufacturing a wafer backside seal structure according to the present embodiment is a flowchart.
FIG. 2: step S1 is shown in the corresponding schematic diagram.
FIG. 3: step S2 is shown in the corresponding schematic diagram.
FIG. 4: the position of the first oxide layer is schematically shown.
FIG. 5: the position of the polysilicon layer is shown schematically.
FIG. 6: schematic position of the laminated structure.
FIG. 7: step S4 is shown in the corresponding schematic diagram.
FIG. 8: step S5 is shown in the corresponding schematic diagram.
FIG. 9: step S6 is shown in the corresponding schematic diagram.
Description of the symbols
101: substrate, 101 a: first surface, 101 b: second surface, 102: epitaxial layer, 103: first oxide layer, 104: polysilicon layer, 105: second oxide layer, 106: a laminated structure.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, the present embodiment provides a method for manufacturing a wafer backside seal structure, including:
s1: providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged;
s2: forming an epitaxial layer on the first surface;
s3: forming a laminated structure on the epitaxial layer and the second surface; the laminated structure comprises a first oxide layer, a polycrystalline silicon layer and a second oxide layer;
s4: removing the second oxide layer on the epitaxial layer by dry etching to expose the polysilicon layer on the first surface;
s5: removing the polysilicon layer on the epitaxial layer by wet etching to expose the first oxide layer on the first surface;
s6: and removing the first oxide layer on the epitaxial layer and the second oxide layer on the second surface by wet etching to expose the epitaxial layer and the polysilicon layer on the second surface.
As shown in fig. 2, in step S1, a substrate 101 is first provided, where the substrate 101 has a first surface 101a and a second surface 101b disposed oppositely. The present embodiment defines the upper surface of the substrate 101 as a first surface 101a, and the lower surface of the substrate 101 as a second surface 101 b. In this embodiment, the material of the substrate 101 may be a semiconductor material, and the semiconductor material may be silicon (Si), germanium (Ge)Or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other semiconductor materials such as iii-v compounds such as gallium arsenide. The substrate 101 may be a heavily doped substrate, an N-type substrate doped with Sb, As, P, N, or the like, or a P-type substrate doped with Ga, In, B, or the like, and may have a doping concentration of, for example, 1 × 1017To 1X 1020cm-3. The crystal plane of the substrate 101 may be (100), but for some high speed and high voltage devices a different crystal plane such as (111) may be used to enhance carrier mobility, or a (110) crystal plane may be used as needed to control the epitaxial growth rate.
As shown in fig. 3, in step S2, the substrate 101 is placed in an epitaxial furnace, heated to a predetermined temperature, and then a reaction gas carried by, for example, an inert gas is introduced to form an epitaxial layer 102 on the first surface of the substrate 101. The epitaxial layer 102 may be a homoepitaxial layer of the same material as the substrate 101, or may be a heteroepitaxial layer of a different material from the substrate 101. In the present embodiment, the epitaxial furnace may be a (liquid phase epitaxial) barrel furnace, a flat plate epitaxial furnace, or a monolithic epitaxial furnace. The epitaxial temperature is set appropriately according to the growth rate and epitaxial layer quality control requirements, for example, 700-1300 ℃. The epitaxial layer 102 is formed to have a first thickness that is greater than the thickness of the epitaxial layer that is ultimately required to form the high voltage device, i.e., greater than a minimum thickness to avoid device breakdown. In some embodiments, the furnace may also be charged with, for example, B2H6、PH3、AsH3And so on, such that epitaxial layer 102 is of the same doping type as substrate 101 to reduce on-resistance and prevent parasitic diode formation at the interface. In some embodiments, before the epitaxial layer 102 is formed, a buffer layer may be deposited on the substrate 101, wherein the buffer layer is made of a material different according to the lattice constant matching requirement between the epitaxial layer 102 and the substrate 101, such as Si, Ge, GaN, etc., and is deposited by a chemical vapor deposition method, for example, and has a thickness of about 8-13 μm. In this embodiment, the epitaxial layer 102 may further be doped with ions, and the doping concentration of the doped ions in the epitaxial layer 102 may be smallThe doping concentration of the dopant ions in the substrate 101.
As shown in fig. 4, in step S3, the substrate 101 forming the epitaxial layer 102 is first disposed in the first cavity to form the first oxide layer 103 on the epitaxial layer 102, and simultaneously the first oxide layer 103 is formed on the second surface of the substrate 101. In this embodiment, the step of forming the first oxide layer 103 may include introducing a silicon-containing precursor, which may be Tetraethylorthosilicate (TEOS), into the first chamber, and heating the first chamber. In this embodiment, the temperature in the first cavity may be 550-620 ℃, for example 600 ℃. In this embodiment, when the temperature in the first chamber reaches 550-620 ℃, Tetraethylorthosilicate (TEOS) forms a first oxide layer 103 on the epitaxial layer 102 and on the second surface of the substrate 101. The thickness of the first oxide layer 103 may be 800-1000 angstroms, such as 800 angstroms, 900 angstroms, 1000 angstroms. In this embodiment, the first cavity may be a heat pipe furnace, that is, the first oxide layer 103 may be formed by a thermal oxidation method. In some embodiments, the first oxide layer 103 may also be formed by means of chemical vapor deposition. The substrate 101 may also be rotated while forming the first oxide layer 103 to improve the thickness uniformity of the first oxide layer 103.
As shown in fig. 5, after forming the first oxide layer 103, the substrate 101 is placed in a second cavity to form a polysilicon layer 104 on the first oxide layer 103. The step of forming the polysilicon layer 104 may include flowing silane into the second cavity at a flow rate of 50sccm to 200sccm, and then raising the temperature of the second cavity to 590-670 ℃, such as 600 ℃ or 630 ℃, to form the polysilicon layer 104 on the first oxide layer 103. In this embodiment, when the temperature in the second cavity reaches 590-670 ℃, silane is gradually deposited on the first oxide layer 103 to form the polysilicon layer 104. The thickness of the first oxide layer 103 may be 600-1000 angstroms, such as 800 angstroms and 1000 angstroms. In this embodiment, the second cavity may be a chemical vapor deposition cavity, that is, the polysilicon layer 104 may be formed by chemical vapor deposition. The substrate 101 may also be rotated while forming the polysilicon layer 104 to improve the thickness uniformity of the polysilicon layer 104. It should be noted that polysilicon layer 104 may be an undoped polysilicon layer. As can be seen in fig. 5, a polysilicon layer 104 is formed on both the first surface and the second surface of the substrate 101.
As shown in fig. 6, after forming polysilicon layer 104, substrate 101 is placed within a third cavity to form a second oxide layer 105 on polysilicon layer 104. In this embodiment, the step of forming the second oxide layer 105 may include introducing a silicon-containing precursor, which may be Tetraethylorthosilicate (TEOS), into the third cavity, and heating the third cavity. In this embodiment, the temperature in the third chamber may be 570-650 ℃, for example 580-620 ℃, for example 600 ℃. In this embodiment, when the temperature in the third chamber reaches 570-650 ℃, Tetraethylorthosilicate (TEOS) forms a second oxide layer 105 on the epitaxial layer 102 and on the second surface of the substrate 101. The thickness of the second oxide layer 105 may be the same as the thickness of the first oxide layer 103. The thickness of the second oxide layer 105 may be 800-1000 angstroms, such as 800 angstroms, 900 angstroms, 1000 angstroms. In this embodiment, the third cavity may be a heat pipe furnace, that is, the second oxide layer 105 may be formed by a thermal oxidation method. In some embodiments, the second oxide layer 105 may also be formed by chemical vapor deposition. The substrate 101 may also be rotated when forming the second oxide layer 105 to improve the thickness uniformity of the second oxide layer 105. As can be seen from fig. 6, the second oxide layer 105 is formed on both the first surface and the second surface of the substrate 101.
As shown in fig. 6, in the present embodiment, the first oxide layer 103, the polysilicon layer 104, and the second oxide layer 105 are defined as a stacked structure 106. A stacked structure 106 is formed on both the first surface and the second surface of the substrate 101, the stacked structure 106 being located on the epitaxial layer 102, the stacked structure 106 also being located on the second surface of the substrate 101. In this embodiment, the first oxide layer 103 and the second oxide layer 105 may be silicon oxide or silicon oxynitride. In some embodiments, polysilicon layer 104 may also be replaced with a silicon nitride layer.
As shown in fig. 7, in step S4, after the laminated structure 106 is formed,a stacked structure 106 located on epitaxial layer 102 is etched. Specifically, the substrate 101 is placed in an etch cavity, and then the stacked structure 106 on the epitaxial structure 102 is etched, i.e., the second oxide layer 105 on the epitaxial structure 102 is etched away, to expose the polysilicon layer 104 on the epitaxial structure 102. In the present embodiment, the second oxide layer 105 may be removed, for example, by dry etching. The etching gas used in the present embodiment may be Cl2HBr or a mixture of HBr and another gas, e.g. HBr and O2And Cl2Or HBr and NF3And He. In this embodiment, the second oxide layer 105 on the epitaxial structure 102 is etched by dry etching, and during the etching process, the second oxide layer 105 on the second surface of the substrate 101 is not etched. If the second oxide layer 105 on the epitaxial layer 102 is etched by wet etching, the second oxide layer 105 on the second surface of the substrate 101 is also etched, and the second oxide layer 105 on the second surface of the substrate 101 cannot protect the polysilicon layer 104, so that when the polysilicon layer 104 on the epitaxial layer 102 is etched by wet etching in a later stage, the polysilicon layer 104 on the second surface of the substrate 101 is also etched, and the polysilicon layer 104 cannot protect the first oxide layer 103, so that the second oxide layer 105 on the epitaxial layer 102 is removed by dry etching in the present application.
As shown in fig. 8, in step S5, after removing the second oxide layer 105 on the epitaxial layer 102, the substrate 101 is placed in an etching solution to remove the polysilicon layer 104 on the epitaxial layer 102 and expose the first oxide layer 103. In this embodiment, the etching solution may be an alkaline solution, and the alkaline solution may include ammonia, hydrogen peroxide and deionized water; wherein the volume ratio of the ammonia water, the hydrogen peroxide and the deionized water can be 5:2: 500. The proportioned alkaline solution has good etching selectivity, and the etching rate of the alkaline solution to the polysilicon layer 104 is greater than that of the alkaline solution to the second oxide layer 105. In the present embodiment, the etching rate of the polysilicon layer 104 is much greater than that of the second oxide layer 105, and the ratio of the etching rate of the polysilicon layer 104 to that of the second oxide layer 105 may be 40:1.4, so that only a portion of the second oxide layer 105 is etched when the polysilicon layer 104 is etched. As can be seen from fig. 8, while the alkaline solution etches the polysilicon layer 104 and also etches the second oxide layer 105, since the etching rate of the polysilicon layer 104 is much greater than that of the second oxide layer 105, the thickness of the second oxide layer 105 is reduced when the polysilicon layer 104 is completely etched away. Note that the second oxide layer 105 is located on the second surface of the substrate 101, and as can be seen from fig. 6 to 8, the thickness of the second oxide layer 105 located on the second surface of the substrate 101 is reduced.
As shown in fig. 9, in step S6, after exposing the first oxide layer 103, the substrate 101 is placed in an etching solution to etch the first oxide layer 103 on the epitaxial layer 102 and to etch the second oxide layer 105 on the second surface of the substrate 101 to expose the epitaxial layer 102 and the polysilicon layer 104 on the second surface of the substrate 101. In this embodiment, the etching solution may be diluted hydrofluoric acid; wherein the volume ratio of the hydrofluoric acid to the deionized water can be 1:200-1: 500. In this embodiment, after the etching is finished, the first oxide layer 103 on the epitaxial layer 102 and the second oxide layer 105 on the second surface of the substrate 101 may be completely removed. Of course, in some embodiments, hydrofluoric acid and ammonium fluoride (NH) may also be used4F) The first oxide layer 103 and the second oxide layer 105. NH (NH)4F may be a buffer, by adjusting NH4The concentration of F can control the etch rate of the wet etch. In this embodiment, the hydrofluoric acid has a good etching selectivity, that is, the etching rate of the hydrofluoric acid on the second oxide layer 103 or the second oxide layer 105 is greater than the etching rate of the hydrofluoric acid on the polysilicon layer 104, so that when the second oxide layer 105 is etched away, the influence of the hydrofluoric acid on the polysilicon layer 104 is small, the integrity of the polysilicon layer 104 is not damaged, and the polysilicon layer 104 can be ensured to protect the first oxide layer 103. Meanwhile, since the second surface of the substrate 101 has the first oxide layer 103 and the polysilicon layer 104, the dopant ions in the substrate 101 can be prevented from overflowing outwards.
As shown in fig. 9, in the present embodiment, the first oxide layer 103 on the epitaxial layer 102 and the second oxide layer 105 on the second surface of the substrate 101 are simultaneously removed by the hydrofluoric acid solution, so that the work efficiency can be improved. Meanwhile, the hydrofluoric acid solution and the alkaline solution have good etching selection ratio, so that the plurality of substrates 101 can be placed in the multi-piece machine table at the same time, and then the plurality of substrates 101 are sequentially processed by the alkaline solution and the hydrofluoric acid solution without being separately processed, so that the working efficiency can be improved, and the cost is saved.
As shown in fig. 9, the present embodiment further provides a wafer backside seal structure, where the wafer backside seal structure includes a substrate 101, and the substrate 101 may include a first surface and a second surface that are oppositely disposed. In this embodiment, the substrate 101 may be a semiconductor material, and the semiconductor material may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other semiconductor materials such as iii-v compounds such as gallium arsenide. The substrate 101 may be a heavily doped substrate, an N-type substrate doped with Sb, As, P, N, or the like, or a P-type substrate doped with Ga, In, B, or the like, and may have a doping concentration of, for example, 1 × 1017To 1X 1020cm-3. The crystal plane of the substrate 101 may be (100), but for some high speed and high voltage devices a different crystal plane such as (111) may be used to enhance carrier mobility, or a (110) crystal plane may be used as needed to control the epitaxial growth rate.
As shown in fig. 9, in the present embodiment, the wafer backside seal structure further includes an epitaxial layer 102, the epitaxial layer 102 is located on the first surface of the substrate 101, the epitaxial layer 102 can be doped with ions, and the doping concentration of the doping ions in the epitaxial layer 102 is less than the doping concentration of the doping ions in the substrate 101. The epitaxial layer 102 may be formed by means of epitaxial growth.
As shown in fig. 9, in the present embodiment, the wafer backside seal structure further includes a first oxide layer 103, the first oxide layer 103 is located on the second surface of the substrate 101, and a polysilicon layer 104 is further formed on a surface of the first oxide layer 103 away from the epitaxial layer 102. The first oxide layer 103 may be silicon oxide or silicon oxynitride, the thickness of the first oxide layer 103 may be, for example, 800-1000 angstroms, and the thickness of the polysilicon layer 104 may be, for example, 600-1000 angstroms. The first oxide layer 103 may be formed by low temperature thermal oxidation, and the polysilicon layer 104 may be formed by chemical vapor deposition. In some embodiments, polysilicon layer 104 may also be replaced with a silicon nitride layer.
As shown in fig. 9, in the present embodiment, a first oxide layer 103 and a polysilicon layer 104 are formed on a second surface of a substrate 101, and during a subsequent operation on the substrate 101, the polysilicon layer 104 can effectively protect the first oxide layer 103 and prevent doped ions in the substrate 101 from being separated from the first oxide layer 103. Without the polysilicon layer 104, the thickness of the first oxide layer 103 is reduced in the subsequent operation, so that the dopant ions in the substrate 101 are extracted from the first oxide layer 103, thereby affecting the test. For example, when annealing the substrate 101, it is necessary to perform a test through the second surface of the substrate 101, that is, to test the resistivity of the second surface of the substrate 101, in order to obtain the temperature inside the chamber; if dopant ions enter the first oxide layer 103, the resistivity of the second surface will be reduced, thereby causing inaccuracies in the test, i.e. the temperature measured in the chamber. When the polysilicon layer 104 or the silicon nitride layer is formed on the first oxide layer 103, the first oxide layer 103 can be effectively protected, and meanwhile, because the polysilicon layer 104 is close to the substrate 101 in material structure, the temperature of the polysilicon layer 104 is measured to be close to the temperature of the substrate 101, the measured temperature is more accurate, and the temperature in the cavity obtained is more accurate.
As shown in fig. 9, in the present embodiment, the wafer backside seal structure can be applied to various integrated circuits, such as memory circuits, such as random access memory, dynamic random access memory, synchronous random access memory, static random access memory, or read only memory. The integrated circuit may also be a logic device such as a programmable logic array, an application specific integrated circuit, a combinational logic integrated circuit, a radio frequency circuit, or any other circuit device. The integrated circuit can also be used in, for example, consumer electronic products such as personal computers, portable computers, game machines, cellular phones, personal digital assistants, video cameras, digital cameras, cellular phones, and various other electronic products.
In summary, the present invention provides a wafer back seal structure and a method for manufacturing the same, wherein an epitaxial layer is formed on a substrate, and a doping concentration of the substrate is greater than a doping concentration of the epitaxial layer; the epitaxial layer is positioned on the first surface of the substrate, and then a laminated structure is formed on the epitaxial layer and the second surface of the substrate, wherein the laminated structure comprises a first oxide layer, a polycrystalline silicon layer and a second oxide layer; and then, the first oxide layer and the polycrystalline silicon layer positioned on the second surface of the substrate are reserved through an etching process, the polycrystalline silicon layer can protect the first oxide layer and prevent the influence of the subsequent process on the first oxide layer, and the second surface of the substrate is provided with the first oxide layer and the polycrystalline silicon layer, so that the separation of doped ions in the substrate can be avoided. Meanwhile, when the substrate is annealed, because the polycrystalline silicon layer is exposed on the surface and is close to the material structure of the substrate, the temperature close to the substrate can be obtained by measuring the temperature of the polycrystalline silicon layer, so that the temperature of the substrate is easier to monitor, and the temperature of an annealing chamber is convenient to control; the invention adopts alkaline solution with high selection ratio to etch the polysilicon, adopts acid solution to etch the oxide layer, uses acid and alkali wet etching in combination, and is processed by the alkaline solution tank and the acid solution tank at one time, thus having low cost.
Reference throughout this specification to "one embodiment", "an embodiment", or "a specific embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment, and not necessarily all embodiments, of the present invention. Thus, respective appearances of the phrases "in one embodiment", "in an embodiment", or "in a specific embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment of the present invention may be combined in any suitable manner with one or more other embodiments. It is to be understood that other variations and modifications of the embodiments of the invention described and illustrated herein are possible in light of the teachings herein and are to be considered as part of the spirit and scope of the present invention.
It will also be appreciated that one or more of the elements shown in the figures can also be implemented in a more separated or integrated manner, or even removed for inoperability in some circumstances or provided for usefulness in accordance with a particular application.
Additionally, any reference arrows in the drawings/figures should be considered only as exemplary, and not limiting, unless otherwise expressly specified. Further, as used herein, the term "or" is generally intended to mean "and/or" unless otherwise indicated. Combinations of components or steps will also be considered as being noted where terminology is foreseen as rendering the ability to separate or combine is unclear.
As used in the description herein and throughout the claims that follow, "a", "an", and "the" include plural references unless otherwise indicated. Also, as used in the description herein and throughout the claims that follow, unless otherwise indicated, the meaning of "in …" includes "in …" and "on … (on)".
The above description of illustrated embodiments of the invention, including what is described in the abstract of the specification, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention, as those skilled in the relevant art will recognize and appreciate. As indicated, these modifications may be made to the present invention in light of the foregoing description of illustrated embodiments of the present invention and are to be included within the spirit and scope of the present invention.
The systems and methods have been described herein in general terms as the details aid in understanding the invention. Furthermore, various specific details have been given to provide a general understanding of the embodiments of the invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well-known structures, materials, and/or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.
Thus, although the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosures, and it will be appreciated that in some instances some features of the invention will be employed without a corresponding use of other features without departing from the scope and spirit of the invention as set forth. Thus, many modifications may be made to adapt a particular situation or material to the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular terms used in following claims and/or to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include any and all embodiments and equivalents falling within the scope of the appended claims. Accordingly, the scope of the invention is to be determined solely by the appended claims.
The above description is only a preferred embodiment of the present application and a description of the applied technical principle, and it should be understood by those skilled in the art that the scope of the present invention related to the present application is not limited to the technical solution of the specific combination of the above technical features, and also covers other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, for example, the technical solutions formed by mutually replacing the above features with (but not limited to) technical features having similar functions disclosed in the present application.
Other technical features than those described in the specification are known to those skilled in the art, and are not described herein in detail in order to highlight the innovative features of the present invention.

Claims (8)

1. A method for manufacturing a wafer back seal structure comprises the following steps:
providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged;
forming an epitaxial layer on the first surface;
forming a laminated structure on the epitaxial layer and the second surface; the laminated structure comprises a first oxide layer, a polycrystalline silicon layer and a second oxide layer;
removing the second oxide layer on the epitaxial layer by dry etching to expose the polysilicon layer on the first surface;
removing the polysilicon layer on the epitaxial layer by wet etching to expose the first oxide layer on the first surface;
removing the first oxide layer on the epitaxial layer and the second oxide layer on the second surface by wet etching to expose the epitaxial layer and the polysilicon layer on the second surface;
soaking the substrate by using an alkaline solution to remove the polycrystalline silicon layer; wherein the volume ratio of ammonia water, hydrogen peroxide and deionized water in the alkaline solution is 5:2: 500;
etching the second oxide layer on the second surface while removing the polysilicon layer on the first surface, wherein the etching rate of the polysilicon layer on the first surface is greater than that of the second oxide layer;
wherein the ratio of the etching rate of the polysilicon layer to the etching rate of the second oxide layer is 40: 1.4.
2. The manufacturing method according to claim 1, wherein the step of forming the first oxide layer comprises:
placing the substrate in a first cavity;
and introducing a silicon-containing precursor into the first cavity, and raising the temperature in the first cavity to 550-620 ℃.
3. The method of manufacturing according to claim 1, wherein the step of forming the polysilicon layer comprises:
placing the substrate in a second cavity;
introducing silane into the second cavity, and raising the temperature in the second cavity to 590-670 ℃.
4. The manufacturing method according to claim 1, wherein the step of forming the second oxide layer includes:
placing the substrate within a third chamber;
and introducing a silicon-containing precursor into the third cavity, and raising the temperature in the third cavity to 570-650 ℃.
5. The manufacturing method according to claim 1, wherein the first oxide layer on the epitaxial layer and the second oxide layer on the second surface are etched using a dilute hydrofluoric acid solution having a volume ratio of hydrofluoric acid to deionized water of 1:200 to 1: 500.
6. The method according to claim 1, wherein the first oxide layer and the second oxide layer have a thickness of 800 to 1000 angstroms, and the polysilicon layer has a thickness of 600 to 1000 angstroms.
7. The manufacturing method according to claim 1, wherein the substrate is in a rotated state when the laminated structure is formed.
8. A wafer backside seal structure manufactured by the manufacturing method according to any one of claims 1 to 7, comprising:
a substrate comprising a first surface and a second surface disposed opposite;
an epitaxial layer on the first surface;
a first oxide layer on the second surface of the substrate;
and the polycrystalline silicon layer is positioned on the first oxidation layer.
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