CN113793802A - Wafer back sealing structure and manufacturing method - Google Patents
Wafer back sealing structure and manufacturing method Download PDFInfo
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- CN113793802A CN113793802A CN202111070680.0A CN202111070680A CN113793802A CN 113793802 A CN113793802 A CN 113793802A CN 202111070680 A CN202111070680 A CN 202111070680A CN 113793802 A CN113793802 A CN 113793802A
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- 238000007789 sealing Methods 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 97
- 238000000034 method Methods 0.000 claims abstract description 95
- 239000010410 layer Substances 0.000 claims abstract description 79
- 230000003647 oxidation Effects 0.000 claims abstract description 47
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 47
- 239000011241 protective layer Substances 0.000 claims abstract description 24
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 39
- 229910052760 oxygen Inorganic materials 0.000 claims description 39
- 239000001301 oxygen Substances 0.000 claims description 39
- 239000007789 gas Substances 0.000 claims description 11
- 238000001039 wet etching Methods 0.000 claims description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 229910052739 hydrogen Inorganic materials 0.000 claims description 7
- 239000001257 hydrogen Substances 0.000 claims description 7
- 238000002161 passivation Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 60
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 6
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000003908 quality control method Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
Abstract
The invention provides a manufacturing method of a wafer back seal structure, which comprises the following steps: providing a substrate, wherein the substrate is a heavily doped substrate, the substrate is provided with a first surface and a second surface which are oppositely arranged, and an epitaxial layer is formed on the first surface of the substrate; forming a protective layer on the surface of the epitaxial layer, the epitaxial layer and the side wall of the substrate; forming a wafer back sealing structure on the second surface of the substrate; and removing the surface of the epitaxial layer, the epitaxial layer and the protective layer on the side wall of the substrate. The wafer back sealing structure is generated by adopting a thermal oxidation process, and the wafer back sealing structure which grows on the substrate needs to be consumed due to the thermal oxidation process, so that the compactness is high, and the problem that the wafer back sealing structure falls off is avoided during the subsequent furnace tube process; meanwhile, when the wafer back sealing structure is formed, the epitaxial layer on the first surface of the substrate is protected by the protective layer, so that the epitaxial layer is prevented from being consumed and damaged.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a wafer back sealing structure and a manufacturing method thereof.
Background
At present, wafers used in image sensor chip products are generally heavily doped P-type substrates, and the Resistivity (Resistivity) of the wafers is about 0.01 Ω · cm. An epitaxial layer is grown on a heavily doped substrate, but the temperature of the epitaxial growth process is very high (usually 1130 ℃), the dopant in the substrate can diffuse out, this phenomenon is called "auto-doping effect", and a protective layer is needed to prevent a large amount of boron in the substrate from being separated out in the manufacturing process to influence the electrical properties of the epitaxial layer. Therefore, at present, a Chemical Vapor Deposition (CVD) method is used to deposit an LTO film (low temperature oxide film) on the first surface and the sidewall of the substrate, then an etching process is used to remove the LTO film on the sidewall, the substrate is turned over, the second surface of the substrate on which no LTO film is deposited is placed facing upward, that is, the second surface of the substrate on which no LTO film is deposited is away from the susceptor, and then an epitaxial layer is grown. However, at present, manufacturers modify the hardware (hardware) of the machine to eliminate the self-doping effect, and do not need to form an LTO film to protect the substrate to generate the self-doping effect.
Wafer manufacturers use low temperature silicon dioxide (LTO) process as the back sealing material, and the subsequent chip manufacturing will execute the furnace process, specifically, a vertical furnace platform will be used to grow a layer of oxygen pad, but the difference between the thermal expansion coefficients of the LTO film and the silicon carbide boat (SIC boat) is large, so that the LTO film on the back peels off to generate defects, which affects the yield of the product.
Disclosure of Invention
The invention aims to provide a wafer back sealing structure and a manufacturing method thereof, which aim to solve the problem of falling-off of an LTO film on the back surface of a heavily doped P-type substrate.
To solve the above technical problem, the present invention provides a method for manufacturing a wafer back seal structure, comprising:
providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged, and an epitaxial layer is formed on the first surface of the substrate;
forming a protective layer on the surface of the epitaxial layer, the epitaxial layer and the side wall of the substrate;
forming a wafer back sealing structure on the second surface of the substrate;
and removing the surface of the epitaxial layer, the epitaxial layer and the protective layer on the side wall of the substrate.
Optionally, the process of forming the wafer back sealing structure is a thermal oxidation process.
Optionally, the thermal oxidation process includes performing a dry oxygen oxidation process and then performing a wet oxygen oxidation process.
Optionally, the temperature of the dry oxygen oxidation process is 700 ℃ to 750 ℃, and the temperature of the wet oxygen oxidation process is 930 ℃ to 980 ℃.
Optionally, the gas of the dry oxygen oxidation process comprises oxygen, and the gas of the wet oxygen oxidation process comprises hydrogen and oxygen.
Optionally, the thickness of the wafer back sealing structure is 3800 angstroms-4200 angstroms.
Optionally, the process of forming the protective layer is a chemical vapor deposition process.
Optionally, the thickness of the protective layer is 800 angstroms to 1200 angstroms.
Optionally, a wet etching process is used to remove the surface of the epitaxial layer, and the protective layer on the sidewall of the substrate, and the wet etching process simultaneously removes a part of the wafer back sealing structure on the substrate.
Based on the same inventive concept, the invention also provides a wafer back seal structure, which is prepared by the manufacturing method of the wafer back seal structure, and the manufacturing method comprises the following steps:
a substrate comprising a first surface and a second surface disposed opposite;
an epitaxial layer on the first surface of the substrate;
and the wafer back sealing structure is positioned on the second surface of the substrate.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a wafer back seal structure and a manufacturing method, wherein an epitaxial layer is formed on a first surface of a substrate, then a protective layer is formed on the surface of the epitaxial layer, the epitaxial layer and the side wall of the substrate, and further a wafer back seal structure is formed on a second surface of the substrate; the wafer back sealing structure is generated by adopting a thermal oxidation process, and the wafer back sealing structure is high in compactness due to the thermal oxidation process, so that the problem that the wafer back sealing structure falls off is avoided during the subsequent furnace tube process; because the wafer back sealing structure adopts a thermal oxidation process, the expansion coefficient of the generated oxide layer is closer to that of the silicon carbide boat, and the problem of falling off of the wafer back sealing structure caused by the difference of the expansion coefficients in the subsequent manufacturing process is avoided; meanwhile, when the wafer back sealing structure is formed, the epitaxial layer on the first surface of the substrate is protected by the protective layer, so that the epitaxial layer is prevented from being consumed and damaged.
Drawings
FIG. 1 is a flow chart of a method for fabricating a wafer backside seal structure according to an embodiment of the present invention;
fig. 2 to 5 are schematic structural views corresponding to a manufacturing method of a wafer back seal structure according to an embodiment of the invention;
in the figure, the position of the upper end of the main shaft,
100-a substrate; 101-an epitaxial layer; 102-a protective layer; 103-wafer back sealing structure; .
Detailed Description
The wafer back seal structure and the manufacturing method according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
FIG. 1 is a flow chart of a method for fabricating a wafer backside seal structure according to an embodiment of the present invention; as shown in fig. 1, an embodiment of the invention provides a method for manufacturing a wafer back seal structure, including:
step S10, providing a substrate, wherein the substrate has a first surface and a second surface which are oppositely arranged, and an epitaxial layer is formed on the first surface of the substrate;
step S20, forming a protective layer on the surface of the epitaxial layer, the epitaxial layer and the side wall of the substrate;
step S30, forming a wafer back sealing structure on the second surface of the substrate;
and step S40, removing the protective layer on the surface of the epitaxial layer, the epitaxial layer and the side wall of the substrate.
Fig. 2 to 5 are schematic structural diagrams corresponding to a manufacturing method of a wafer backside seal structure according to an embodiment of the invention, and each step of the trench forming method provided in this embodiment is described in detail with reference to fig. 2 to 5.
Referring to fig. 2, a substrate 100 is provided. The material of the substrate 100 may be a semiconductor material, which may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or other semiconductor materials, such as iii-v compounds like gallium arsenide. The substrate 100 is a heavily doped substrate, the resistivity of the substrate 100 is, for example, 0.01 Ω · cm to 0.05 Ω · cm, the substrate 100 may be an N-type substrate doped with Sb, As, P, N, or the like, or a P-type substrate doped with Ga, In, B, or the like, In the present embodiment, the substrate 100 is, for example, a heavily doped P-type substrate, and the thickness of the substrate 100 is, for example, 750 μm to 770 μm.
The substrate 100 has a first surface (which may be referred to as a front surface in this embodiment) and a second surface (which may be referred to as a back surface in this embodiment) that are opposite to each other, and the epitaxial layer 101 is formed on the first surface of the substrate 100. The substrate 100 is placed in an epitaxial furnace, and after the temperature is raised to a predetermined temperature, a reaction gas carried by, for example, an inert gas is introduced to form an epitaxial layer 101 on the first surface of the substrate 100. The epitaxial layer 101 may be a homoepitaxial layer of the same material as the substrate 100 or a heteroepitaxial layer of a different material from the substrate 100. In the present embodiment, the epitaxial furnace may be a (liquid phase epitaxial) barrel furnace, a flat plate epitaxial furnace, or a monolithic epitaxial furnace. The epitaxial temperature is set reasonably according to growth rate and epitaxial layer quality control requirements, for example, 700 ℃ to 1300 ℃. The epitaxial layer 101 is formed to have a first thickness that is greater than the thickness of the epitaxial layer that is required to ultimately form the high voltage device, i.e., greater than a minimum thickness to avoid device breakdown. In this implementationIn this example, the thickness of the epitaxial layer 101 is, for example, 4 μm to 6 μm. In some embodiments, the epitaxial furnace may also be charged with, for example, B2H6、PH3、AsH3And the like so that the epitaxial layer 101 is doped with the same type as the substrate 100 to reduce on-resistance and prevent parasitic diode formation at the interface. In some embodiments, before the epitaxial layer 101 is formed, a buffer layer may be deposited on the substrate 100, the buffer layer being made of a material different according to the lattice constant matching requirement between the epitaxial layer 101 and the substrate 100, such as Si, Ge, GaN, etc., and the buffer layer may be formed by a chemical vapor deposition method. In this embodiment, the epitaxial layer 101 may further be doped with ions, and the doping concentration of the doping ions in the epitaxial layer 101 may be smaller than the doping concentration of the doping ions in the substrate 100.
Referring to fig. 3, a protective layer 102 is formed on the surface of the epitaxial layer 101, the epitaxial layer 101 and the sidewall of the substrate 100. The substrate 100 formed with the epitaxial layer 101 is placed in a CVD chamber, and a protective layer 102 is formed using a chemical vapor deposition process. In the present embodiment, the protection layer 102 is formed by a High Aspect Ratio Process (HARP). In the high aspect ratio deposition process, the process gas comprises, for example, TEOS (tetraethylorthosilicate) and O3Preferably, the TEOS flow is, for example, 500sccm to 3000sccm, O3The flow rate is, for example, 10000sccm to 30000 sccm. The protective layer 102 is, for example, silicon oxide, and the thickness of the protective layer 102 is, for example, 800 angstroms to 1200 angstroms.
Referring to fig. 4, a wafer backside seal structure 103 is formed on the second surface of the substrate 100. The wafer back sealing structure 103 is, for example, an oxide layer, and the wafer back sealing structure 103 is formed by a thermal oxidation process. The thermal oxidation process comprises a dry oxygen oxidation process and a wet oxygen oxidation process. The temperature of the dry oxygen oxidation process is, for example, 700 ℃ to 750 ℃, and the temperature of the wet oxygen oxidation process is, for example, 930 ℃ to 980 ℃. The gas of the dry oxygen oxidation process is oxygen, and the gas flow rate of the oxygen is, for example, 10slm to 15 slm. The gases of the wet oxygen oxidation process are hydrogen and oxygen, and the gas ratio of the hydrogen and the oxygen is, for example, 4:4 to 7.5:4, that is, in specific implementation, the gases of the hydrogen and the oxygen may be 4L respectively, and the gases of the hydrogen and the oxygen may also be 7.5L and 4L respectively. The wafer backside seal structure 103 has a thickness of 3800 angstroms to 4200 angstroms, for example. The thermal oxidation process firstly adopts a dry oxygen oxidation process (for example, 700 ℃ to 750 ℃) with slightly lower temperature, avoids the escape of heavily doped ions in the substrate 100, executes a wet oxygen oxidation process after an oxide layer with a certain thickness is grown, increases the temperature (for example, 930 ℃ to 980 ℃), and introduces hydrogen and oxygen, thereby increasing the growth rate of the oxide layer and reducing the process time.
The wafer back sealing structure 103 formed by the thermal oxidation process is an oxide layer formed by the reaction of oxygen and Si in the substrate 100 at high temperature, and has good compactness, so that when a vertical furnace tube machine is adopted for growing a layer of oxygen cushion process in subsequent chip manufacturing, the back wafer back sealing structure cannot be peeled off to generate defects, and the yield of products is not influenced.
Because the compactness of the wafer back seal structure 103 formed by the thermal oxidation process is good, the Etching Rate (ER) of the wafer back seal structure 103 formed by the thermal oxidation process is low, and the etching Rate of the low-temperature silicon dioxide is 1.5 times of that of the thermal-oxidized silicon oxide, the wafer back seal structure 103 formed by the thermal oxidation process increases the rework frequency bearing capacity of the subsequent process, that is, when the subsequent process needs to be reworked for many times, the wafer back seal structure 103 formed by the thermal oxidation process can still protect the substrate 100 from being corroded, the wafer back seal structure does not need to be regenerated, and the production cost is saved.
Because the thermal expansion coefficient of the wafer back sealing structure 103 formed by the thermal oxidation process is closer to the thermal expansion coefficient of the silicon carbide boat, in the subsequent process of growing a layer of oxygen cushion by using a vertical furnace platform in the chip manufacturing, the wafer back sealing structure 103 cannot be peeled off to generate defects due to the large difference between the thermal expansion coefficient and the thermal expansion coefficient of the silicon carbide boat, so that the yield of products is influenced.
Referring to fig. 5, after the wafer back sealing structure 103 is formed, the surface of the epitaxial layer 101, the epitaxial layer 101 and the protective layer 102 on the sidewall of the substrate 100 are removed by a wet etching process, and the wet etching process simultaneously removes a portion of the wafer back sealing structure 103 on the substrate. The solution of the wet etching process is, for example, a diluted hydrofluoric acid (DHF) solution. After the wet etching process, the thickness of the wafer back sealing structure 103 is remained, for example, 2800 angstroms to 3200 angstroms. Before the wet etching process, a Chemical Mechanical Polishing (CMP) process may be used to adjust the thickness of the protection layer 102, so that the required thickness of the wafer back seal structure is obtained after the wet etching process, that is, the thickness of the protection layer 102 may be adjusted according to any experimental requirements, and does not need to be consistent with the etching thickness of the wafer back seal structure 103, and the thicknesses of the protection layer 102 and the wafer back seal structure 103 may be flexibly set through the CMP process.
With reference to fig. 5, based on the same inventive concept, an embodiment of the present invention further provides a wafer back seal structure, which is manufactured by the method for manufacturing the wafer back seal structure, including:
a substrate 100 comprising a first surface and a second surface oppositely disposed;
an epitaxial layer 101 on a first surface of the substrate 100;
a wafer backside seal structure 103 located on the second surface of the substrate 100.
The substrate 100 is, for example, a heavily doped P-type substrate, and the resistivity of the substrate 100 is, for example, 0.01 Ω · cm to 0.05 Ω · cm. The wafer back sealing structure 103 is formed by a thermal oxidation process. The thermal oxidation process comprises a dry oxygen oxidation process and a wet oxygen oxidation process, wherein the dry oxygen oxidation process is executed firstly, and then the wet oxygen oxidation process is executed.
In summary, according to the wafer back seal structure and the manufacturing method provided by the embodiment of the invention, the epitaxial layer is formed on the first surface of the substrate, the protective layer is formed on the surface of the epitaxial layer, the epitaxial layer and the side wall of the substrate, and the wafer back seal structure is further formed on the second surface of the substrate; the wafer back sealing structure is generated by adopting a thermal oxidation process, and the wafer back sealing structure which grows on the substrate needs to be consumed due to the thermal oxidation process, so that the compactness is high, and the problem that the wafer back sealing structure falls off is avoided during the subsequent furnace tube process; because the wafer back sealing structure adopts a thermal oxidation process, the expansion coefficient of the generated oxide layer is closer to that of the silicon carbide boat, and the problem of falling off of the wafer back sealing structure caused by the difference of the expansion coefficients in the subsequent manufacturing process is avoided; meanwhile, when the wafer back sealing structure is formed, the epitaxial layer on the first surface of the substrate is protected by the protective layer, so that the epitaxial layer is prevented from being consumed and damaged.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method for manufacturing a wafer back seal structure comprises the following steps:
providing a substrate, wherein the substrate is a heavily doped substrate, the substrate is provided with a first surface and a second surface which are oppositely arranged, and an epitaxial layer is formed on the first surface of the substrate;
forming a protective layer on the surface of the epitaxial layer, the epitaxial layer and the side wall of the substrate;
forming a wafer back sealing structure on the second surface of the substrate;
and removing the surface of the epitaxial layer, the epitaxial layer and the protective layer on the side wall of the substrate.
2. The method of claim 1, wherein the wafer backside seal structure is formed by a thermal oxidation process.
3. The method of claim 2, wherein the thermal oxidation process comprises performing a dry oxygen oxidation process followed by a wet oxygen oxidation process.
4. The method for manufacturing the wafer back sealing structure as claimed in claim 3, wherein the temperature of the dry oxygen oxidation process is 700 ℃ to 750 ℃, and the temperature of the wet oxygen oxidation process is 930 ℃ to 980 ℃.
5. The method of claim 3, wherein the dry oxygen oxidation process gas comprises oxygen and the wet oxygen oxidation process gas comprises hydrogen and oxygen.
6. The method of claim 1, wherein the wafer back seal structure has a thickness of 3800 angstroms to 4200 angstroms.
7. The method of claim 1, wherein the step of forming the passivation layer is a chemical vapor deposition process.
8. The method for manufacturing the wafer backside seal structure of claim 1 or 7, wherein the thickness of the protection layer is 800 angstroms to 1200 angstroms.
9. The method for manufacturing the wafer back sealing structure as claimed in claim 1, wherein a wet etching process is used to remove the surface of the epitaxial layer, the epitaxial layer and the protective layer on the sidewall of the substrate, and the wet etching process simultaneously removes a portion of the wafer back sealing structure on the substrate.
10. A wafer back seal structure prepared by the method of manufacturing a wafer back seal structure according to any one of claims 1 to 8, comprising:
the substrate comprises a first surface and a second surface which are oppositely arranged, and the substrate is a heavily doped substrate;
an epitaxial layer on the first surface of the substrate;
and the wafer back sealing structure is positioned on the second surface of the substrate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111070680.0A CN113793802A (en) | 2021-09-13 | 2021-09-13 | Wafer back sealing structure and manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111070680.0A CN113793802A (en) | 2021-09-13 | 2021-09-13 | Wafer back sealing structure and manufacturing method |
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| CN113793802A true CN113793802A (en) | 2021-12-14 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115642112A (en) * | 2022-11-24 | 2023-01-24 | 西安奕斯伟材料科技有限公司 | Back sealing device and method for silicon wafer |
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2021
- 2021-09-13 CN CN202111070680.0A patent/CN113793802A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115642112A (en) * | 2022-11-24 | 2023-01-24 | 西安奕斯伟材料科技有限公司 | Back sealing device and method for silicon wafer |
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Application publication date: 20211214 |