CN104425248B - Heavily doped P-type substrate back sealing process method - Google Patents
Heavily doped P-type substrate back sealing process method Download PDFInfo
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- CN104425248B CN104425248B CN201310382900.2A CN201310382900A CN104425248B CN 104425248 B CN104425248 B CN 104425248B CN 201310382900 A CN201310382900 A CN 201310382900A CN 104425248 B CN104425248 B CN 104425248B
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- 239000000758 substrate Substances 0.000 title claims abstract description 84
- 238000000034 method Methods 0.000 title claims abstract description 64
- 230000008569 process Effects 0.000 title claims abstract description 30
- 238000007789 sealing Methods 0.000 title claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 43
- 229920005591 polysilicon Polymers 0.000 claims abstract description 43
- 238000000407 epitaxy Methods 0.000 claims abstract description 30
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 6
- 238000001947 vapour-phase growth Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 230000008859 change Effects 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000012071 phase Substances 0.000 claims 1
- 238000004062 sedimentation Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 77
- 239000012535 impurity Substances 0.000 abstract description 11
- 238000005253 cladding Methods 0.000 abstract description 4
- 239000011241 protective layer Substances 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 11
- 238000005530 etching Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000007788 liquid Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
A kind of heavily doped P-type substrate back sealing process method, comprises the following steps：Heavily doped P-type substrate is provided, heavily doped P-type substrate includes the heavily doped P-type substrate and N-type epitaxy layer of stacking；Oxide layer, oxide layer cladding heavily doped P-type substrate are formed in the outside of heavily doped P-type substrate；Polysilicon layer, polysilicon layer cladding oxide layer are formed in the outside of oxide layer；Remove the polysilicon of side of the N-type epitaxy layer away from heavily doped P-type substrate；Remove the oxide of side of the N-type epitaxy layer away from heavily doped P-type substrate.Above-mentioned heavily doped P-type substrate back sealing process method, oxide and the polysilicon covering that surface, the side of heavily doped P-type substrate and the side of N-type epitaxy layer of side of the heavily doped P-type substrate away from N-type epitaxy layer are all stacked.The oxide and polysilicon of stacking can effectively prevent the p type impurity in heavily doped P-type substrate to be diffused into N-type epitaxy layer as protective layer.
Description
Technical field
The present invention relates to semiconductor applications, more particularly to a kind of heavily doped P-type substrate back sealing process method.
Background technology
In high pressure punch（PT types）Insulated gate bipolar transistor（Insulated Gate Bipolar
Transistor, IGBT）Production process in, the substrate of usually used wafer is heavily doped P-type substrate, the wafer used
Epitaxial wafer is generally the larger N-type epitaxial wafer of resistivity.Heavily doped P-type substrate refers to that doping concentration is larger, and resistivity exists substantially
The substrate of 0.001ohm.cm~0.005ohm.cm boron-doping.The IGBT devices of heavily doped P-type substrate combination N-type epitaxial wafer manufacture
Part, can preferably optimize the performance of IGBT device.But in actual manufacturing process, can introduce multiple simultaneously in a device
The epitaxial wafer that the p type impurity in the heavily doped P-type substrate in substrate is diffused into another substrate is easily caused in substrate, production process
In, the doping type and doping concentration of epitaxial layer are influenceed, so as to influence the performance of product.
The content of the invention
Based on this, it is necessary to provide a kind of heavily doped P-type substrate back sealing process for preventing heavily doped P-type substrate impurity from spreading
Method.
A kind of heavily doped P-type substrate back sealing process method, comprises the following steps：
Heavily doped P-type substrate is provided, the heavily doped P-type substrate includes the heavily doped P-type substrate and N-type extension of stacking
Layer；
Oxide layer is formed in the outside of the heavily doped P-type substrate, the oxide layer coats the heavily doped P-type substrate；
Polysilicon layer is formed in the outside of the oxide layer, the polysilicon layer coats the oxide layer；
Remove the polysilicon of side of the N-type epitaxy layer away from the heavily doped P-type substrate；
Remove the oxide of side of the N-type epitaxy layer away from the heavily doped P-type substrate.
In one of the embodiments, the oxide layer is formed using boiler tube atmospheric pressure oxidation method.
In one of the embodiments, the temperature of the boiler tube atmospheric pressure oxidation method is 750 DEG C~1100 DEG C, the time of oxidation
For 60min~180min.
In one of the embodiments, the thickness of the oxide layer is 8000 angstroms~13000 angstroms.
In one of the embodiments, the polysilicon layer is formed using low-pressure chemical vapor phase deposition method.
In one of the embodiments, the source of the gas of the low-pressure chemical vapor phase deposition method is SiH4。
In one of the embodiments, the thickness of the polysilicon layer is 6000 angstroms~12000 angstroms.
In one of the embodiments, it is described to remove the side of the N-type epitaxy layer away from the heavily doped P-type substrate
In the operation of polysilicon, the polysilicon is removed using dry etching.
In one of the embodiments, dry etching can be plasma etch process.
In one of the embodiments, it is described to remove the side of the N-type epitaxy layer away from the heavily doped P-type substrate
In the operation of oxide, the oxide is removed using wet etching.
Above-mentioned heavily doped P-type substrate back sealing process method, etches away side of the N-type epitaxy layer away from heavily doped P-type substrate
Oxide and polysilicon after, surface, the side of heavily doped P-type substrate of side of the heavily doped P-type substrate away from N-type epitaxy layer
And the oxide that is all stacked of the side of N-type epitaxy layer and polysilicon covering.The oxide and polysilicon of stacking are used as protection
Layer, can effectively prevent the p type impurity in heavily doped P-type substrate to be diffused into N-type epitaxy layer.
Brief description of the drawings
Fig. 1 is the flow chart of the heavily doped P-type substrate back sealing process method of an embodiment；
Fig. 2 to Fig. 6 is the structure change schematic diagram corresponding to the flowchart process shown in Fig. 1.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.Many details are elaborated in the following description to fully understand this hair
It is bright.But the invention can be embodied in many other ways as described herein, those skilled in the art can be not
Similar improvement is done in the case of running counter to intension of the present invention, therefore the present invention is not limited to the specific embodiments disclosed below.
As shown in figure 1, the heavily doped P-type substrate back sealing process method of an embodiment, comprises the following steps：
S10, offer heavily doped P-type substrate.
Fig. 2 is refer to, heavily doped P-type substrate 10 includes the heavily doped P-type substrate 12 and N-type epitaxy layer 14 of stacking.
P type impurity can be boron in heavily doped P-type substrate 12（B）.The resistivity of heavily doped P-type substrate 12 can be
0.001ohm.cm~0.005ohm.cm.N-type impurity can be phosphorus in N-type epitaxy layer 14（P）Or arsenic（As）.N-type epitaxy layer 14
Resistivity can be 50ohm.cm~110ohm.cm.
S20, the outside formation oxide layer in heavily doped P-type substrate, oxide layer cladding heavily doped P-type substrate.
The structure formed on the surface of heavily doped P-type substrate 10 after oxide layer 20 is as shown in Figure 3.
In the present embodiment, oxide layer 20 can be formed using boiler tube atmospheric pressure oxidation method.The material of oxide layer 20 is oxidation
Silicon.The temperature of boiler tube atmospheric pressure oxidation method is 750 DEG C~1100 DEG C, and the time of oxidation is 60min~180min.Using boiler tube normal pressure
During oxidizing process, under hot conditions, the silicon atom reaction generation SiO2 on oxygen molecule and the surface of heavily doped P-type substrate 10.Using boiler tube
The structure of oxide layer 20 of atmospheric pressure oxidation method formation is finer and close, prevents that the effect that impurity spreads is more preferable.The thickness of oxide layer 20 can
Think 8000 angstroms~13000 angstroms.It is conventional field oxygen menu thickness that the thickness of oxide layer 20, which is 8000 angstroms~13000 angstroms, is easy to
Production.It is raw if the thickness of oxide layer 20 is too thick if the thickness of oxide layer 20 is too thin, it is possible to impurity can not be stopped completely
The longer time is also required to when the longer time is needed during production, and being removed.In other embodiments, oxide layer 20 can also be used
The techniques such as steam oxidation in situ are formed.The forming method of oxide layer 20 is not restricted, as long as the energy of oxide layer 20 formed
Enough meet thickness and quality requirement.
S30, the outside formation polysilicon layer in oxide layer, polysilicon layer cladding oxide layer.
The structure formed on the surface of oxide layer 20 after polysilicon layer 30 is as shown in Figure 4.
Polysilicon layer 30 is formed using low-pressure chemical vapor phase deposition method.The thickness of polysilicon layer 30 can for 6000 angstroms~
1200 angstroms.When the thickness of polysilicon layer 30 is 6000 angstroms~1200 angstroms, the effect for stopping impurity diffusion of polysilicon layer 30 is preferable.
The thickness of polysilicon layer 30 is too thin, stops that the ability of impurity diffusion is weaker.The thickness of polysilicon layer 30 is too thick, is needed more during production
The long time, and it is also required to the longer time when removing.Low-pressure chemical vapor phase deposition method formation polysilicon layer 30 when temperature be
600 DEG C~700 DEG C.The source of the gas of low-pressure chemical vapor phase deposition method is SiH4。SiH4Flow be about 50sccm~200sccm.
S40, the polysilicon for removing side of the N-type epitaxy layer away from heavily doped P-type substrate.
The structure removed after the polysilicon of side of the N-type epitaxy layer 14 away from heavily doped P-type substrate 12 is as shown in Figure 5.
In the operation for the polysilicon for removing side of the N-type epitaxy layer 14 away from heavily doped P-type substrate 12, polysilicon can be adopted
Use dry etch process.Dry etching can be plasma etching.Etching gas can be the gases such as hydrogen bromide, chlorine.It is dry
The selectivity of method etching is high, is more suitable for the polysilicon for removing target location.
S50, the oxide for removing side of the N-type epitaxy layer away from heavily doped P-type substrate.
The structure removed after the oxide of side of the N-type epitaxy layer 14 away from heavily doped P-type substrate 12 is as shown in Figure 6.
In the operation for the oxide for removing side of the N-type epitaxy layer 14 away from heavily doped P-type substrate 12, oxide can be adopted
Removed with the method for wet etching.The solution of wet etching can buffer etching liquid or hydrogen fluoride (HF) aqueous solution for BOE.BOE
It is hydrogen fluoride and ammonium fluoride (NH to buffer etching liquid4F the aqueous solution).In BOE buffering etching liquids, NH4F is buffer, passes through regulation
NH4F concentration can control the corrosion rate of wet etching.
Above-mentioned heavily doped P-type substrate back sealing process method, etches away N-type epitaxy layer 14 away from heavily doped P-type substrate 12
After the oxide and polysilicon of side, the surface of side of the heavily doped P-type substrate 12 away from N-type epitaxy layer 14, heavily doped P-type base
Oxide and the polysilicon covering that the side of piece 12 and the side of N-type epitaxy layer 14 are all stacked.By heavily doped P-type substrate 10
When carrying out follow-up manufacturing process, because polysilicon layer 30 can avoid etching from removing in subsequent wet etching process, stacking
Oxide layer 20 and polysilicon layer 30 as protective layer, can effectively prevent the p type impurity in heavily doped P-type substrate 12 to be diffused into
The performance of the product of the influence manufacture of N-type epitaxy layer 14.Meanwhile, after semiconductor fabrication process terminates, when being removed compared to SiN,
Need to use nitric acid, a large amount of smog can be produced during reaction, there is potential safety hazard, above-mentioned heavily doped P-type substrate back sealing process method
In polysilicon layer 30 easily etching remove.And polysilicon layer 30 will not produce surface stress, if the surface stress produced is big,
Easily cause disk to crack, the danger such as sliver.Above-mentioned heavily doped P-type substrate back sealing process method, technological operation is simple, peace
It is complete reliable, it is easier to realize in production.
Embodiment described above only expresses the several embodiments of the present invention, and it describes more specific and detailed, but simultaneously
Therefore the limitation to the scope of the claims of the present invention can not be interpreted as.It should be pointed out that for one of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the guarantor of the present invention
Protect scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
1. a kind of heavily doped P-type substrate back sealing process method, it is characterised in that comprise the following steps：
Heavily doped P-type substrate is provided, the heavily doped P-type substrate includes the heavily doped P-type substrate and N-type epitaxy layer of stacking；
Oxide layer is formed in the outside of the heavily doped P-type substrate, the oxide layer coats the heavily doped P-type substrate；
Polysilicon layer is formed in the outside of the oxide layer, the polysilicon layer coats the oxide layer；
Remove the polysilicon of side of the N-type epitaxy layer away from the heavily doped P-type substrate；
Remove the oxide of side of the N-type epitaxy layer away from the heavily doped P-type substrate.
2. heavily doped P-type substrate back sealing process method according to claim 1, it is characterised in that the oxide layer is used
Boiler tube atmospheric pressure oxidation method is formed.
3. heavily doped P-type substrate back sealing process method according to claim 2, it is characterised in that the boiler tube normobaric oxygen
The temperature of change method is 750 DEG C~1100 DEG C, and the time of oxidation is 60min~180min.
4. heavily doped P-type substrate back sealing process method according to claim 1, it is characterised in that the thickness of the oxide layer
Spend for 8000 angstroms~13000 angstroms.
5. heavily doped P-type substrate back sealing process method according to claim 1, it is characterised in that the polysilicon layer is adopted
Formed with low-pressure chemical vapor phase deposition method.
6. heavily doped P-type substrate back sealing process method according to claim 5, it is characterised in that the low pressure chemical gas
The source of the gas of phase sedimentation is SiH4。
7. heavily doped P-type substrate back sealing process method according to claim 1, it is characterised in that the polysilicon layer
Thickness is 6000 angstroms~12000 angstroms.
8. heavily doped P-type substrate back sealing process method according to claim 1, it is characterised in that the removal N-type
In the operation of the polysilicon of side of the epitaxial layer away from the heavily doped P-type substrate, the polysilicon is removed using dry etching.
9. heavily doped P-type substrate back sealing process method according to claim 8, it is characterised in that dry etching can be
Plasma etch process.
10. heavily doped P-type substrate back sealing process method according to claim 1, it is characterised in that the removal N
In the operation of the oxide of side of the type epitaxial layer away from the heavily doped P-type substrate, the oxidation is removed using wet etching
Thing.
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| CN107256837B (en) * | 2017-07-19 | 2020-01-07 | 河北普兴电子科技股份有限公司 | Method for measuring resistivity of epitaxial wafer based on super back-sealed substrate |
| US10741638B2 (en) * | 2018-08-08 | 2020-08-11 | Infineon Technologies Austria Ag | Oxygen inserted Si-layers for reduced substrate dopant outdiffusion in power devices |
| CN111933692B (en) * | 2020-10-12 | 2021-02-09 | 晶芯成(北京)科技有限公司 | Wafer back sealing structure and manufacturing method thereof |
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| KR101102771B1 (en) * | 2008-12-24 | 2012-01-05 | 매그나칩 반도체 유한회사 | Epitaxial wafer and method for manufacturing the same |
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