CN104851792A - Passivation processing method - Google Patents
Passivation processing method Download PDFInfo
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- CN104851792A CN104851792A CN201410052085.8A CN201410052085A CN104851792A CN 104851792 A CN104851792 A CN 104851792A CN 201410052085 A CN201410052085 A CN 201410052085A CN 104851792 A CN104851792 A CN 104851792A
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Abstract
The invention provides a passivation processing method, and the method comprises the steps: employing acid solution to wash a silicon wafer; employing a thermal oxidation method to generate a silicon oxide layer on the silicon wafer in an oxidation furnace; and generating a semi-insulating polycrystalline silicon layer on the silicon oxide layer, wherein the oxygen content of the semi-insulating polycrystalline silicon layer is greater than or equal to 2%, and is also less than or equal to 35%. The method effectively improves the uniformity of the oxygen content of the semi-insulating polycrystalline silicon layer, reduces the defects and impurity density of a silicon face, can effectively reduce the surface state density, and reduces the current leakage, thereby improving the reliability of a device.
Description
Technical field
The present invention relates to semiconductor chip fabrication process technology, particularly relate to a kind of processing method of passivation.
Background technology
Because the surface of device (i.e. silicon wafer) is not when having effective safeguard measure; very easily be subject to the impact of surrounding environment; the staining and reacting with surrounding chemical composition of impurity; thus the surperficial energy state that result in device changes; and then device electric property is changed, namely result in device performance stability and reliability is all deteriorated, therefore; in prior art, the main passivating technique that adopts increases passivation layer on the surface of device, to ensure device performance stability and reliability.
At present, passivating technique mainly adopts semi-insulating polysilicon thin film passivation material, increases passivation layer on the surface (i.e. silicon face) of device.Because semi-insulating polysilicon film is a kind of material mixing oxygen formation in polysilicon, it has semi-insulating character, close to electric neutrality, therefore, the passivation layer adopting semi-insulating polysilicon film to be formed effectively can reduce surface density of states, greatly reduce rain supply, ensure that device performance stability and reliability.
But, when the oxygen content fluctuation in semi-insulating polysilicon film is excessive, namely oxygen content is uneven, and/or the defect of above-mentioned silicon face (namely silicon face has hole or protruding) and impurity density increase time, the half insulation qualitative change of semi-insulating polysilicon film all can be caused poor, thus make the fixed charge in the passivation layer using this semi-insulating polysilicon film to be formed can form accumulation layer or the inversion layer of electronics on the surface of device, and then affect the surface electric field distribution of device, namely cause device performance stability and less reliable.
Summary of the invention
The invention provides a kind of processing method of passivation, for reducing surface density of states, reducing leakage current, and improving the reliability of device.
First aspect of the present invention is to provide a kind of processing method of passivation, comprising:
Adopt acid solution cleaning silicon wafer;
In oxidation furnace, thermal oxidation process is adopted to generate silicon oxide layer on described silicon wafer;
Described silicon oxide layer generates semi-insulating polysilicon layer;
Wherein, the oxygen content in described semi-insulating polysilicon is more than or equal to 2%, and is less than or equal to 35%.
Technique effect of the present invention is: by adopting acid solution cleaning silicon wafer, and in oxidation furnace, thermal oxidation process is adopted to generate silicon oxide layer on this silicon wafer, then on this silicon oxide layer, semi-insulating polysilicon layer is generated, wherein, oxygen content in this semi-insulating polysilicon is more than or equal to 2%, and is less than or equal to 35%.Silicon oxide layer is generated on silicon as the transition zone generating semi-insulating polysilicon layer owing to adopting thermal oxidation process in oxidation furnace, therefore, effectively improve the uniformity of semi-insulating polysilicon layer oxygen content, decrease the defect and impurity density of silicon face, thus effectively can reduce surface density of states, reduce leakage current, and then improve the reliability of device.
Accompanying drawing explanation
Fig. 1 is the flow chart of an embodiment of the processing method of passivation of the present invention;
Fig. 2 is the flow chart of another embodiment of the processing method of passivation of the present invention;
Fig. 3 is the flow chart of another embodiment of the processing method of passivation of the present invention.
Embodiment
Fig. 1 is the flow chart of an embodiment of the processing method of passivation of the present invention, and as shown in Figure 1, the method for the present embodiment comprises:
Step 101, employing acid solution cleaning silicon wafer.
In the present embodiment, the type of this silicon wafer comprises N-type silicon substrate and P-type silicon substrate.In addition, alternatively, the type of this silicon wafer also comprises the epitaxial wafer growing one or more layers silicon thin film on a silicon substrate.
Preferably, this acid solution comprises one or several combination following: the acid of sulfuric acid, nitric acid and hydrogen fluorine (HF).
Step 102, in oxidation furnace, adopt thermal oxidation process on this silicon wafer, generate silicon oxide layer.
In the present embodiment, after the acid solution adopted in step 101 and hydrofluoric acid solution are to silicon wafer cleaning, the silicon wafer after cleaning is put in oxidation furnace, and in this oxidation furnace, adopt thermal oxidation process to generate silicon oxide layer on this silicon wafer.
Step 103, on this silicon oxide layer, generate semi-insulating polysilicon layer; Wherein, the oxygen content in this semi-insulating polysilicon is more than or equal to 2%, and is less than or equal to 35%.
In the present embodiment, by adopting acid solution cleaning silicon wafer, and in oxidation furnace, thermal oxidation process is adopted to generate silicon oxide layer on this silicon wafer, then on this silicon oxide layer, semi-insulating polysilicon layer is generated, wherein, the oxygen content in this semi-insulating polysilicon is more than or equal to 2%, and is less than or equal to 35%.Silicon oxide layer is generated on silicon as the transition zone generating semi-insulating polysilicon layer owing to adopting thermal oxidation process in oxidation furnace, therefore, effectively improve the uniformity of semi-insulating polysilicon layer oxygen content, decrease the defect and impurity density of silicon face, thus effectively can reduce surface density of states, reduce leakage current, and then improve the reliability of device.
Fig. 2 is the flow chart of another embodiment of the processing method of passivation of the present invention, and on above-mentioned basis embodiment illustrated in fig. 1, as shown in Figure 2, a kind of specific implementation of step 102 is:
Step 201, in this oxidation furnace, be filled with protective gas, with by the temperature in this oxidation furnace to annealing temperature, and keep this annealing temperature to carry out annealing in process to this silicon wafer.
In the present embodiment, preferably, this protective gas comprises: gaseous inert gas, ammonia and hydrogen.Wherein, this inert gas comprises argon gas and nitrogen.
More preferably, the gas flow ratio scope of this inert gas and hydrogen is 10:1 to 2:1; The gas flow ratio scope of this ammonia and this hydrogen is 1:1 to 2:1.
More preferably, the range of flow of this protective gas is 0.1 liter/min to 20 liters/min.
Step 202, in this oxidation furnace, be filled with oxygen, so that the temperature in this oxidation furnace is warmed up to oxidizing temperature by this annealing temperature, and keep this oxidizing temperature to carry out thermal oxidation to this silicon wafer, make this silicon wafer generates this silicon oxide layer.
In the present embodiment, preferably, this annealing temperature is more than or equal to 700 DEG C, and is less than or equal to 950 DEG C; This oxidizing temperature is more than or equal to 800 DEG C, and is less than or equal to 1200 DEG C.
Step 203, in this oxidation furnace, be filled with inert gas, so that the temperature of this silicon wafer is cooled to room temperature by this oxidizing temperature.
In the present embodiment, preferably, in this thermal oxidation process, air pressure is more than or equal to 0.5bar, and is less than or equal to 1bar, i.e. in oxidizing process in intensification in step 201, the annealing in step 202 and step 202, air pressure range is in 0.5bar to 1bar.
In the present embodiment, by before generation semi-insulating polysilicon layer, add the process that thermal oxidation process generates silicon oxide layer, namely in oxidation furnace, protective gas is filled with, with by the temperature in this oxidation furnace to annealing temperature, and keep this annealing temperature to carry out annealing in process to this silicon wafer, oxygen is filled with again in this oxidation furnace, so that the temperature in this oxidation furnace is warmed up to oxidizing temperature by annealing temperature, and keep this oxidizing temperature to carry out thermal oxidation to this silicon wafer, make this silicon wafer generates this silicon oxide layer, finally in oxidation furnace, be filled with inert gas, so that the temperature of this silicon wafer is cooled to room temperature by this oxidizing temperature, thus decrease the defect and impurity density of silicon face, and improve the uniformity of semi-insulating polysilicon oxygen content.
Fig. 3 is the flow chart of another embodiment of the processing method of passivation of the present invention, and on above-mentioned basis embodiment illustrated in fig. 1, as shown in Figure 3, after step 103, the method can also comprise:
Step 104, using plasma strengthen chemical vapour deposition technique (Plasma Enhanced ChemicalVapor Deposition; PECVD) or low-pressure chemical vapour deposition technique (Low PressureChemical Vapor Deposition be called for short:; Be called for short: method LPCVD) generates silicon oxide layer on this semi-insulating polysilicon layer, and generates silicon nitride layer on this silicon oxide layer.
Preferably, a kind of specific implementation of step 103 is:
The method of step 301, employing PECVD or LPCVD generates semi-insulating polysilicon layer on this silicon oxide layer; Wherein, the oxygen content in this semi-insulating polysilicon is more than or equal to 2%, and is less than or equal to 35%.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (11)
1. a processing method for passivation, is characterized in that, comprising:
Adopt acid solution cleaning silicon wafer;
In oxidation furnace, thermal oxidation process is adopted to generate silicon oxide layer on described silicon wafer;
Described silicon oxide layer generates semi-insulating polysilicon layer;
Wherein, the oxygen content in described semi-insulating polysilicon is more than or equal to 2%, and is less than or equal to 35%.
2. method according to claim 1, is characterized in that, described in oxidation furnace, adopts thermal oxidation process to generate silicon oxide layer on described silicon wafer, comprising:
In described oxidation furnace, be filled with protective gas, with by the temperature in described oxidation furnace to annealing temperature, and keep described annealing temperature to carry out annealing in process to described silicon wafer;
In described oxidation furnace, be filled with oxygen, so that the temperature in described oxidation furnace is warmed up to oxidizing temperature by described annealing temperature, and keep described oxidizing temperature to carry out thermal oxidation to described silicon wafer, make described silicon wafer generates described silicon oxide layer;
Inert gas is filled with, so that the temperature of described silicon wafer is cooled to room temperature by described oxidizing temperature in described oxidation furnace.
3. method according to claim 1 and 2, is characterized in that, also comprises:
Adopt the method for low-pressure chemical vapour deposition technique or low-pressure chemical vapour deposition technique to generate silicon oxide layer on described semi-insulating polysilicon layer, and generate silicon nitride layer on described silicon oxide layer.
4. method according to claim 1, is characterized in that, described acid solution comprises one or several combination following: sulfuric acid, nitric acid and hydrofluoric acid.
5. method according to claim 2, is characterized in that, described protective gas comprises: inert gas, ammonia and hydrogen; Described inert gas comprises argon gas and nitrogen.
6. method according to claim 5, is characterized in that, the gas flow ratio scope of described inert gas and described hydrogen is 10:1 to 2:1; The gas flow ratio scope of described ammonia and described hydrogen is 1:1 to 2:1.
7. the method according to claim 2 or 5, is characterized in that, the range of flow of described protective gas is 0.1 liter/min to 20 liters/min.
8. method according to claim 2, is characterized in that, the described oxidizing temperature of described maintenance carries out thermal oxidation to described silicon wafer, comprising:
Described oxidizing temperature is kept to carry out dry-oxygen oxidation or wet-oxygen oxidation process to described silicon wafer.
9. method according to claim 2, is characterized in that, described annealing temperature is more than or equal to 700 DEG C, and is less than or equal to 950 DEG C; Described oxidizing temperature is more than or equal to 800 DEG C, and is less than or equal to 1200 DEG C.
10. method according to claim 1, is characterized in that, in described thermal oxidation process, air pressure is more than or equal to 0.5bar, and is less than or equal to 1bar.
11. methods according to claim 1, is characterized in that, describedly on described silicon oxide layer, generate semi-insulating polysilicon layer, comprising:
The method of PECVD or LPCVD is adopted to generate semi-insulating polysilicon layer on described silicon oxide layer.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110690319A (en) * | 2019-08-30 | 2020-01-14 | 江苏顺风新能源科技有限公司 | Oxidation annealing process of high-efficiency monocrystalline silicon battery |
Citations (3)
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| CN101521223A (en) * | 2008-11-19 | 2009-09-02 | 深圳深爱半导体有限公司 | Surface passivation structure of bipolar transistor and manufacturing method |
| US20120009797A1 (en) * | 2009-04-21 | 2012-01-12 | Patrick Reynaud | Method to thin a silicon-on-insulator substrate |
| CN103035732A (en) * | 2012-12-17 | 2013-04-10 | 华南理工大学 | VDMOS transistor and preparation method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521223A (en) * | 2008-11-19 | 2009-09-02 | 深圳深爱半导体有限公司 | Surface passivation structure of bipolar transistor and manufacturing method |
| US20120009797A1 (en) * | 2009-04-21 | 2012-01-12 | Patrick Reynaud | Method to thin a silicon-on-insulator substrate |
| CN103035732A (en) * | 2012-12-17 | 2013-04-10 | 华南理工大学 | VDMOS transistor and preparation method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110690319A (en) * | 2019-08-30 | 2020-01-14 | 江苏顺风新能源科技有限公司 | Oxidation annealing process of high-efficiency monocrystalline silicon battery |
| CN110690319B (en) * | 2019-08-30 | 2021-06-25 | 江苏顺风新能源科技有限公司 | Oxidation annealing process of high-efficiency monocrystalline silicon battery |
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Effective date of registration: 20220718 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District, Cheng Fu Road, No. 298, Zhongguancun Fangzheng building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |
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