CN102376752A - Substrate for epitaxial wafer, epitaxial wafer and semiconductor device - Google Patents
Substrate for epitaxial wafer, epitaxial wafer and semiconductor device Download PDFInfo
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- CN102376752A CN102376752A CN2011102956410A CN201110295641A CN102376752A CN 102376752 A CN102376752 A CN 102376752A CN 2011102956410 A CN2011102956410 A CN 2011102956410A CN 201110295641 A CN201110295641 A CN 201110295641A CN 102376752 A CN102376752 A CN 102376752A
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Abstract
The invention discloses a substrate for an epitaxial wafer, comprising a substrate body. The substrate for the epitaxial wafer is characterized in that a silicon dioxide layer is arranged at the back of the substrate body, and a polycrystalline silicon layer is arranged on the surface of the silicon dioxide layer. the substrate for the epitaxial wafer provided by the invention has the advantages that the number of monocrystalline silicon particles and the surface metal concentration can be reduced, and the yield of the epitaxial wafer can be increased. By using the substrate back-sealed by the silicon dioxide layer, monocrystalline silicon monocrystalline particles can generate in the epitaxial layer growing process, and the monocrystalline silicon particles are produced by reducing the silicon dioxide layer by hydrogen gas, which is much associated with the compactness of the back sealing layer; and therefore, in the technical scheme of the invention, a layer of polycrystalline silicon is arranged on the surface of the silicon dioxide layer, thereby reducing the monocrystalline silicon particles.
Description
Technical field
The present invention relates to a kind of epitaxial wafer with substrate, epitaxial wafer and semiconductor device.
Background technology
For semiconductor device, need epitaxial loayer to have perfect crystal structure, and all there is certain requirement the aspects such as thickness, conduction type, resistivity and resistance uniformity of epitaxial loayer.Semi-conductive resistivity generally changes along with the variation of factors such as temperature, doping content, magnetic field intensity and intensity of illumination.
Substrate is also referred to as substrate.In the outer layer growth process, especially back of the body envelope adopts the substrate of silicon dioxide layer, can produce the monocrystalline silicon particle.The monocrystalline silicon particle can influence the quality of epitaxial wafer.The monocrystalline silicon particle is many more, and then the epitaxial wafer quality is low more.The factor that another one influences the epitaxial wafer quality is a surface metal concentration.Surface metal concentration is high more, and the epitaxial wafer quality is low more.Substrate of the prior art all too much influences the finished product rate because of the monocrystalline silicon particle.
Summary of the invention
The objective of the invention is in order to overcome deficiency of the prior art, provide a kind of epitaxial wafer that improves rate of finished products to use substrate.
For realizing above purpose, the present invention realizes through following technical scheme:
Epitaxial wafer is used substrate, comprises substrate bulk, it is characterized in that, the said substrate bulk back side is provided with silicon dioxide layer, is provided with polysilicon layer at the silicon dioxide laminar surface.
Preferably, described silicon dioxide layer thickness is 3-7um.
Preferably, described polysilicon layer thickness is 6-10um.
Preferably, described substrate bulk is the N type.
Preferably, described N type substrate bulk is doped with at least a element in arsenic, phosphorus and the antimony.
Preferably, described substrate bulk is the P type.
Preferably, described P type substrate bulk is doped with boron.
Second purpose of the present invention provides the high epitaxial wafer of a kind of epilayer resistance uniformity.
Epitaxial wafer is characterized in that, comprises that aforementioned epitaxial wafer uses substrate.
The 3rd purpose of the present invention provides a kind of semiconductor device.
Semiconductor device is characterized in that, comprises aforesaid epitaxial wafer.
Advantage of the present invention is to reduce monocrystalline silicon amounts of particles and surface metal concentration, can improve the rate of finished products of epitaxial wafer.Use is provided with the substrate of silicon dioxide layer back of the body envelope, can produce the monocrystalline silicon particle in the outer layer growth process.The monocrystalline silicon particle is that silicon dioxide layer is produced by hydrogen reducing, with the back of the body seal compactness much relations is arranged.Therefore, among the present invention, one deck polysilicon is set, can reduces the monocrystalline silicon particle at the silicon dioxide laminar surface.
Description of drawings
Fig. 1 uses the substrat structure sketch map for the epitaxial wafer among the embodiment 1-4 among the present invention.
Fig. 2 is the epitaxial slice structure sketch map of embodiments of the invention 5-8.
Embodiment
Below in conjunction with embodiment the present invention is carried out detailed description:
Embodiment 1-4
Fig. 1 is that the epitaxial wafer in the present embodiment is used the substrat structure sketch map.As shown in Figure 1, epitaxial wafer is used substrate, comprises substrate bulk 1, and substrate bulk 1 both can be the N type, promptly was doped with arsenic, phosphorus or antimony element; Described substrate bulk 1 can also be the P type, promptly is doped with boron element.Be provided with silicon dioxide layer 2 at substrate bulk 1 back side.Silicon dioxide layer 2 surfaces are provided with polysilicon layer 3.
Embodiment 1-4 is heavily doped arsenic substrate bulk, and the substrate bulk back side among the embodiment 1-4 is provided with thickness and is respectively 3um, 4.2um, 5.9, um7um silicon dioxide layer; Thickness is respectively 6.2um, 7.7um, 8.5um, 9.8um polysilicon layer.
The technology of deposition of silica layer, polysilicon layer existing techniques in realizing all capable of using.
Embodiment 5-8
Fig. 2 is the epitaxial slice structure sketch map among the embodiment 5-8.As shown in Figure 2, embodiment 5-8 is for using the epitaxial wafer of the substrate production among the embodiment 1-4 respectively, and its structure comprises substrate shown in Figure 1, at substrate bulk 1 front grown epitaxial layer 4.Said substrate comprises substrate bulk 1, is provided with silicon dioxide layer 2 at substrate bulk 1 back side.Silicon dioxide layer 2 surfaces are provided with polysilicon layer 3.Epitaxial loayer 4 is arranged on substrate bulk 1 front.
Among the comparative example 1-4, at the substrate bulk back side silicon dioxide layer and polysilicon layer are not set, the positive growth of the direct substrate bulk of epitaxial loayer forms.
The epitaxial wafer monocrystalline silicon particle area correction data of embodiment 5-8 and comparative example 1-4 is as shown in table 1.
Table 1: the monocrystalline silicon particle accounts for the epitaxial wafer area percentage
Use the substrate among the embodiment 2, the epitaxial wafer surface metal concentration determination data of production are shown in table 2-5.
Table 2, heavily doped phosphorus substrate bulk.The E+10/cm of ionic activity unit
2
Table 3 is gently mixed the phosphorus substrate bulk.The E+10/cm of ionic activity unit
2
Table 4, heavily doped boron substrate bulk.The E+10/cm of ionic activity unit
2
Table 5, light boron-doping substrate bulk.The E+10/cm of ionic activity unit
2
Can find out that from above data the substrate among the present invention can improve epi-layer surface tenor concentration.It is that heavy doping or light dope influence that its beneficial effect can't receive substrate bulk.
Embodiment among the present invention only is used for that the present invention will be described, does not constitute the restriction to the claim scope, and other substituting of being equal in fact that those skilled in that art can expect are all in protection range of the present invention.
Claims (9)
1. epitaxial wafer is used substrate, comprises substrate bulk, it is characterized in that, the said substrate bulk back side is provided with silicon dioxide layer, is provided with polysilicon layer at the silicon dioxide laminar surface.
2. epitaxial wafer according to claim 1 is used substrate, it is characterized in that, described silicon dioxide layer thickness is 3-7um.
3. epitaxial wafer according to claim 1 and 2 is used substrate, it is characterized in that, described polysilicon layer thickness is 6-10um.
4. epitaxial wafer according to claim 1 is used substrate, it is characterized in that, described substrate bulk is the N type.
5. epitaxial wafer according to claim 4 is used substrate, it is characterized in that, described N type substrate bulk is doped with at least a element in arsenic, phosphorus and the antimony.
6. epitaxial wafer according to claim 1 is used substrate, it is characterized in that, described substrate bulk is the P type.
7. epitaxial wafer according to claim 6 is used substrate, it is characterized in that, described P type substrate bulk is doped with boron.
8. epitaxial wafer is characterized in that, comprises that the described epitaxial wafer of the arbitrary claim of claim 1 to 7 uses substrate.
9. semiconductor device is characterized in that, comprises the described epitaxial wafer of claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102956410A CN102376752A (en) | 2011-09-30 | 2011-09-30 | Substrate for epitaxial wafer, epitaxial wafer and semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011102956410A CN102376752A (en) | 2011-09-30 | 2011-09-30 | Substrate for epitaxial wafer, epitaxial wafer and semiconductor device |
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| CN102376752A true CN102376752A (en) | 2012-03-14 |
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| CN2011102956410A Pending CN102376752A (en) | 2011-09-30 | 2011-09-30 | Substrate for epitaxial wafer, epitaxial wafer and semiconductor device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425248A (en) * | 2013-08-28 | 2015-03-18 | 无锡华润上华半导体有限公司 | Method for back sealing process of heavy doped P-type substrate |
| CN105702710A (en) * | 2016-01-29 | 2016-06-22 | 上海华虹宏力半导体制造有限公司 | A method for manufacturing a deep-groove type super junction device |
| CN107723797A (en) * | 2016-08-11 | 2018-02-23 | 北大方正集团有限公司 | The preparation method and silicon carbide whisker disk of silicon carbide whisker disk |
| CN108054082A (en) * | 2017-12-06 | 2018-05-18 | 上海华力微电子有限公司 | A kind of substrat structure of CIS and preparation method thereof |
| CN109037030A (en) * | 2018-07-04 | 2018-12-18 | 上海晶盟硅材料有限公司 | Improve preparation method, epitaxial wafer and the semiconductor devices of the epitaxial wafer of back side silicon single crystal |
| CN113496869A (en) * | 2020-04-03 | 2021-10-12 | 重庆超硅半导体有限公司 | Back film layer of silicon wafer for epitaxial substrate and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101740525A (en) * | 2008-11-24 | 2010-06-16 | 合晶科技股份有限公司 | Encapsulation structure for wafer backside |
| CN202282351U (en) * | 2011-09-30 | 2012-06-20 | 上海晶盟硅材料有限公司 | Epitaxial wafer substrate, epitaxial wafer and semiconductor device |
-
2011
- 2011-09-30 CN CN2011102956410A patent/CN102376752A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101740525A (en) * | 2008-11-24 | 2010-06-16 | 合晶科技股份有限公司 | Encapsulation structure for wafer backside |
| CN202282351U (en) * | 2011-09-30 | 2012-06-20 | 上海晶盟硅材料有限公司 | Epitaxial wafer substrate, epitaxial wafer and semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425248A (en) * | 2013-08-28 | 2015-03-18 | 无锡华润上华半导体有限公司 | Method for back sealing process of heavy doped P-type substrate |
| CN105702710A (en) * | 2016-01-29 | 2016-06-22 | 上海华虹宏力半导体制造有限公司 | A method for manufacturing a deep-groove type super junction device |
| CN107723797A (en) * | 2016-08-11 | 2018-02-23 | 北大方正集团有限公司 | The preparation method and silicon carbide whisker disk of silicon carbide whisker disk |
| CN108054082A (en) * | 2017-12-06 | 2018-05-18 | 上海华力微电子有限公司 | A kind of substrat structure of CIS and preparation method thereof |
| CN109037030A (en) * | 2018-07-04 | 2018-12-18 | 上海晶盟硅材料有限公司 | Improve preparation method, epitaxial wafer and the semiconductor devices of the epitaxial wafer of back side silicon single crystal |
| CN113496869A (en) * | 2020-04-03 | 2021-10-12 | 重庆超硅半导体有限公司 | Back film layer of silicon wafer for epitaxial substrate and manufacturing method thereof |
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Application publication date: 20120314 |