CN109037030A - Improve preparation method, epitaxial wafer and the semiconductor devices of the epitaxial wafer of back side silicon single crystal - Google Patents

Improve preparation method, epitaxial wafer and the semiconductor devices of the epitaxial wafer of back side silicon single crystal Download PDF

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CN109037030A
CN109037030A CN201810722379.5A CN201810722379A CN109037030A CN 109037030 A CN109037030 A CN 109037030A CN 201810722379 A CN201810722379 A CN 201810722379A CN 109037030 A CN109037030 A CN 109037030A
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epitaxial wafer
back side
single crystal
silicon single
preparation
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CN109037030B (en
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高璇
陈建纲
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WAFER WORKS EPITAXIAL CORP
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

The invention discloses preparation method, epitaxial wafer and the semiconductor devices of a kind of epitaxial wafer for improving back side silicon single crystal, method is before outer layer growth, one layer of polysilicon is covered in carrying panel surface first, this layer of polysilicon gets up the clearance seal between epitaxial wafer dorsal edge and carrier, hydrogen when outer layer growth is set to cannot be introduced into epitaxial wafer dorsal edge, to reduce the silicon single crystal point at the epitaxial wafer back side.According to the epitaxial wafer that technical solution of the present invention produces, the growth of epitaxial wafer back side monocrystalline silicon point can be completely inhibited.

Description

Improve preparation method, epitaxial wafer and the semiconductor devices of the epitaxial wafer of back side silicon single crystal
Technical field
The present invention relates to preparation method, epitaxial wafer and the semiconductor devices of a kind of epitaxial wafer for improving back side silicon single crystal.
Background technique
For semiconductor devices, need epitaxial layer have perfect crystal structure, and to the thickness of epitaxial layer, lead Electric type, resistivity and resistance homogeneity etc. have certain requirement.In addition to this, more and more products are to epitaxial wafer The requirement at the back side is higher and higher, because of its lithography process for directly influencing later product, the epitaxial wafer back side has flaw to be easy to make The problem of at defocusing.Epitaxial wafer back side flaw is for example: epitaxial wafer back side silicon wafer point, scratch, color difference etc., after these are all directly affected Road IC processing procedure.
Since most extension flake products are determined by later product application, more and more circuits and electronic component need It completes in extension on piece, such as Power MOS, NMOS, CMOS and Super junction etc..With IC design Narrow towards line width, the development trend that lithography requirement is higher and higher, it is also constantly harsh for extension product requirement.Improve outer Prolong piece back seal structure, so that epitaxial wafer is more applicable for more rear road lithography process becomes main problem.
As shown in Figure 1, a kind of epitaxial wafer, due to substrate slice high-temperature heating during extension, edges of substrate carries on the back inside front cover oxygen SiClx is easy to react with hydrogen to be reduced into silicon single crystal, is pierced by silicon dioxide layer.
In addition, since back surface of the wafer edge is needed by acid corrosion, its chamfering and edge etch is clean, therefore, chip The thickness of dorsal edge silica can be corresponding thinning.Meanwhile chip high-temperature heating during extension, edge can slightly be stuck up Rising will not fit closely with carrier, and such reaction gas hydrogen, which will permeate into, is reduced into silicon with silicon dioxde reaction Monocrystalline.It is this how to avoid back surface of the wafer edge hydrogen especially in the production method of vapour phase epitaxy in epitaxial wafer production process Become the difficult point of epitaxial wafer production at silicon single crystal with silicon dioxde reaction.
Theoretically, normal epitaxial wafer production completion should be very smooth.But reality is all sticked up around chip, U-shaped structure is presented, if temperature control is bad, Waffer edge warpage is more, and epitaxial wafer back side silicon single crystal point situation can be more serious.
The situation at the epitaxial wafer back side is equally one of the important indicator of the epitaxial growth strength of enterprise, is that a kind of process capability is high Low measurement index.Therefore, improve epitaxial wafer back side silicon single crystal phenomenon to be a problem to be solved.
Summary of the invention
The present invention is in order to solve the above technical problems, provide the preparation method of a kind of epitaxial wafer for improving back side silicon single crystal, outer Prolong piece and semiconductor devices.
In order to achieve the above object, the invention is realized by the following technical scheme:
A kind of preparation method for the epitaxial wafer improving back side silicon single crystal before outer layer growth, is covered in carrying panel surface first One layer of polysilicon of lid.
An embodiment according to the present invention, the polysilicon of the described carrying panel surface covering it is micro- with a thickness of 0.5~1 Rice.
An embodiment according to the present invention, the substrate of the epitaxial wafer is n-type doping, overweight to mix.
An embodiment according to the present invention, the substrate N-type impurity atom are arsenic atom.
An embodiment according to the present invention, the doping concentration 1.2 × 10 of the arsenic atom19~2.2 × 1019。
An embodiment according to the present invention, the substrate are made for pulling of crystals autofrettage.
The back side setting layer of silicon dioxide of an embodiment according to the present invention, the substrate carries on the back envelope, titanium dioxide Silicon back envelope with a thickness of
An embodiment according to the present invention, the epitaxial layer of the epitaxial wafer is n-type doping, heavily doped.
An embodiment according to the present invention, the n-type doping have at least one of phosphorus, arsenic or antimony element.
An embodiment according to the present invention, the n-type doping atom are phosphorus atoms, the doping concentration 5 of phosphorus atoms ×1015~5.5 × 1015cm3。
An embodiment according to the present invention, the epitaxial layer are made for chemical vapor deposition.
A kind of epitaxial wafer, the epitaxial wafer are made by the above method.
An embodiment according to the present invention, the epitaxial layer of the epitaxial wafer with a thickness of 4~20 microns.
An embodiment according to the present invention, the epitaxial layer with a thickness of 7.5 microns.
A kind of semiconductor devices, including above-mentioned epitaxial wafer.
The present invention before epitaxial growth, first carrying panel surface cover one layer of polysilicon, by its back surface of the wafer edge with hold Clearance seal between load plate gets up, and so that its hydrogen is cannot be introduced into back surface of the wafer edge can tail off to silicon single crystal point, situation meeting Improved.The preferable epitaxial wafer in the back side can greatly increase the yield of device during subsequent technique, reduce process costs and Improve IC products quality.The epitaxial layer of epitaxial wafer with a thickness of 4~20 microns, be more than this thickness section, carrier Upper long polysilicon not can avoid the long polycrystalline point of back surface of the wafer yet.It, can be complete according to the epitaxial wafer that technical solution of the present invention produces Inhibit the growth of epitaxial wafer back side monocrystalline silicon point.
Detailed description of the invention
Fig. 1 is the schematic diagram of substrate back edge silicon single crystal in background technique；
Fig. 2 is the structural schematic diagram of epitaxial wafer；Wherein, 1- substrate, 2- silica back envelope, 3- epitaxial layer；
Fig. 3 is structural schematic diagram of the invention.
Specific embodiment
The present invention is described in detail with reference to the accompanying drawing:
Embodiment 1
As shown in figure 3, the present embodiment improves the preparation method of the epitaxial wafer of back side silicon single crystal, before outer layer growth, first One layer of polysilicon 5 is covered on 6 surface of carrier, this layer of polysilicon 5 is by the gap between 4 dorsal edge of epitaxial wafer and carrier 6 It seals, hydrogen when outer layer growth is made to cannot be introduced into 4 dorsal edge of epitaxial wafer, to reduce the silicon list at 4 back side of epitaxial wafer Crystal point.The polysilicon 5 with a thickness of 0.5 micron.
The substrate of the epitaxial wafer 4 is n-type doping, overweight to mix.The substrate N-type impurity atom is arsenic atom.Institute The doping concentration 1.2 × 10 for the arsenic atom stated19cm3.The substrate is made for pulling of crystals autofrettage.
As shown in Fig. 2, the substrate the back side setting layer of silicon dioxide carry on the back envelope, silica back envelope with a thickness of 4000A°。
The epitaxial layer of the epitaxial wafer 4 is n-type doping, heavily doped.The n-type doping has in phosphorus, arsenic or antimony at least A kind of element.The n-type doping atom is phosphorus atoms, the doping concentration 5 × 10 of phosphorus atoms15cm3.The epitaxial layer is to change Vapor deposition is learned to be made.
The epitaxial layer of the epitaxial wafer 4 with a thickness of 4 microns.
Embodiment 2
As shown in figure 3, the present embodiment improves the preparation method of the epitaxial wafer of back side silicon single crystal, before outer layer growth, first One layer of polysilicon 5 is covered on 6 surface of carrier, this layer of polysilicon 5 is by the gap between 4 dorsal edge of epitaxial wafer and carrier 6 It seals, hydrogen when outer layer growth is made to cannot be introduced into 4 dorsal edge of epitaxial wafer, to reduce the silicon list at 4 back side of epitaxial wafer Crystal point.The polysilicon 5 with a thickness of 1 micron.
The substrate of the epitaxial wafer 4 is n-type doping, overweight to mix.The substrate N-type impurity atom is arsenic atom.Institute The doping concentration 2.2 × 10 for the arsenic atom stated19cm3.The substrate is made for pulling of crystals autofrettage.
As shown in Fig. 2, the substrate the back side setting layer of silicon dioxide carry on the back envelope, silica back envelope with a thickness of 5000A°。
The epitaxial layer of the epitaxial wafer 4 is n-type doping, heavily doped.The n-type doping has in phosphorus, arsenic or antimony at least A kind of element.The n-type doping atom is phosphorus atoms, the doping concentration 5.5 × 10 of phosphorus atoms15cm3.The epitaxial layer is Chemical vapor deposition is made.
The epitaxial layer of the epitaxial wafer 4 with a thickness of 20 microns.
Embodiment 3
As shown in figure 3, the present embodiment improves the preparation method of the epitaxial wafer of back side silicon single crystal, before outer layer growth, first One layer of polysilicon 5 is covered on 6 surface of carrier, this layer of polysilicon 5 is by the gap between 4 dorsal edge of epitaxial wafer and carrier 6 It seals, hydrogen when outer layer growth is made to cannot be introduced into 4 dorsal edge of epitaxial wafer, to reduce the silicon list at 4 back side of epitaxial wafer Crystal point.The polysilicon 5 with a thickness of 0.7 micron.
The substrate of the epitaxial wafer 4 is n-type doping, overweight to mix.The substrate N-type impurity atom is arsenic atom.Institute The doping concentration 2.0 × 10 for the arsenic atom stated19cm3.The substrate is made for pulling of crystals autofrettage.
As shown in Fig. 2, the substrate the back side setting layer of silicon dioxide carry on the back envelope, silica back envelope with a thickness of 4500A°。
The epitaxial layer of the epitaxial wafer 4 is n-type doping, heavily doped.The n-type doping has in phosphorus, arsenic or antimony at least A kind of element.The n-type doping atom is phosphorus atoms, the doping concentration 5.25 × 10 of phosphorus atoms15cm3.The epitaxial layer It is made for chemical vapor deposition.
The epitaxial layer of the epitaxial wafer 4 with a thickness of 7.5 microns.
Table 1 is the thickness value of the epitaxial layer of epitaxial wafer, takes five samples, and each value of each sample nine times is simultaneously averaged Value, takes five samples, and each value of each sample nine times is simultaneously averaged, and uniformity refers to value five times calculating on wafer epitaxial layer Uniformity, formula: (maximum-minimum)/(maximum+minimum):
Epitaxial wafer 1 2 3 4 5 6 7 8 9 Average value Uniformity
1 7.564 7.577 7.552 7.530 7.589 7.664 7.532 7.630 7.571 7.579 0.88%
2 7.414 7.538 7.531 7.468 7.494 7.556 7.499 7.533 7.482 7.502 0.95%
3 7.535 7.548 7.502 7.441 7.473 7.514 7.463 7.513 7.473 7.496 0.71%
4 7.500 7.537 7.499 7.447 7.474 7.508 7.465 7.514 7.477 7.491 0.60%
5 7.559 7.580 7.590 7.686 7.594 7.593 7.549 7.569 7.574 7.588 0.90%
Table 2 is the resistivity (from doping concentration conversion) of the epitaxial layer of epitaxial wafer, takes five samples, each sample is each Value nine times is simultaneously averaged:
Above-mentioned two table shows fine according to epitaxy layer thickness manufactured in the present embodiment and resistance value uniformity.
Table 3 show the growing polycrystalline silicon 5 on carrier 6, and thicker 4 back side silicon single crystal point of epitaxial wafer of 5 thickness of polysilicon is more It is few slighter.Without polysilicon 5, silicon single crystal point in the back side is gathered in apart from 5~10mm of Waffer edge, and whole circle is very fine and close；Long 0.5 is micro- Rice polysilicon 5, silicon single crystal point in the back side is gathered in apart from 1~3m of Waffer edge, almost invisible；Long 1 micron of polysilicon 5, the back side Silicon single crystal point is not generally visible.
Table 3
Embodiment 4
The present embodiment semiconductor devices, including the epitaxial wafer 4 prepared by embodiment 1,2 or 3.
Embodiment in the present invention is only used for that the present invention will be described, and is not construed as limiting the scope of claims limitation, Other substantially equivalent substitutions that those skilled in that art are contemplated that, all fall in the scope of protection of the present invention.

Claims (15)

1. a kind of preparation method for the epitaxial wafer for improving back side silicon single crystal, which is characterized in that before outer layer growth, carrying first Panel surface covers one layer of polysilicon.
2. the preparation method of the epitaxial wafer according to claim 1 for improving back side silicon single crystal, which is characterized in that described holds Load plate surface covering polysilicon with a thickness of 0.5~1 micron.
3. the preparation method of the epitaxial wafer according to claim 1 for improving back side silicon single crystal, which is characterized in that described is outer The substrate for prolonging piece is n-type doping, overweight to mix.
4. the preparation method of the epitaxial wafer according to claim 3 for improving back side silicon single crystal, which is characterized in that the lining Bottom N-type impurity atom is arsenic atom.
5. the preparation method of the epitaxial wafer according to claim 4 for improving back side silicon single crystal, which is characterized in that the arsenic The doping concentration 1.2 × 10 of atom19~2.2 × 1019cm3。
6. improving the preparation method of the epitaxial wafer of back side silicon single crystal according to claim 3,4 or 5, which is characterized in that institute The substrate stated is made for pulling of crystals autofrettage.
7. the preparation method of the epitaxial wafer according to claim 6 for improving back side silicon single crystal, which is characterized in that the lining Bottom the back side setting layer of silicon dioxide carry on the back envelope, silica back envelope with a thickness of
8. the preparation method of the epitaxial wafer according to claim 1 for improving back side silicon single crystal, which is characterized in that described is outer The epitaxial layer for prolonging piece is n-type doping, heavily doped.
9. the preparation method of the epitaxial wafer according to claim 8 for improving back side silicon single crystal, which is characterized in that the N Type is doped at least one of phosphorus, arsenic or antimony element.
10. the preparation method of the epitaxial wafer according to claim 9 for improving back side silicon single crystal, which is characterized in that the N Type foreign atom is phosphorus atoms, the doping concentration 5 × 10 of phosphorus atoms15~5.5 × 1015cm3。
11. improving the preparation method of the epitaxial wafer of back side silicon single crystal according to claim 8,9 or 10, which is characterized in that The epitaxial layer is made for chemical vapor deposition.
12. a kind of epitaxial wafer, which is characterized in that the epitaxial wafer is made by the described in any item methods of claim 1-11.
13. epitaxial wafer according to claim 12, which is characterized in that the epitaxial layer of the epitaxial wafer with a thickness of 4~ 20 microns.
14. epitaxial wafer according to claim 13, which is characterized in that the epitaxial layer with a thickness of 7.5 microns.
15. a kind of semiconductor devices, which is characterized in that including the described in any item epitaxial wafers of claim 12-14.
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