CN105070647A - Epitaxial wafer, preparation method thereof and semiconductor device - Google Patents

Epitaxial wafer, preparation method thereof and semiconductor device Download PDF

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CN105070647A
CN105070647A CN201510448219.2A CN201510448219A CN105070647A CN 105070647 A CN105070647 A CN 105070647A CN 201510448219 A CN201510448219 A CN 201510448219A CN 105070647 A CN105070647 A CN 105070647A
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epitaxial
doping
substrate
type
epitaxial wafer
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CN105070647B (en
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高璇
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WAFER WORKS EPITAXIAL CORP
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers

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Abstract

The invention discloses an epitaxial wafer. The epitaxial wafer is characterized by comprising a substrate and an epitaxial layer; and the doping type of the substrate is different from that of the epitaxial layer, namely, the substrate includes P type doping and the epitaxial layer includes N type doping, or the substrate includes N type doping and the epitaxial layer includes P type doping. The warpage degree of the epitaxial wafer satisfies production requirements of follow-up devices, an integrated circuit manufacturer is effectively avoided from defocusing in exposure, the yield and product quality of the follow-up devices are improved, and strict requirements for epitaxial products in products, including mobile communication units and information household electrical appliance, can be better met.

Description

Epitaxial wafer, epitaxial wafer preparation method and semiconductor device
Technical field
The present invention relates to a kind of epitaxial wafer and preparation method thereof, and a kind of semiconductor device comprising this kind of epitaxial wafer.
Background technology
Have certain requirements at Grown one deck, the single crystalline layer identical with Substrate orientation (i.e. epitaxial loayer), stretched out one section just as original crystal, thus claim epitaxial growth.For semiconductor device, need the epitaxial loayer of epitaxial wafer to have perfect crystal structure, and all have certain requirement to the thickness of epitaxial loayer, conduction type, the aspect such as resistivity and resistance homogeneity.In addition, the requirement of increasing product to epitaxial wafer geometric parameter is more and more higher, because epitaxial wafer geometric parameter directly has influence on the processing of rear road product.Such as: the warped degree of epitaxial wafer is higher than 60 μm, and integrated circuit suppliers can be caused to expose processing and defocus, yield is low, and the warped degree of epitaxial wafer is larger, defocuses more serious, produces yield lower.The computing formula of the warped degree of epitaxial wafer is as follows: warped degree=(a-b)/2.As shown in Figure 1, the distance in epitaxial wafer 01 intermediate interface 011 between distance reference face 02 point farthest and the plane of reference 02 is a.As shown in Figure 2, overturn by the epitaxial wafer 01 in Fig. 1, the distance between the point that in epitaxial wafer 01 intermediate interface 011, distance reference face 02 is nearest and the plane of reference 02 is b.
The application of rear road device determines, and increasing circuit and electronic component need to complete on epitaxial wafer, such as PowerMOSFET, NMOS, CMOS and Superjunction etc.Along with integrated circuit (IC) design is towards development trend that is light, thin, short, little and power saving, the product such as Mobile Communications, information household appliances is effected the greatest economy energy resource consumption invariably, also constantly harsh for extension product requirement.Therefore, improve epitaxial wafer geometric parameter, make epitaxial wafer be more applicable for Geng Duohou road IC factory be processed in order to epitaxial wafer make subject matter.
Epitaxial wafer is made up of the main body of substrate and epitaxial loayer, and element is identical, is silicon.Existing epitaxial wafer, usually adopts and mixes foreign atom to improve electric conductivity, but substrate must be identical with the doping type of epitaxial loayer, is namely all the doping of P type or is all N-type doping.Because as shown in Figure 3, if substrate 1 is different with the doping type of epitaxial loayer 2, the atom of substrate and the interior doping of epitaxial loayer varies in size, and interface 3 can produce dislocation, and this dislocation can produce pulling force and cause epitaxial wafer to be out of shape, and forms epitaxial wafer 01 as shown in Figure 4.In Fig. 4, the edge of epitaxial wafer 01 tilts, and presents bowl-shape time serious, and warped degree is up to 80 μm, and cause integrated circuit suppliers to expose processing and seriously defocus, yield is extremely low.Therefore, the satisfactory epitaxial wafer of existing warped degree is the epitaxial wafer that substrate and epitaxial loayer are all the doping of P type or are all N-type doping.
Summary of the invention
The object of the invention is to overcome deficiency of the prior art, a kind of epitaxial wafer of low warped degree is provided.
For realizing above object, the present invention is achieved through the following technical solutions:
Epitaxial wafer, is characterized in that, comprises substrate and epitaxial loayer; Described substrate is different with the doping type of described epitaxial loayer; Described substrate is the doping of P type, and described epitaxial loayer is N-type doping; Or described substrate is N-type doping, described epitaxial loayer is the doping of P type.
Preferably, the atom that described P type adulterates is boron atom.
Preferably, the doping type of described boron atom is overweight mixing, and doping content is 9*e 18~ 1*e 20individual/cm 3.
Preferably, the concentration of described boron atom is 4.5*e 19~ 5.5*e 19individual/cm 3.
Preferably, the foreign atom of described N-type doping is the one or several arbitrarily in phosphorus atoms, arsenic atom, antimony atoms.
Preferably, the doping type of described phosphorus atoms is heavily doped, and doping content is 8*e 16~ 2*e 17individual/cm 3.
Preferably, the thickness of described epitaxial loayer is 1.5 ~ 150 μm.
Preferably, the thickness of described epitaxial loayer is 18 ~ 50 μm.
Preferably, thickness is 645 ~ 675 μm or 745 ~ 775 μm.
Two of object of the present invention is to overcome deficiency of the prior art, provides a kind of manufacture method of above-mentioned epitaxial wafer.
For realizing above object, the present invention is achieved through the following technical solutions:
The manufacture method of above-mentioned epitaxial wafer, is characterized in that, comprises the steps:
A., one substrate is provided; Doping treatment is carried out to substrate, makes described substrate form the doping of P type or N-type doping;
B. grown epitaxial layer over the substrate; Doping treatment is carried out to described epitaxial loayer, makes described epitaxial loayer form the doping of P type or N-type doping;
C. after having adulterated, carry out high-temperature baking to described substrate and described epitaxial loayer, baking temperature is 1100 ~ 1120 DEG C, and baking time is 20 ~ 50s.
Preferably, described substrate adopts CZ method to be made.
Preferably, the grown epitaxial layer in described step B carries out in one chip epitaxial furnace; Be normal pressure in described one chip epitaxial furnace.
Preferably, in described step B, the method for chemical vapour deposition (CVD) is adopted to grow described epitaxial loayer; Chemical vapour deposition (CVD) comprises the steps: to utilize trichlorosilane and hydrogen to react under the hot environment of 1040 ~ 1200 DEG C, makes described substrate generates described epitaxial loayer.
Preferably, in described step B, trichlorosilane and hydrogen reaction, with while making epitaxial loayer described in described Grown, carry out doping treatment to described epitaxial loayer.
Preferably, after described step B completes, the temperature in described one chip epitaxial furnace is risen to 1100 ~ 1200 DEG C, in one chip epitaxial furnace, carries out described step C, high-temperature baking is carried out to described substrate and described epitaxial loayer.
Preferably, in described step C, while high-temperature baking, the hydrogen that flow is 50-150SLM is passed into.
Three of object of the present invention is to overcome deficiency of the prior art, provides a kind of semiconductor device.
For realizing above object, the present invention is achieved through the following technical solutions:
Semiconductor device, is characterized in that, comprises above-mentioned epitaxial wafer.
Epitaxial wafer of the present invention, warped degree meets the Production requirement of rear road device, effectively avoids integrated circuit suppliers to expose processing and defocuses, improve yields and the product quality of rear road device.Meet the rigors of the product such as Mobile Communications, information household appliances for extension product better.
Adopt the semiconductor device that epitaxial wafer of the present invention makes, yields and product quality high, meet integrated circuit (IC) design better towards development trend that is light, thin, short, little and power saving.
Adopt epitaxial wafer manufacture method provided by the invention, the epitaxial wafer that warped degree is less than 30 μm can be obtained, effective reduction is because of the substrate warped degree that cause different from epitaxial loayer doping type of epitaxial wafer, thus make the warped degree of the substrate epitaxial wafer different with epitaxial loayer doping type meet the Production requirement of rear road device, effectively avoid integrated circuit suppliers to expose processing to defocus, improve the yields of rear road device.Simultaneously, adopt epitaxial wafer manufacture method provided by the invention, also can revise the shape of the substrate epitaxial wafer identical with epitaxial loayer doping type, the warped degree of the epitaxial wafer that further reduction substrate is identical with epitaxial loayer doping type, the substrate epitaxial wafer identical with epitaxial loayer doping type is made to adapt to rear road device production better, the quality of road device after improving.
Accompanying drawing explanation
Fig. 1 is the schematic diagram measuring epitaxial wafer warped degree;
Fig. 2 is another schematic diagram measuring epitaxial wafer warped degree;
Fig. 3 is the atomic diagram of the substrate epitaxial wafer different with epitaxial loayer doping type;
Fig. 4 is the structural representation of the traditional substrate epitaxial wafer different with epitaxial loayer doping type;
Fig. 5 is the structural representation of the epitaxial wafer in embodiment 1.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in detail:
Embodiment 1
The manufacture method of epitaxial wafer, is characterized in that, comprises the steps:
A. the obtained substrate 1 of CZ method is adopted.Carry out doping treatment to substrate 1, make substrate 1 form the doping of P type, the foreign atom of P type doping is boron atom, and the doping content of boron atom is 9*e 18individual/cm 3.
B. substrate 1 is put into the one chip epitaxial furnace that model is ASME2000, make to keep normal pressure in one chip epitaxial furnace.Then the trichlorosilane in one chip epitaxial furnace and hydrogen is utilized to issue biochemical vapour deposition at 1040 DEG C, to grow thickness on substrate 1 at the epitaxial loayer 2 of 1.5-150 μm, and the gross thickness controlling epitaxial loayer 2 and substrate 1 is in the scope of 645-675 μm or 745-775 μm.The present embodiment preferred version, the thickness of epitaxial loayer 2 is 18 μm, and the gross thickness of epitaxial loayer 2 and substrate 1 is 675 μm.Employing model is the epitaxial loayer that the one chip epitaxial furnace of ASME2000 makes, and the epitaxial loayer quality made compared with other epitaxial furnaces is high, all has castering action to the parameter such as resistance, thickness, resistance uniformity, thickness evenness of epitaxial loayer.Carry out doping treatment to epitaxial loayer, make epitaxial loayer 2 form N-type doping, the foreign atom of N-type doping is phosphorus atoms, and the doping content of phosphorus atoms is 1*e 17individual/cm 3.The doping treatment of this step is carried out with the grown epitaxial layer 2 in steps A in above-mentioned one chip epitaxial furnace simultaneously.
C. after having adulterated, the temperature in one chip epitaxial furnace is increased to 1130 DEG C, and passes into the hydrogen that flow is 100SLM, substrate 1 and epitaxial loayer 2 are carried out to the high-temperature baking of 50s, final obtained epitaxial wafer 01 (as shown in Figure 5).
In the process of the high-temperature baking of step C, when being baked to 0s, 20s, 30s, 45s, 50s, epitaxial wafer 01 is taken out in one chip epitaxial furnace respectively, and adopting company's warped degree=(a+b)/2 to calculate the warped degree of epitaxial wafer 01 after baking 20s, 30s, 45s, 50s, concrete numerical value is as shown in table 1.
Embodiment 2
The manufacture method of epitaxial wafer, is characterized in that, comprises the steps:
A. the obtained substrate 1 of CZ method is adopted.Carry out doping treatment to substrate 1, make substrate 1 form the doping of P type, the foreign atom of P type doping is boron atom, and the doping content of boron atom is 1*e 20individual/cm 3.
B. substrate 1 is put into one chip epitaxial furnace, make to keep normal pressure in one chip epitaxial furnace.Then the trichlorosilane in one chip epitaxial furnace and hydrogen is utilized to issue biochemical vapour deposition at 1200 DEG C, to grow thickness on substrate 1 at the epitaxial loayer 2 of 1.5-150 μm, and the gross thickness controlling epitaxial loayer 2 and substrate 1 is in the scope of 645-675 μm or 745-775 μm.The present embodiment preferred version, the thickness of epitaxial loayer 2 is 50 μm, and the gross thickness of epitaxial loayer 2 and substrate 1 is 745 μm.Carry out doping treatment to epitaxial loayer 2, make epitaxial loayer 2 form N-type doping, the foreign atom of N-type doping is arsenic atom, and the doping content of arsenic atom is 8*e 16individual/cm 3.The doping treatment of this step is carried out with the grown epitaxial layer 2 in steps A in above-mentioned one chip epitaxial furnace simultaneously.
C. after having adulterated, the temperature in one chip epitaxial furnace is adjusted to 1100 DEG C, and passes into the hydrogen that flow is 50SLM, substrate 1 and epitaxial loayer 2 are carried out to the high-temperature baking of 50s, final obtained epitaxial wafer 01.
In the process of the high-temperature baking of step C, when being baked to 0s, 20s, 30s, 45s, 50s, epitaxial wafer 01 is taken out in one chip epitaxial furnace respectively, and adopting company's warped degree=(a+b)/2 to calculate the warped degree of epitaxial wafer 01 after baking 20s, 30s, 45s, 50s, concrete numerical value is as shown in table 1.
Embodiment 3
The manufacture method of epitaxial wafer, is characterized in that, comprises the steps:
A. the obtained substrate 1 of CZ method is adopted.Carry out doping treatment to substrate 1, make substrate 1 form the doping of P type, the foreign atom of P type doping is boron atom, and the doping content of boron atom is 4.5*e 19individual/cm 3.
B. substrate 1 is put into one chip epitaxial furnace, make to keep normal pressure in one chip epitaxial furnace.Then the trichlorosilane in one chip epitaxial furnace and hydrogen is utilized to issue biochemical vapour deposition at 1130 DEG C of environment, to grow thickness on substrate 1 at the epitaxial loayer 2 of 1.5-150 μm, and the gross thickness controlling epitaxial loayer 2 and substrate 1 is in the scope of 645-675 μm or 745-775 μm.The present embodiment preferred version, the thickness of epitaxial loayer 2 is 1.5 μm, and the gross thickness of epitaxial loayer 2 and substrate 1 is 775 μm.Carry out doping treatment to epitaxial loayer 2, make epitaxial loayer 2 form N-type doping, the foreign atom of N-type doping is antimony atoms, and the doping content of antimony atoms is 2*e 17individual/cm 3.The doping treatment of this step is carried out with the grown epitaxial layer 2 in steps A in above-mentioned one chip epitaxial furnace simultaneously.
C. after having adulterated, the temperature in one chip epitaxial furnace is increased to 1150 DEG C, and passes into the hydrogen that flow is 150SLM, substrate 1 and epitaxial loayer 2 are carried out to the high-temperature baking of 50s, final obtained epitaxial wafer 01.
In the process of the high-temperature baking of step C, when being baked to 0s, 20s, 30s, 45s, 50s, epitaxial wafer 01 is taken out in one chip epitaxial furnace respectively, and adopting company's warped degree=(a+b)/2 to calculate the warped degree of epitaxial wafer 01 after baking 20s, 30s, 45s, 50s, concrete numerical value is as shown in table 1.
Embodiment 4
The manufacture method of epitaxial wafer, is characterized in that, comprises the steps:
A. the obtained substrate 1 of CZ method is adopted.Carry out doping treatment to substrate 1, make substrate 1 form the doping of P type, the foreign atom of P type doping is boron atom, and the doping content of boron atom is 5.5*e 20individual/cm 3.
B. substrate 1 is put into one chip epitaxial furnace, make to keep normal pressure in one chip epitaxial furnace.Then the trichlorosilane in one chip epitaxial furnace and hydrogen is utilized to issue biochemical vapour deposition at 1150 DEG C, to grow thickness on substrate 1 at the epitaxial loayer 2 of 1.5-150 μm, and the gross thickness controlling epitaxial loayer 2 and substrate 1 is in the scope of 645-675 μm or 745-775 μm.The present embodiment preferred version, the thickness of epitaxial loayer 2 is 150 μm, and the gross thickness of epitaxial loayer 2 and substrate 1 is 650 μm.Doping treatment is carried out to epitaxial loayer 2.Make epitaxial loayer 2 form N-type doping, the foreign atom of N-type doping is antimony atoms and phosphorus atoms, and the doping content neutralization of antimony atoms and phosphorus atoms is 1*e 17individual/cm 3.The doping treatment of this step is carried out with the grown epitaxial layer 2 in steps A in above-mentioned one chip epitaxial furnace simultaneously.
C. after having adulterated, the temperature in one chip epitaxial furnace is adjusted to 1130 DEG C, and passes into the hydrogen that flow is 120SLM, substrate 1 and epitaxial loayer 2 are carried out to the high-temperature baking of 50s, final obtained epitaxial wafer 01.
In the process of the high-temperature baking of step C, when being baked to 0s, 20s, 30s, 45s, 50s, epitaxial wafer 01 is taken out in one chip epitaxial furnace respectively, and adopting company's warped degree=(a+b)/2 to calculate the warped degree of epitaxial wafer 01 after baking 20s, 30s, 45s, 50s, concrete numerical value is as shown in table 1.
Embodiment 5
The manufacture method of epitaxial wafer, is characterized in that, comprises the steps:
A. the obtained substrate 1 of CZ method is adopted.Carry out doping treatment to substrate 1, make substrate 1 form N-type doping, the foreign atom of N-type doping is phosphorus atoms, and the doping content of phosphorus atoms is 5*e 19individual/cm 3.
B. substrate 1 is put into one chip epitaxial furnace, make to keep normal pressure in one chip epitaxial furnace.Then the trichlorosilane in one chip epitaxial furnace and hydrogen is utilized to issue biochemical vapour deposition at 1050 DEG C of environment, to grow thickness on substrate 1 at the epitaxial loayer 2 of 1.5-150 μm, and the gross thickness controlling epitaxial loayer 2 and substrate 1 is in the scope of 645-675 μm or 745-775 μm.The present embodiment preferred version, the thickness of epitaxial loayer 2 is 38 μm, and the gross thickness of epitaxial loayer 2 and substrate 1 is 645 μm.Carry out doping treatment.Make epitaxial loayer 2 form the doping of P type, the foreign atom of P type doping is boron atom, and the doping content of boron atom is 1.5*e 17individual/cm 3.The doping treatment of this step is carried out with the grown epitaxial layer 2 in steps A in above-mentioned one chip epitaxial furnace simultaneously.
C. after having adulterated, the temperature in one chip epitaxial furnace is increased to 1120 DEG C, and passes into the hydrogen that flow is 110SLM, substrate 1 and epitaxial loayer 2 are carried out to the high-temperature baking of 50s, final obtained epitaxial wafer 01.
In the process of the high-temperature baking of step C, when being baked to 0s, 20s, 30s, 45s, 50s, epitaxial wafer 01 is taken out in one chip epitaxial furnace respectively, and adopting company's warped degree=(a+b)/2 to calculate the warped degree of epitaxial wafer 01 after baking 20s, 30s, 45s, 50s, concrete numerical value is as shown in table 1.
Table 1
As shown in Table 1, though be to substrate be P type doping, epitaxial loayer be N-type doping epitaxial wafer (embodiment 1-4), or the epitaxial wafer (embodiment 5) that substrate is N-type doping, epitaxial loayer is the doping of P type, the warped degree of the epitaxial wafer that the warped degree of the epitaxial wafer after high-temperature baking process under hydrogen environment does not all toast reduces.Under the hot environment of 1100 ~ 1200 DEG C being connected with hydrogen, toast 30s after epitaxial wafer carries out doping treatment, warped degree remains within the scope of 14 ~ 18 μm; Baking 45s, warped degree remains within the scope of 8 ~ 12 μm; Baking 50s, warped degree remains on lower than within the scope of 7 μm.Namely in the baking time of 50s, baking time is longer, and the value that the warped degree of epitaxial wafer reduces is larger.
As can be seen here, adopt epitaxial wafer manufacture method provided by the invention, effectively can reduce the substrate warped degree that cause different from epitaxial loayer doping type because of epitaxial wafer, thus make the warped degree of the substrate epitaxial wafer different with epitaxial loayer doping type meet the Production requirement of rear road device, effectively avoid integrated circuit suppliers to expose processing to defocus, improve the yields of rear road device.Simultaneously, adopt epitaxial wafer manufacture method provided by the invention, also can revise the shape of the substrate epitaxial wafer identical with epitaxial loayer doping type, the warped degree of the epitaxial wafer that further reduction substrate is identical with epitaxial loayer doping type, the substrate epitaxial wafer identical with epitaxial loayer doping type is made to adapt to rear road device production better, the quality of road device after improving.
Embodiment in the present invention, only for the present invention will be described, does not form the restriction to right, other equivalent in fact substituting, all in scope that those skilled in that art can expect.

Claims (10)

1. epitaxial wafer, is characterized in that, comprises substrate and epitaxial loayer; Described substrate is different with the doping type of described epitaxial loayer; Described substrate is the doping of P type, and described epitaxial loayer is N-type doping; Or described substrate is N-type doping, described epitaxial loayer is the doping of P type.
2. epitaxial wafer according to claim 1, is characterized in that, the atom that described P type adulterates is boron atom.
3. want the epitaxial wafer described in 2 according to right, it is characterized in that, the doping type of described boron atom is overweight mixing, and doping content is 9*e 18~ 1*e 20individual/cm 3.
4. epitaxial wafer according to claim 1, is characterized in that, the foreign atom of described N-type doping is the one or several arbitrarily in phosphorus atoms, arsenic atom, antimony atoms.
5. epitaxial wafer according to claim 4, is characterized in that, the doping type of described phosphorus atoms is heavily doped, and doping content is 8*e 16~ 2*e 17individual/cm 3.
6. epitaxial wafer according to claim 1, is characterized in that, the thickness of described epitaxial loayer is 1.5 ~ 150 μm.
7. epitaxial wafer according to claim 1, is characterized in that, thickness 645 ~ 675 μm or 745 ~ 775 μm.
8. the manufacture method of the epitaxial wafer described in any one of claim 1-7, is characterized in that, comprises the steps:
A., one substrate is provided; Doping treatment is carried out to substrate, makes described substrate form the doping of P type or N-type doping;
B. grown epitaxial layer over the substrate; Doping treatment is carried out to described epitaxial loayer, makes described epitaxial loayer form the doping of P type or N-type doping;
C. after having adulterated, carry out high-temperature baking to described substrate and described epitaxial loayer, baking temperature is 1100 ~ 1120 DEG C, and baking time is 20 ~ 50s.
9. the manufacture method of epitaxial wafer according to claim 8, is characterized in that, in described step C, while high-temperature baking, passes into the hydrogen that flow is 50-150SLM.
10. semiconductor device, is characterized in that, comprises the epitaxial wafer described in any one of claim 1-7.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109003884A (en) * 2018-07-04 2018-12-14 上海晶盟硅材料有限公司 Preparation method, epitaxial wafer and the semiconductor devices of epitaxial wafer without back side silicon single crystal
CN109037030A (en) * 2018-07-04 2018-12-18 上海晶盟硅材料有限公司 Improve preparation method, epitaxial wafer and the semiconductor devices of the epitaxial wafer of back side silicon single crystal

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5261999A (en) * 1991-05-08 1993-11-16 North American Philips Corporation Process for making strain-compensated bonded silicon-on-insulator material free of dislocations
CN101187058A (en) * 2006-09-20 2008-05-28 硅电子股份公司 Silicon wafer for semiconductor and manufacturing method thereof
CN101256958A (en) * 2008-04-08 2008-09-03 南京国盛电子有限公司 Method for manufacturing IGBT silicon epitaxial wafer
JP4460671B2 (en) * 1999-03-26 2010-05-12 シルトロニック・ジャパン株式会社 Silicon semiconductor substrate and manufacturing method thereof
CN101724896A (en) * 2009-11-26 2010-06-09 上海宏力半导体制造有限公司 Method for growing germanium-silicon epitaxies in nonselective way
CN102290337A (en) * 2011-09-26 2011-12-21 南京国盛电子有限公司 Manufacturing method for silicon epitaxial wafer of low-voltage TVS (transient voltage suppressor)
CN102376749A (en) * 2010-08-09 2012-03-14 硅电子股份公司 Silicon wafer and production method thereof
CN103633120A (en) * 2012-08-28 2014-03-12 上海晶盟硅材料有限公司 Resistivity gradient distributed epitaxial wafer and production method thereof

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5261999A (en) * 1991-05-08 1993-11-16 North American Philips Corporation Process for making strain-compensated bonded silicon-on-insulator material free of dislocations
JP4460671B2 (en) * 1999-03-26 2010-05-12 シルトロニック・ジャパン株式会社 Silicon semiconductor substrate and manufacturing method thereof
CN101187058A (en) * 2006-09-20 2008-05-28 硅电子股份公司 Silicon wafer for semiconductor and manufacturing method thereof
CN101256958A (en) * 2008-04-08 2008-09-03 南京国盛电子有限公司 Method for manufacturing IGBT silicon epitaxial wafer
CN101724896A (en) * 2009-11-26 2010-06-09 上海宏力半导体制造有限公司 Method for growing germanium-silicon epitaxies in nonselective way
CN102376749A (en) * 2010-08-09 2012-03-14 硅电子股份公司 Silicon wafer and production method thereof
CN102290337A (en) * 2011-09-26 2011-12-21 南京国盛电子有限公司 Manufacturing method for silicon epitaxial wafer of low-voltage TVS (transient voltage suppressor)
CN103633120A (en) * 2012-08-28 2014-03-12 上海晶盟硅材料有限公司 Resistivity gradient distributed epitaxial wafer and production method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
段光复: "《高效晶硅太阳电池技术-设计、制造、测试、发电》", 28 February 2014 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109003884A (en) * 2018-07-04 2018-12-14 上海晶盟硅材料有限公司 Preparation method, epitaxial wafer and the semiconductor devices of epitaxial wafer without back side silicon single crystal
CN109037030A (en) * 2018-07-04 2018-12-18 上海晶盟硅材料有限公司 Improve preparation method, epitaxial wafer and the semiconductor devices of the epitaxial wafer of back side silicon single crystal

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