CN102332465A - Novel substrate, epitaxial wafer and semiconductor device - Google Patents
Novel substrate, epitaxial wafer and semiconductor device Download PDFInfo
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- CN102332465A CN102332465A CN201110295648A CN201110295648A CN102332465A CN 102332465 A CN102332465 A CN 102332465A CN 201110295648 A CN201110295648 A CN 201110295648A CN 201110295648 A CN201110295648 A CN 201110295648A CN 102332465 A CN102332465 A CN 102332465A
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Abstract
The invention discloses a novel substrate, which comprises a substrate body, and the novel substrate is characterized in that a monocrystalline silicon layer is arranged on the surface of the substrate body. The resistivity uniformity of an epitaxial layer produced with the novel substrate in the invention can be less than 1.5 percent. Compared with the resistivity uniformity value of an epitaxial layer which is not produced with the novel substrate in the invention, the resistivity uniformity value of the epitaxial layer in the invention can be decreased by one percent. By means of using the novel substrate in the invention, the subsequent production cost can be reduced, and the quality of products can be increased.
Description
Technical field
The present invention relates to a kind of novel substrate, epitaxial wafer and semiconductor device.
Background technology
For semiconductor device, need epitaxial loayer to have perfect crystal structure, and all there is certain requirement the aspects such as thickness, conduction type, resistivity and resistance uniformity of epitaxial loayer.Semi-conductive resistivity generally changes along with the variation of factors such as temperature, doping content, magnetic field intensity and intensity of illumination.
Combination and product specification for epitaxial loayer and substrate are to be determined by the product application of road, back.Circuit and electronic component need complete on epitaxial wafer, PMOS, NMOS, CMOS and ambipolar middle saturation type and unsaturation type in different application such as the MOS type.Along with IC design towards light, thin, short, little and economize the development trend of electrification, the energy resource consumption of effecting the greatest economy invariably of products such as Mobile Communications, information household appliances also improves constantly for the extension product requirement.Solve the change profile problem of epitaxial wafer resistivity, can satisfy not only that epitaxial wafer is light, thin, little, the power saving development trend, can also improve the utilization rate of road electronic component behind the epitaxial wafer, effectively reduce the product cost of client.
Substrate is also referred to as substrate.In a large amount of at present homoepitaxy sheets that use, substrate is identical with the element that the main body of epitaxial loayer constitutes, and is silicon.Dopant mainly contains n type element and p type element.N type element comprises arsenic AS, antimony and phosphorus (PH); P type element mainly is a boron element.
Existing epitaxial wafer, the kind and the concentration of substrate and epitaxial loayer dopant are inequality.Like a kind of epitaxial wafer commonly used, its substrate is the N type, i.e. one or more in Doped n-type atom phosphorus, arsenic or the antimony in the substrate; Its epitaxial loayer is doped with p type atomic boron.In the production process of epitaxial wafer, exist general auto-doping phenomenon.Autodoping be since the accessory substance of thermal evaporation or chemical reaction to the diffusion of substrate, silicon in the substrate and impurity get into gas phase, have changed doping composition and the concentration in the gas phase, thereby have caused the impurity actual distribution in the epitaxial loayer to depart from desirable situation.By the reason that produces, autodoping can be divided into gas phase autodoping, solid phase outdiffusion and system's autodoping.The alloy of gas phase autodoping is mainly from the back side and the edge solid phase outdiffusion of wafer.Mainly from the diffusion of substrate, alloy diffuses to epitaxial loayer at the contact-making surface of substrate and epitaxial loayer by substrate to the alloy of solid phase outdiffusion.The alloy of system's autodoping is from the gas wafer, the inside of graphite plate and reacting furnace cavity homepitaxy sheet process units.
Generation reason by autodoping can find out that in the epitaxial wafer production process, especially in the production method of vapour phase epitaxy, auto-doping phenomenon is difficult to avoid.
Be illustrated in figure 1 as a kind of sketch map of epitaxial wafer, because the influence of autodoping, generally speaking, 1. locate the highlyest, 2., 3., 4., 5. locate to take second place with respect to outer ring resistivity, edge 6., 7., 8., 9. to locate resistance lower relatively.Also can exist edge's resistivity to be higher than situation in some cases near circle centre position resistivity.The inhomogeneity standard of gauge resistor can be calculated computing formula through computing formula: the * 100%/(MAX+MIN) of resistivity evenness=(MAX-MIN), and MAX is a maximum resistance rate score in 9 points, MIN is a minimum resistance rate score in 9 points.The uniformity numerical value that calculates through this computing formula is more little, and then its uniformity is high more, and the epitaxial wafer quality is high more.
At present, can accept scope less than 5% for the resistivity evenness of epitaxial wafer.And epitaxial wafer of the prior art, its resistivity evenness is minimum also only to reach 2.5%, and according to prior art production, resistivity evenness numerical value is difficult to reduce again.
The mutual diffusion of the impurity in the substrate and the impurity of epitaxial loayer has reduced the resistance uniformity of epitaxial loayer.How a kind of self-diffusion substrate that reduces in the epitaxial loayer production process is provided, and to improve epilayer resistance rate uniformity, one to being the difficult in the industry problem to overcome.
Summary of the invention
The objective of the invention is in order to overcome deficiency of the prior art, a kind of inhomogeneity novel substrate of epilayer resistance rate that improves is provided.
For realizing above purpose, the present invention realizes through following technical scheme:
Novel substrate comprises substrate bulk, it is characterized in that, is provided with monocrystalline silicon layer on the substrate bulk surface.
Preferably, described monocrystalline silicon layer thickness is 2-5 μ m.
Preferably, described substrate bulk is the N type.
Preferably, described N type substrate bulk is doped with at least a element in arsenic, phosphorus and the antimony.
Preferably, described substrate bulk is the P type.
Preferably, described P type substrate bulk is doped with boron.
Another object of the present invention provides the high epitaxial wafer of a kind of epilayer resistance uniformity.
Epitaxial wafer is characterized in that, comprises aforesaid novel substrate.
The 3rd purpose of the present invention provides a kind of semiconductor device.
Semiconductor device is characterized in that, the epitaxial wafer before comprising.
Epilayer resistance rate uniformity is one of important indicator of weighing an epitaxial growth strength of enterprise, is a kind of measurement index of processing procedure ability height.Resistivity evenness is good can to guarantee that each device on the technology epitaxial wafer of back electrically meets the requirements.If the epitaxial wafer resistivity evenness is bad, in the subsequent technique process, can increase the edge devices scrappage greatly, increase the technology cost and reduce the IC products quality.
Among the present invention, monocrystalline silicon layer is set, can substrate bulk and epitaxial loayer be separated, can prevent that therefore substrate bulk and epitaxial loayer from producing auto-doping phenomenon on the substrate bulk surface.Prevent that the dopant in the substrate bulk from getting into epitaxial loayer, can improve the resistivity evenness of epitaxial loayer.
Use the novel substrate among the present invention, with respect to the substrate that monocrystalline silicon layer is not set, when grown epitaxial layer, the growth temperature of epitaxial loayer can reduce by 20 ℃, and still can produce the higher epitaxial loayer of resistance uniformity.Therefore, the novel substrate that uses the method among the present invention to produce, more energy-conservation when making epitaxial wafer.
Use the novel substrate among the present invention to make epitaxial wafer, the transition region SRP curve of epitaxial wafer is more precipitous.
Using the epitaxial loayer of the novel substrate production among the present invention, its resistivity evenness can accomplish＜1.5%.Than the epitaxial loayer that does not use novel substrate production of the present invention, the epilayer resistance rate uniformity numerical value among the present invention can reduce by 1 percentage point.Use the novel substrate among the present invention, can reduce the subsequent production cost, improve product quality.
Description of drawings
Fig. 1 is a kind of epitaxial wafer sketch map;
Fig. 2 is the novel substrat structure sketch map among the present invention.
Fig. 3 is the epitaxial slice structure sketch map among the present invention.
Fig. 4 is the SRP figure of the epitaxial wafer of embodiment 12 and comparative example's 9 productions.
Embodiment
Below in conjunction with embodiment the present invention is carried out detailed description:
Embodiment 1-4
As shown in Figure 2, novel substrate comprises substrate bulk 1, has monocrystalline silicon layer 2 on substrate bulk 1 surface.The thickness of monocrystalline silicon layer 2 is 2-5 μ m.Its concrete thickness can be confirmed according to the general thickness of epitaxial wafer, the thickness of substrate bulk.Substrate thickness is high more, and then monocrystalline silicon layer is also thick more.In the subsequent production, at monocrystalline silicon layer 2 superficial growth epitaxial loayers.
Embodiment 1-4 is heavily doped arsenic substrate bulk, between substrate bulk and epitaxial loayer, is provided with 2 μ m, 2.6 μ m, 3.5 μ m, 4.8 μ m monocrystalline silicon layers among the embodiment 1-4 respectively.
Among the embodiment 1-4, monocrystalline silicon layer all adopts trichlorosilane and hydrogen reaction to generate.The monocrystalline silicon that reaction generates is deposited on substrate bulk 1 surface and forms monocrystalline silicon layer 2.Reaction temperature among the embodiment 1-4 is respectively 920 ℃, 950 ℃, 985 ℃, 1015 ℃.Hydrogen flow rate among the embodiment 1-4 is respectively 120slm/s, 135slm/s, 150slm/s and 165slm/s.
Embodiment 5-8
Fig. 3 is the epitaxial slice structure sketch map among the embodiment 5-8.Embodiment 5-8 uses the substrate among the embodiment 1-4 respectively.As shown in Figure 3, form epitaxial loayer 3 on monocrystalline silicon layer 2 surfaces.Monocrystalline silicon layer 2 is between substrate bulk 1 and epitaxial loayer 3.
Among the comparative example 1-4, substrate bulk is heavily doped arsenic body, between substrate bulk and epitaxial loayer, monocrystalline silicon layer is not set.
The epilayer resistance uniformity correction data of embodiment 5-8 and comparative example 1-4 as the table 1-4 shown in shown in.In each group contrast, all select two substrate bulk of same batch of production for use, a slice is provided with regrowth epitaxial loayer behind the monocrystalline silicon layer; Another sheet direct growth epitaxial loayer.Outer layer growth technology is all identical.Test point is a 1-9 point as shown in Figure 1.
Table 1:
| |
Point 2 | Point 3 | Point 4 | Point 5 | Point 6 | Point 7 | Point 8 | Point 9 | AVE | UNI | |
| Embodiment 5 | 6.712 | 6.81 | 6.803 | 6.806 | 6.755 | 6.594 | 6.677 | 6.583 | 6.582 | 6.657 | 1.70％ |
| The comparative example 1 | 6.801 | 6.843 | 6.932 | 6.844 | 6.885 | 6.67 | 6.541 | 6.571 | 6.601 | 6.732 | 2.90％ |
Table 2:
| |
Point 2 | Point 3 | Point 4 | Point 5 | Point 6 | Point 7 | Point 8 | Point 9 | AVE | UNI | |
| Embodiment 6 | 5.215 | 5.29 | 5.259 | 5.269 | 5.279 | 5.105 | 5.109 | 5.102 | 5.209 | 5.191 | 1.81％ |
| The comparative example 2 | 5.083 | 5.122 | 5.103 | 5.09 | 5.121 | 4.881 | 4.894 | 4.925 | 4.881 | 5.011 | 2.41％ |
Table 3:
| Point 1 | Point 2 | Point 3 | Point 4 | Point 5 | Point 6 | Point 7 | Point 8 | Point 9 | AVE | UNI | |
| Embodiment 7 | 7.739 | 7.749 | 7.758 | 7.725 | 7.656 | 7.778 | 7.699 | 7.761 | 7.611 | 7.675 | 1.09％ |
| The comparative example 3 | 7.836 | 7.723 | 7.701 | 7.694 | 7.594 | 7.674 | 7.647 | 7.7907 | 7.416 | 7.738 | 2.75％ |
Table 4:
| |
Point 2 | Point 3 | Point 4 | Point 5 | Point 6 | Point 7 | Point 8 | Point 9 | AVE | UNI | |
| Embodiment 8 | 2.03 | 2.09 | 2.04 | 2.09 | 2.02 | 2.01 | 2.02 | 2.073 | 2.085 | 2.236 | 1.95％ |
| The comparative example 4 | 2.233 | 2.283 | 2.232 | 2.234 | 2.277 | 2.35 | 2.326 | 2.312 | 2.288 | 2.28 | 2.58％ |
In the table 1-table 4, some 1-point 9 row are represented the resistivity at 9 some places, unit: ohmcm respectively.The resistivity mean value at these nine some places is shown in the AVE tabulation.The resistance uniformity is shown in U NI tabulation, promptly according to the resistivity evenness formula: the numerical value that the * 100%/(MAX+MIN) of resistivity evenness=(MAX-MIN) calculates.
Can find out that from the data of table 1-table 4 use the substrate among the embodiment 1-4, the epilayer resistance uniformity of growth is higher.
Embodiment 9
Select two heavily doped phosphorus substrate bulk of same batch of production for use, a slice is used for embodiment 9, at substrate bulk 1 superficial growth monocrystalline silicon layer 2 back regrowth epitaxial loayers 3; Another sheet is used for comparative example 5, the direct growth epitaxial loayer on the substrate bulk surface.Monocrystalline silicon layer 2 among the embodiment 9 adopts trichlorosilane and hydrogen reaction to generate.Reaction temperature is 960 ℃, and hydrogen flow rate is 140slm/s.The monocrystalline silicon that reaction generates is deposited on substrate bulk 1 surface and forms monocrystalline silicon layer 2.Monocrystalline silicon layer 2 thickness are 4 μ m.
Among the comparative example 5, between substrate bulk and epitaxial loayer, monocrystalline silicon layer is not set.
Embodiment 9 is all identical with outer layer growth technology among the comparative example 5.
Embodiment 9, comparative example's 5 epilayer resistance uniformity correction data is as shown in table 5.Test point is a 1-9 point as shown in Figure 1.Data are as shown in table 5.
Table 5:
Can find out that from the data of table 5 use the substrate among the embodiment 9, the epilayer resistance uniformity of growth is higher.
Select for use two of same batch of production gently to mix the phosphorus substrate bulk, a slice is used for embodiment 10, at substrate bulk 1 superficial growth monocrystalline silicon layer 2 back regrowth epitaxial loayers 3; Another sheet is used for comparative example 6, the direct growth epitaxial loayer on the substrate bulk surface.Monocrystalline silicon layer 2 among the embodiment 10 adopts trichlorosilane and hydrogen reaction to generate.Reaction temperature is 1025 ℃, and hydrogen flow rate is 155slm/s.The monocrystalline silicon that reaction generates is deposited on substrate bulk 1 surface and forms monocrystalline silicon layer 2.Monocrystalline silicon layer 2 thickness are 3 μ m.
Among the comparative example 10, between substrate bulk and epitaxial loayer, monocrystalline silicon layer is not set.
Table 6:
Can find out that from the data of table 6 use the substrate among the embodiment 10, the epilayer resistance uniformity of growth is higher.
Embodiment 11
Select two heavily doped boron substrate bulk of same batch of production for use, a slice is used for embodiment 11, at substrate bulk 1 superficial growth monocrystalline silicon layer 2 back regrowth epitaxial loayers 3; Another sheet is used for comparative example 7, the direct growth epitaxial loayer on the substrate bulk surface.Monocrystalline silicon layer 2 among the embodiment 11 adopts trichlorosilane and hydrogen reaction to generate.Reaction temperature is 1030 ℃, and hydrogen flow rate is 145slm/s.The monocrystalline silicon that reaction generates is deposited on substrate bulk 1 surface and forms monocrystalline silicon layer 2.Monocrystalline silicon layer 2 thickness are 3 μ m.
Among the comparative example 7, between substrate bulk and epitaxial loayer, monocrystalline silicon layer is not set.
Embodiment 11 is all identical with outer layer growth technology among the comparative example 7.
Embodiment 11, comparative example's 7 epilayer resistance uniformity correction datas are as shown in table 7.Test point is a 1-9 point as shown in Figure 1.Data are as shown in table 7.
Table 7
Can find out that from the data of table 7 use the substrate of embodiment 11, the epilayer resistance uniformity of growth is higher.
Embodiment 12
Select two light boron-doping substrate bulk of same batch of production for use, a slice is used for embodiment 12, at substrate bulk 1 superficial growth monocrystalline silicon layer 2 back regrowth epitaxial loayers 3; Another sheet is used for comparative example 8, the direct growth epitaxial loayer on the substrate bulk surface.Monocrystalline silicon layer 2 among the embodiment 12 adopts trichlorosilane and hydrogen reaction to generate.Reaction temperature is 990 ℃, and hydrogen flow rate is 140slm/s.The monocrystalline silicon that reaction generates is deposited on substrate bulk 1 surface and forms monocrystalline silicon layer 2.Monocrystalline silicon layer 2 thickness are 1.5 μ m.
Among the comparative example 8, between substrate bulk and epitaxial loayer, monocrystalline silicon layer is not set.
Embodiment 12 is all identical with outer layer growth technology among the comparative example 8.
Embodiment 12, comparative example's 8 epilayer resistance uniformity correction datas are as shown in table 8.Test point is a 1-9 point as shown in Figure 1.Data are as shown in table 8.
Table 8
Can find out that from the data of table 8 use the substrate among the embodiment 12, the epilayer resistance uniformity of growth is higher.
Embodiment 13, embodiment 14 and comparative example 9
Choose two novel substrates of embodiment 1, a slice is used for embodiment 13, at 1040 ℃ of following grown epitaxial layers.Another sheet is used for embodiment 14, at 1020 ℃ of following grown epitaxial layers.Among the comparative example 9, use the substrate that monocrystalline silicon layer is not set, at 1040 ℃ of following grown epitaxial layers.Among embodiment 13, embodiment 14 and the comparative example 9, the growth technique of epitaxial loayer is except that the temperature difference, and all the other steps are all identical.The resistivity evenness correction data of the epitaxial loayer that embodiment 13, embodiment 14, comparative example 9 are grown is as shown in table 9.
Table 9
Embodiment 15, embodiment 16 and comparative example 10
Choose two novel substrates of embodiment 2, a slice is used for embodiment 15, at 1040 ℃ of following grown epitaxial layers.A slice is used for embodiment 16, at 1020 ℃ of following grown epitaxial layers.Among the comparative example 10, use the substrate that monocrystalline silicon layer is not set, at 1040 ℃ of following grown epitaxial layers.Among embodiment 15, embodiment 16 and the comparative example 10, the growth technique of epitaxial loayer is except that the temperature difference, and all the other steps are all identical.The resistivity evenness correction data of the epitaxial loayer that embodiment 15, embodiment 16 and comparative example 10 are grown is as shown in table 10.
Table 10
Can find out from the data of table 9 and table 10, when the novel substrate in the same the present invention of use is made epitaxial wafer, under lower temperature, can obtain the better epitaxial loayer of resistivity evenness.Under identical temperature, use the novel substrate among the present invention, the resistivity evenness of the epitaxial loayer that comparable use substrate of the prior art is made is better.With respect to using substrate of the prior art to make epitaxial wafer, when the novel substrate among use the present invention is made epitaxial wafer,, still can produce more evenly epitaxial loayer of resistivity even the growth temperature of epitaxial loayer is hanged down 20 ℃.
Embodiment 12 is as shown in Figure 4 with the SRP figure of the epitaxial wafer that comparative example 9 produces, and from Fig. 4, can find out, the novel substrate that uses the inventive method to produce is made epitaxial wafer, and the transition region SRP curve of epitaxial wafer is more precipitous.
IGBT, i.e. insulated gate bipolar transistor: the compound device for power switching that to be the mos gate device architecture combine and evolve and form with bipolar transistor is a main product in the present semiconductor device.The application market of IGBT is huge.One, is applied in the household electrical appliances energy-saving field, is mainly used on the frequency-conversion domestic electric appliances; Two, be applied in the electrical machine energy-saving field, be mainly used in the medium and low frequency frequency converter, and high voltage converter; Three, be applied in high ferro, intelligent grid and new energy field.
The epitaxial wafer that uses the novel substrate among the present invention to make meets IGBT high-speed switching capability and bipolar processes ability, can obtain driving, characteristics capacious.The substrate bulk surface has monocrystalline silicon layer, in low-temperature epitaxy is made, can obtain precipitous substrate and the epitaxial layer transition zone of SRP curve, road manufacturing behind the IGBT is laid the basis, preceding road of good characteristic.
Embodiment among the present invention only is used for that the present invention will be described, does not constitute the restriction to the claim scope, and other substituting of being equal in fact that those skilled in that art can expect are all in protection range of the present invention.
Claims (8)
1. novel substrate comprises substrate bulk, it is characterized in that, is provided with monocrystalline silicon layer on the substrate bulk surface.
2. novel substrate according to claim 1 is characterized in that, described monocrystalline silicon layer thickness is 2-5 μ m.
3. novel substrate according to claim 1 is characterized in that, described substrate bulk is the N type.
4. novel substrate according to claim 3 is characterized in that, described N type substrate bulk is doped with at least a element in arsenic, phosphorus and the antimony.
5. novel substrate according to claim 1 is characterized in that, described substrate bulk is the P type.
6. novel substrate according to claim 5 is characterized in that, described P type substrate bulk is doped with boron.
7. epitaxial wafer is characterized in that, comprises the described novel substrate of the arbitrary claim of claim 1 to 6.
8. semiconductor device is characterized in that, comprises the described epitaxial wafer of claim 7.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106505093A (en) * | 2016-10-21 | 2017-03-15 | 上海晶盟硅材料有限公司 | Epitaxial wafer production method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101256958A (en) * | 2008-04-08 | 2008-09-03 | 南京国盛电子有限公司 | Method for manufacturing IGBT silicon epitaxial wafer |
| CN202332856U (en) * | 2011-09-30 | 2012-07-11 | 上海晶盟硅材料有限公司 | Novel substrate, epitaxial wafer and semiconductor element |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101256958A (en) * | 2008-04-08 | 2008-09-03 | 南京国盛电子有限公司 | Method for manufacturing IGBT silicon epitaxial wafer |
| CN202332856U (en) * | 2011-09-30 | 2012-07-11 | 上海晶盟硅材料有限公司 | Novel substrate, epitaxial wafer and semiconductor element |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106505093A (en) * | 2016-10-21 | 2017-03-15 | 上海晶盟硅材料有限公司 | Epitaxial wafer production method |
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Application publication date: 20120125 |