CN111929569B - Calibration method, system and device of IC chip - Google Patents

Calibration method, system and device of IC chip Download PDF

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CN111929569B
CN111929569B CN202010984631.7A CN202010984631A CN111929569B CN 111929569 B CN111929569 B CN 111929569B CN 202010984631 A CN202010984631 A CN 202010984631A CN 111929569 B CN111929569 B CN 111929569B
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chip
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CN111929569A (en
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丁淼
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Shenzhen Injoinic Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

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Abstract

The application relates to a method, a system and a device for calibrating an IC chip, wherein an IC to be calibrated is assembled on a finished PCB, and then a port on the PCB is connected with a calibration circuit to carry out voltage calibration. Like this, can directly carry out voltage calibration and current calibration to the IC on the IC finished product, eliminate the test fixture and the PCB of traditional calibration method and walk the calibration deviation that the line caused, effectively improve calibration accuracy, also avoided traditional calibration method to cause the risk of damage to the IC at the dismouting in-process, it is more secure to leave factory IC quality, through utilizing the finished product calibration after the volume production from the port of taking on the finished product, need not to tear open the shell simultaneously, easy operation, greatly reduced cost has shortened development cycle.

Description

Calibration method, system and device of IC chip
Technical Field
The application belongs to the technical field of chips, and particularly relates to a method, a system and a device for calibrating an IC chip.
Background
Due to wafer manufacturing variations, Integrated Circuit (IC) chips are calibrated for various internal parameters before they are shipped. For a direct current converter DCDC chip and a protocol chip in a vehicle-mounted fast charging system, output voltage and output current of the DCDC chip and the protocol chip are main parameters and must be calibrated, and the output current is generally understood as a corresponding Over Current ProtectIOn (OCP) point.
However, the applicant found that: at present, the calibration of an IC chip before leaving a factory is generally to install an IC to be calibrated on a test fixture and then connect a peripheral calibration Circuit for calibration, because the test fixture can bring the deviation of contact impedance and even can be fatigue and soft after long-time test, the greater deviation is brought to the IC, and when the IC after leaving the factory is welded on a finished Printed Circuit Board (PCB), the deviation can be brought to various parameters of the IC due to the impedance and difference of PCB wiring, so that the requirement of high precision cannot be met.
Disclosure of Invention
The application provides a calibration method, a system and a device of an IC chip, so that calibration deviation caused by test fixtures and PCB wiring of a traditional calibration method is eliminated, calibration precision is effectively improved, the risk that the IC is damaged in the disassembly and assembly process of the traditional calibration method is avoided, the quality of an outgoing IC is guaranteed, meanwhile, a port on a finished product is utilized to calibrate the finished product after volume production, the shell does not need to be disassembled, the operation is simple and easy, the cost is greatly reduced, and the development period is shortened.
In a first aspect, an embodiment of the present application provides a calibration method for an IC chip, which is applied to a calibration circuit in a chip calibration system, where the chip calibration system includes the IC chip mounted on a finished printed circuit board PCB and the calibration circuit, the calibration circuit includes an analog-to-digital converter ADC sampling module, a switch K1, a switch K2, a load resistor RL1, a load resistor RL2, a system communication module, and a processor, a voltage output port of the IC chip is connected to a first end of the ADC sampling module, a first end of the switch K1, a first end of the switch K2, a second end of the switch K1 is connected to a first end of the load resistor RL1, a second end of the switch K2 is connected to a first end of the load resistor RL2, a second end of the ADC sampling module, a second end of the load resistor RL1, and a second end of the load resistor RL2 are combined and then grounded, the processor is connected with the ADC sampling module and the system communication module, and the IC chip is connected with the system communication module; the method comprises the following steps:
controlling the switch K1 and the switch K2 to be switched off, so that the output is unloaded;
setting the value of an internal output voltage register of the IC chip to VREG1 through the system communication module, and then obtaining the current actual output voltage VO1 through the ADC sampling module;
setting the value of the internal output voltage register of the IC chip to VREG2 through the system communication module, and then obtaining the current actual output voltage VO2 through the ADC sampling module;
the calibration values of the voltage parameters Voffset and Vstep to be calibrated are calculated by the following formula:
Vstep=（VO2－VO1）÷（VREG2－VREG1），
Voffset=VO1－[（VO2－VO1）÷（VREG2－VREG1）]×VREG1，
wherein an actual output voltage Vo of the IC chip and a value VREG of the internal output voltage register of the IC chip satisfy a first linear relationship, the value of the internal output voltage register corresponding to an internal reference voltage of the IC chip, the first linear relationship satisfying the following formula:
VO= Voffset + Vstep×VREG，
voffset is the drift of the internal output voltage register, and Vstep is the voltage step of the internal output voltage register.
In a second aspect, the present embodiments provide a calibration circuit for use in a chip calibration system, the chip calibration system including the IC chip and the calibration circuit mounted on a finished printed circuit board PCB, the calibration circuit including an analog-to-digital converter ADC sampling module, a switch K1, a switch K2, a load resistor RL1, a load resistor RL2, a system communication module, and a processor;
a voltage output port of the IC chip is connected to a first end of the ADC sampling module, a first end of the switch K1, and a first end of the switch K2, a second end of the switch K1 is connected to a first end of the load resistor RL1, a second end of the switch K2 is connected to a first end of the load resistor RL2, a second end of the ADC sampling module, a second end of the load resistor RL1, and a second end of the load resistor RL2 are grounded after being combined, the processor is connected to the ADC sampling module and the system communication module, and the IC chip is connected to the system communication module;
the calibration circuit is used for controlling the switch K1 and the switch K2 to be switched off, so that the output is unloaded;
the system communication module is used for setting the value of an internal output voltage register of the IC chip to VREG1, and then the ADC sampling module is used for obtaining the current actual output voltage VO 1;
the system communication module is used for setting the value of the internal output voltage register of the IC chip to VREG2, and then the ADC sampling module is used for obtaining the current actual output voltage VO 2;
and the calibration value for the voltage parameters Voffset and Vstep to be calibrated is calculated by the following formula:
Vstep=（VO2－VO1）÷（VREG2－VREG1），
Voffset=VO1－[（VO2－VO1）÷（VREG2－VREG1）]×VREG1，
wherein an actual output voltage Vo of the IC chip and a value VREG of the internal output voltage register of the IC chip satisfy a first linear relationship, the value of the internal output voltage register corresponding to an internal reference voltage of the IC chip, the first linear relationship satisfying the following formula:
VO= Voffset + Vstep×VREG，
voffset is the drift of the internal output voltage register, and Vstep is the voltage step of the internal output voltage register.
In a third aspect, the present invention provides a calibration circuit applied in a chip calibration system, the chip calibration system includes the IC chip and the calibration circuit mounted on a finished printed circuit board PCB, the calibration circuit includes an analog-to-digital converter ADC sampling module, a switch K1, a switch K2, a load resistor RL1, a load resistor RL2, a system communication module, and a processor, a voltage output port of the IC chip is connected to a first end of the ADC sampling module, a first end of the switch K1, a first end of the switch K2, a second end of the switch K1 is connected to a first end of the load resistor RL1, a second end of the switch K2 is connected to a first end of the load resistor RL2, a second end of the ADC sampling module, a second end of the load resistor RL1, and a second end of the load resistor RL2 are combined and then grounded, the processor is connected to the ADC sampling module and the system communication module, the IC chip is connected with the system communication module; the device comprises:
the disconnection unit is used for controlling the disconnection of the switch K1 and the switch K2 so as to enable the output to be unloaded;
the sampling unit is used for setting the value of an internal output voltage register of the IC chip to VREG1 through the system communication module and then obtaining the current actual output voltage VO1 through the ADC sampling module; setting the value of the internal output voltage register of the IC chip to VREG2 through the system communication module, and then obtaining the current actual output voltage VO2 through the ADC sampling module;
a calculating unit, configured to calculate calibration values of the voltage parameters Voffset and Vstep to be calibrated by using the following formulas:
Vstep=（VO2－VO1）÷（VREG2－VREG1），
Voffset=VO1－[（VO2－VO1）÷（VREG2－VREG1）]×VREG1，
wherein an actual output voltage Vo of the IC chip and a value VREG of the internal output voltage register of the IC chip satisfy a first linear relationship, the value of the internal output voltage register corresponding to an internal reference voltage of the IC chip, the first linear relationship satisfying the following formula:
VO= Voffset + Vstep×VREG，
voffset is the drift of the internal output voltage register, and Vstep is the voltage step of the internal output voltage register.
In a fourth aspect, embodiments of the present application provide a calibration circuit comprising a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing the steps of the first aspect of embodiments of the present application.
In a fifth aspect, the present application provides a computer storage medium, which is characterized by storing a computer program for electronic data exchange, wherein the computer program enables a computer to perform some or all of the steps described in the first aspect of the present embodiment.
In a sixth aspect, an embodiment of the present application provides a fast charging chip, where the fast charging chip is an IC chip, and is applied to some or all of the steps described in the first aspect of this embodiment.
In a seventh aspect, this application embodiment provides a computer program product, where the computer program product includes a non-transitory computer-readable storage medium storing a computer program, where the computer program is operable to cause a computer to perform some or all of the steps as described in the first aspect of this application embodiment. The computer program product may be a software installation package.
It can be seen that, in the embodiment of the application, the voltage calibration is directly performed on the IC on the finished product PCB, the calibration deviation caused by the test fixture and the PCB wiring of the traditional calibration method can be eliminated, the calibration precision is effectively improved, the risk of damage to the IC in the disassembly and assembly process of the traditional calibration method is also avoided, the quality of the outgoing IC is more guaranteed, meanwhile, the finished product after mass production is calibrated by using the port on the finished product, the shell does not need to be disassembled, the operation is simple and easy, the cost is greatly reduced, and the development period is shortened.
Drawings
Fig. 1 is a schematic circuit structure diagram of a calibration system of an IC chip according to an embodiment of the present disclosure;
fig. 2 is a schematic flowchart of a calibration method for an IC chip according to an embodiment of the present disclosure;
fig. 3 is a block diagram of functional units of a calibration apparatus for an IC chip according to an embodiment of the present disclosure;
fig. 4 is a schematic circuit structure diagram of a calibration circuit of an IC chip according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
According to the calibration method of the IC chip, the IC to be calibrated is assembled on the finished PCB, and then the port on the PCB is connected with the calibration circuit to carry out voltage calibration and current calibration. During voltage calibration and current calibration, the voltage calibration value and the current calibration value are calculated by setting an internal output voltage register of the IC and an internal output current register of the IC, switching different loads in a calibration circuit, sampling the actual output voltage of the PCB, and inputting the actual output voltage and the actual output voltage to the IC to realize the voltage calibration and the current calibration.
As shown in fig. 1, the chip calibration system according to the embodiment of the present application includes a finished PCB1 equipped with an IC to be tested and a calibration circuit 2; the calibration circuit 2 comprises an analog-digital converter (ADC) sampling module, a switch K1, a switch K2, a load resistor RL1, a load resistor RL2, a system communication module and a processor;
a voltage output port of the IC chip is connected to a first end of the ADC sampling module, a first end of the switch K1, and a first end of the switch K2, a second end of the switch K1 is connected to a first end of the load resistor RL1, a second end of the switch K2 is connected to a first end of the load resistor RL2, a second end of the ADC sampling module, a second end of the load resistor RL1, and a second end of the load resistor RL2 are grounded after being combined, the processor is connected to the ADC sampling module and the system communication module, and the IC chip is connected to the system communication module;
wherein, the IC chip includes but is not limited to a DC converter DCDC chip and a protocol chip.
The switch K1 and the switch K2 may be controlled to be turned on or off by a processor, which may be a micro control unit MCU or the like, and the type of processing is not limited herein.
The ADC sampling module may be, for example, a 16-bit ADC data acquisition chip AD7606, which is not limited herein.
The resistance of the load resistor RL1 may be 100 ohms, and the resistance of the load resistor RL2 may be, for example, 1000 ohms, and the like, which is not limited herein.
The connection between the IC chip and the calibration circuit may be realized through a trace on the PCB and an external port, or may be a direct connection, which is not limited herein. For example, the IC chip may be connected to the system communication module of the calibration circuit through a pin (e.g., a pin commonly used by a USB port such as CC, D +, D-) of the PCB, so as to implement internal communication with the IC chip, control reading and writing of an internal register of the IC, and switch the current output voltage or current of the IC chip.
The calibration circuit further comprises a memory connected to the processor, and the memory stores a program for executing the steps in the calibration method of current and voltage in the embodiment of the present application.
The calibration circuit is used for controlling the switch K1 and the switch K2 to be switched off, so that the output is unloaded;
the system communication module is used for setting the value of an internal output voltage register of the IC chip to VREG1, and then the ADC sampling module is used for obtaining the current actual output voltage VO 1;
the system communication module is used for setting the value of the internal output voltage register of the IC chip to VREG2, and then the ADC sampling module is used for obtaining the current actual output voltage VO 2;
and the calibration value for the voltage parameters Voffset and Vstep to be calibrated is calculated by the following formula:
Vstep=（VO2－VO1）÷（VREG2－VREG1），
Voffset=VO1－[（VO2－VO1）÷（VREG2－VREG1）]×VREG1，
wherein an actual output voltage Vo of the IC chip and a value VREG of the internal output voltage register of the IC chip satisfy a first linear relationship, the value of the internal output voltage register corresponding to an internal reference voltage of the IC chip, the first linear relationship satisfying the following formula:
VO= Voffset + Vstep×VREG，
voffset is the drift of the internal output voltage register, and Vstep is the voltage step of the internal output voltage register.
Voffset and Vstep are voltage calibration parameters of the IC chip.
Since the actual output voltage Vo of the IC chip and the value IREG of the internal output voltage register of the IC chip satisfy the first linear relationship, the value of the internal output voltage register is set to VREG1 at the time of the test, and the calibration system satisfies the equation
VO1= Voffset + Vstep×VREG1，
The value of the internal output voltage register is set to VREG2 and the calibration system satisfies the equation
VO2= Voffset + Vstep×VREG2，
Subtracting the two equations to obtain
VO2－VO1= Vstep×VREG2－Vstep×VREG1，
Namely Vstep = (VO 2-VO 1) ÷ (VREG 2-VREG 1).
In one possible example, the calibration circuit is further configured to set the value of the internal output voltage register of the IC chip to VREG3 through the system communication module;
setting the value of an internal output current register of the IC chip as a maximum value, closing the switch K1, opening the switch K2, obtaining the current actual output voltage VO3 through the ADC sampling module, and calculating the current actual output current IO1 through the following formula:
IO1=VO3÷RL1，
setting the internal output current register of the IC chip, reducing and collecting output voltage step by step, triggering an overcurrent protection action until the current output voltage is reduced or completely closed, and obtaining a value IREG1 of the currently set internal output current register, wherein the value IREG1 of the currently set internal output current register corresponds to an overcurrent protection OCP point of the current output current;
setting the value of the internal output current register of the IC chip as a maximum value, opening the switch K1, closing the switch K2, obtaining the current actual output voltage VO4 through the ADC sampling module, and calculating the current actual output current IO2 through the following formula:
IO2=VO4÷RL2，
setting the internal output current register of the IC chip, reducing and collecting output voltage step by step, triggering an overcurrent protection action until the current output voltage is reduced or completely closed, and obtaining a value IREG2 of the currently set internal output current register, wherein the value IREG2 of the currently set internal output current register corresponds to an overcurrent protection OCP point of the current output current;
the calibration values of the current parameters IOffset and Istep to be calibrated are calculated by the following formula:
Istep=（IO2－IO1）÷（IREG2－IREG1），
IOffset=IO1－[（IO2－IO1）÷（IREG2－IREG1）]×IREG1，
wherein the actual output current IO of the IC chip and the value IREG of the internal output current register of the IC chip satisfy a second linear relationship, the value of the internal output current register corresponds to the output current when the IC chip reaches an overcurrent protection state, and the second linear relationship satisfies the following formula:
IO= IOffset + Istep×IREG，
the IOffset is the drift of the internal output current register, and the Istep is the current step size of the internal output current register.
The IOffset and the Istep are current calibration parameters of the IC chip.
Because the actual output current IO of the IC chip and the value IREG of the internal output current register of the IC chip satisfy the second linear relationship, during the test, the initial value of the internal output current register is set to be the maximum value, in this case, the actual current of VO/RL is smaller than the maximum set current (i.e., the overcurrent protection point), the gear of the internal output current register needs to be reduced step by step, and the detection is continued until the current output voltage starts to be reduced to the reference value (i.e., the overcurrent protection action, which is specifically expressed as the current output voltage starts to be reduced or is completely turned off). The overcurrent protection point currents IO corresponding to different load resistors RL are different, so that the corresponding internal output current registers have different values.
Specifically, the calibration system satisfies the equation when the load resistance RL1 is applied
IO1= IOffset + Istep×IREG1，
When load resistance RL2 is acted on, the calibration system satisfies the equation
IO2= IOffset + Istep×IREG2，
Subtracting the two equations to obtain
IO2－IO1= Istep×IREG2－Istep×IREG1= Istep×（IREG2－IREG1），
I.e., Istep = (IO 2-IO 1) ÷ (IREG 2-IREG 1).
It can be seen that, in this example, the current calibration is directly performed on the IC on the finished product PCB, so that the calibration deviation caused by the test fixture and the PCB wiring of the conventional calibration method can be eliminated, the calibration precision is effectively improved, the risk of damage to the IC in the disassembly and assembly process of the conventional calibration method is also avoided, the quality of the outgoing IC is more guaranteed, and meanwhile, the finished product after mass production is calibrated by using the port on the finished product without disassembling the shell, so that the operation is simple and easy to implement, the cost is greatly reduced, and the development period is shortened. The calibration circuit can be suitable for the calibration of voltage and current simultaneously, and is flexible and comprehensive.
In one possible example, the calibration circuit is further configured to, prior to the step-down operation: acquiring historical detection data of a plurality of calibrated IC chips on the same production line; and determining a deviation of a target parameter of each of the plurality of IC chips from the historical detection data, the target parameter comprising an output voltage and/or an output current; and determining at least one of the plurality of IC chips having a deviation greater than a preset deviation; and determining an accuracy of the chip calibration system from the at least one IC chip and the plurality of IC chips; determining a single-chip calibration reference acceleration duration set by a user; and obtaining a target gear step length used for calibrating the batch of products according to the accuracy, the single-chip calibration reference acceleration time length, a preset reference gear step length, the reference accuracy and the single-chip calibration reference time length.
The preset deviation may be, for example, 2%, 1%, 0.1%, etc., and is not limited herein. The higher the accuracy of the chip calibration system is, the more chips are in actual use after calibration, and the deviation generated is within a preset range.
Wherein the stroke of the internal current register may be, for example, 0-28I.e., 0-256, the reference accuracy may be 98%, the reference gear step size may be set to 2 or 3 percent of the stroke (rounded) according to the reference accuracy, for example, through experimental detection or experience, the single calibration reference time length corresponds to the entire time length of the single chip completing the calibration process, and is mainly affected by the downshift frequency (other parameters such as load resistance may be kept consistent to reduce the differential influence factor), that is, the gear step size has positive correlation accuracy and negative correlation to the single calibration time length, the effects of the accuracy and the single calibration time length are comprehensively considered, and both the calibration efficiency and the calibration precision can be considered.
In a possible example, in the aspect of obtaining the target gear step size used for calibration of the batch of products according to the accuracy, the single-chip calibration reference acceleration duration, the preset reference gear step size, the reference accuracy, and the single-chip calibration reference duration, the calibration circuit is specifically configured to:
updating the gear step SG of the internal output current register by the following formula:
SG= SG0，τ≧τ0，
Figure 639259DEST_PATH_IMAGE001
，
τ﹤τ0，
wherein SG represents the target gear step size, SG0 represents a reference gear step size, SG0 takes the value of 1/10 of the stroke of the internal output current register, τ represents the accuracy, τ 0 represents the reference accuracy, τ 0 takes the value of a value agreed by an industry standard specification, Δ T represents the monolithic calibration reference speed-up duration, and T0 represents the monolithic calibration reference duration.
Wherein, the value range of the accuracy is [0,1], the monolithic calibration reference time length is obtained according to the detection of the actual circuit process, and generally ranges from 100ms to 5 seconds.
It can be seen that, in this example, the actual accuracy of the chip calibration system is obtained by performing statistical analysis on the historically calibrated chips, and it is indicated that the current gear step length has met the requirement for the case of being greater than or equal to the reference accuracy, and no need to be set intensively, and it is indicated that the progress of the chip calibration system needs to be increased to improve the calibration performance for the case of being less than the reference accuracy, and the calibration efficiency and precision can be considered comprehensively in consideration of the accuracy and the single-chip detection duration.
In one possible example, the calibration circuit is further configured to: and programming the calibrated voltage calibration value and/or current calibration value in an internal memory of the IC chip.
Wherein, after the IC chip is calibrated, the IC chip can calculate and output accurate voltage and current according to a formula.
In one possible example, the internal memory includes any one of: random access memory RAM, double data rate synchronous dynamic random access memory DDR, non-volatile memory NVM.
The storage mode of the internal memory of the IC chip includes, but is not limited to, the following modes: FLASH mode, MTP mode (a set of Media Transfer Protocol (Media Transfer Protocol) made by microsoft), OTP mode, etc.
In addition, the IC chip further comprises a first differential pressure sampling port IS + and a second differential pressure sampling port IS-, a sampling resistor RS IS connected between the first differential pressure sampling port IS + and the second differential pressure sampling port IS-, and the current output current IO of the IC chip can be obtained through the IC chip by sampling the differential pressure of IS +/IS-.
It can be seen that, in the embodiment of the application, the voltage calibration is directly performed on the IC on the finished product PCB, the calibration deviation caused by the test fixture and the PCB wiring of the traditional calibration method can be eliminated, the calibration precision is effectively improved, the risk of damage to the IC in the disassembly and assembly process of the traditional calibration method is also avoided, the quality of the outgoing IC is more guaranteed, meanwhile, the finished product after mass production is calibrated by using the port on the finished product, the shell does not need to be disassembled, the operation is simple and easy, the cost is greatly reduced, and the development period is shortened.
Referring to fig. 2, fig. 2 is a flowchart illustrating a calibration method of an IC chip according to an embodiment of the present disclosure, applied to a calibration circuit in the chip calibration system shown in fig. 1.
Step 201, controlling the switch K1 and the switch K2 to be switched off, so that the output is unloaded;
step 202, setting the value of an internal output voltage register of the IC chip to VREG1 through the system communication module, and then obtaining the current actual output voltage VO1 through the ADC sampling module;
step 203, setting the value of the internal output voltage register of the IC chip to VREG2 through the system communication module, and then obtaining the current actual output voltage VO2 through the ADC sampling module;
step 204, calculating the calibration values of the voltage parameters Voffset and Vstep to be calibrated by the following formula:
Vstep=（VO2－VO1）÷（VREG2－VREG1），
Voffset=VO1－[（VO2－VO1）÷（VREG2－VREG1）]×VREG1，
wherein an actual output voltage Vo of the IC chip and a value VREG of the internal output voltage register of the IC chip satisfy a first linear relationship, the value of the internal output voltage register corresponding to an internal reference voltage of the IC chip, the first linear relationship satisfying the following formula:
VO= Voffset + Vstep×VREG，
voffset is the drift of the internal output voltage register, and Vstep is the voltage step of the internal output voltage register.
In one possible example, the method further comprises:
setting a value of the internal output voltage register of the IC chip to VREG3 through the system communication module;
setting the value of an internal output current register of the IC chip as a maximum value, closing the switch K1, opening the switch K2, obtaining the current actual output voltage VO3 through the ADC sampling module, and calculating the current actual output current IO1 through the following formula:
IO1=VO3÷RL1，
setting the internal output current register of the IC chip, reducing and collecting output voltage step by step, triggering an overcurrent protection action until the current output voltage is reduced or completely closed, and obtaining a value IREG1 of the currently set internal output current register, wherein the value IREG1 of the currently set internal output current register corresponds to an overcurrent protection OCP point of the current output current;
setting the value of the internal output current register of the IC chip as a maximum value, opening the switch K1, closing the switch K2, obtaining the current actual output voltage VO4 through the ADC sampling module, and calculating the current actual output current IO2 through the following formula:
IO2=VO4÷RL2，
setting the internal output current register of the IC chip, reducing and collecting output voltage step by step, triggering an overcurrent protection action until the current output voltage is reduced or completely closed, and obtaining a value IREG2 of the currently set internal output current register, wherein the value IREG2 of the currently set internal output current register corresponds to an overcurrent protection OCP point of the current output current;
the calibration values of the current parameters IOffset and Istep to be calibrated are calculated by the following formula:
Istep=（IO2－IO1）÷（IREG2－IREG1），
IOffset=IO1－[（IO2－IO1）÷（IREG2－IREG1）]×IREG1，
wherein the actual output current IO of the IC chip and the value IREG of the internal output current register of the IC chip satisfy a second linear relationship, the value of the internal output current register corresponds to the output current when the IC chip reaches an overcurrent protection state, and the second linear relationship satisfies the following formula:
IO= IOffset + Istep×IREG，
the IOffset is the drift of the internal output current register, and the Istep is the current step size of the internal output current register.
In one possible example, prior to the operation of the gear-wise reduction, the method further comprises:
acquiring historical detection data of a plurality of calibrated IC chips on the same production line;
determining a deviation of a target parameter of each of the plurality of IC chips from the historical inspection data, the target parameter comprising an output voltage and/or an output current;
determining at least one IC chip of the plurality of IC chips, the deviation of which is greater than a preset deviation;
determining an accuracy of the chip calibration system from the at least one IC chip and the plurality of IC chips;
determining a single-chip calibration reference acceleration duration set by a user;
and obtaining a target gear step length used for calibrating the batch of products according to the accuracy, the single-chip calibration reference acceleration time length, a preset reference gear step length, the reference accuracy and the single-chip calibration reference time length.
In a possible example, the obtaining a target gear step length used for calibration of the batch of products according to the accuracy, the single-chip calibration reference acceleration duration, the preset reference gear step length, the reference accuracy, and the single-chip calibration reference duration includes:
updating the gear step SG of the internal output current register by the following formula:
SG= SG0，τ≧τ0，
Figure 199422DEST_PATH_IMAGE001
，
τ﹤τ0，
wherein SG represents the target gear step size, SG0 represents a reference gear step size, SG0 takes the value of 1/10 of the stroke of the internal output current register, τ represents the accuracy, τ 0 represents the reference accuracy, τ 0 takes the value of a value agreed by an industry standard specification, Δ T represents the monolithic calibration reference speed-up duration, and T0 represents the monolithic calibration reference duration.
In one possible example, the internal memory includes any one of: random access memory RAM, double data rate synchronous dynamic random access memory DDR, non-volatile memory NVM.
It can be seen that, in the embodiment of the application, the voltage calibration is directly performed on the IC on the finished product PCB, the calibration deviation caused by the test fixture and the PCB wiring of the conventional calibration method can be eliminated, the calibration precision is effectively improved, the risk of damage to the IC in the disassembly and assembly process of the conventional calibration method is also avoided, the quality of the outgoing IC is more guaranteed, meanwhile, the port on the finished product is utilized to calibrate the finished product after mass production, the shell does not need to be disassembled, the operation is simple and easy, the cost is greatly reduced, and the development period is shortened.
Referring to fig. 3, fig. 3 is a block diagram of functional units of a calibration apparatus for an IC chip according to an embodiment of the present application, wherein the calibration apparatus 300 for an IC chip is applied to the chip calibration system shown in fig. 1; the device comprises:
the disconnection unit 301 is used for controlling the switch K1 and the switch K2 to be disconnected, so that the output is unloaded;
the sampling unit 302 is configured to set a value of an internal output voltage register of the IC chip to VREG1 through the system communication module, and then obtain a current actual output voltage VO1 through the ADC sampling module; setting the value of the internal output voltage register of the IC chip to VREG2 through the system communication module, and then obtaining the current actual output voltage VO2 through the ADC sampling module;
a calculating unit 303, configured to calculate a calibration value of the voltage parameter Voffset and Vstep to be calibrated by using the following formula:
Vstep=（VO2－VO1）÷（VREG2－VREG1），
Voffset=VO1－[（VO2－VO1）÷（VREG2－VREG1）]×VREG1，
wherein an actual output voltage Vo of the IC chip and a value VREG of the internal output voltage register of the IC chip satisfy a first linear relationship, the value of the internal output voltage register corresponding to an internal reference voltage of the IC chip, the first linear relationship satisfying the following formula:
VO= Voffset + Vstep×VREG，
voffset is the drift of the internal output voltage register, and Vstep is the voltage step of the internal output voltage register.
In one possible example, the apparatus further comprises:
a setting unit for setting a value of the internal output voltage register of the IC chip to VREG3 through the system communication module;
the sampling unit is further configured to set a value of an internal output current register of the IC chip to a maximum value, close the switch K1, open the switch K2, obtain a current actual output voltage VO3 through the ADC sampling module, and obtain a current actual output current IO1 through calculation by the following formula:
IO1=VO3÷RL1，
the sampling unit is further configured to set the internal output current register of the IC chip, reduce the internal output current register by steps, and acquire an output voltage, and trigger an overcurrent protection action until the current output voltage is reduced or completely turned off, so as to obtain a currently set value IREG1 of the internal output current register, where the currently set value IREG1 of the internal output current register corresponds to an overcurrent protection OCP point of the current output current;
the sampling unit is further configured to set a value of the internal output current register of the IC chip to a maximum value, open the switch K1, close the switch K2, obtain a current actual output voltage VO4 through the ADC sampling module, and obtain a current actual output current IO2 through calculation according to the following formula:
IO2=VO4÷RL2，
the sampling unit is further configured to set the internal output current register of the IC chip, reduce the internal output current register by steps, and acquire an output voltage, and trigger an overcurrent protection action until the current output voltage is reduced or completely turned off, so as to obtain a currently set value IREG2 of the internal output current register, where the currently set value IREG2 of the internal output current register corresponds to an overcurrent protection OCP point of the current output current;
the calculation unit is used for calculating and obtaining calibration values of current parameters IOffset and Istep to be calibrated through the following formula:
Istep=（IO2－IO1）÷（IREG2－IREG1），
IOffset=IO1－[（IO2－IO1）÷（IREG2－IREG1）]×IREG1，
wherein the actual output current IO of the IC chip and the value IREG of the internal output current register of the IC chip satisfy a second linear relationship, the value of the internal output current register corresponds to the output current when the IC chip reaches an overcurrent protection state, and the second linear relationship satisfies the following formula:
IO= IOffset + Istep×IREG，
the IOffset is the drift of the internal output current register, and the Istep is the current step size of the internal output current register.
In one possible example, the sampling unit is further configured to, before the step-by-step reduction operation: acquiring historical detection data of a plurality of calibrated IC chips on the same production line; and determining a deviation of a target parameter of each of the plurality of IC chips from the historical detection data, the target parameter comprising an output voltage and/or an output current; and determining at least one of the plurality of IC chips having a deviation greater than a preset deviation; and determining an accuracy of the chip calibration system from the at least one IC chip and the plurality of IC chips; determining a single-chip calibration reference acceleration duration set by a user; and obtaining a target gear step length used for calibrating the batch of products according to the accuracy, the single-chip calibration reference acceleration time length, a preset reference gear step length, the reference accuracy and the single-chip calibration reference time length.
In one possible example, the sampling unit is specifically configured to: updating the gear step SG of the internal output current register by the following formula:
SG= SG0，τ≧τ0，
Figure 656948DEST_PATH_IMAGE001
，
τ﹤τ0，
wherein SG represents the target gear step size, SG0 represents a reference gear step size, SG0 takes the value of 1/10 of the stroke of the internal output current register, τ represents the accuracy, τ 0 represents the reference accuracy, τ 0 takes the value of a value agreed by an industry standard specification, Δ T represents the monolithic calibration reference speed-up duration, and T0 represents the monolithic calibration reference duration.
In one possible example, the apparatus further comprises:
and the burning unit is used for burning the calibrated voltage calibration value and/or current calibration value in the internal memory of the IC chip.
In one possible example, the internal memory includes any one of: random access memory RAM, double data rate synchronous dynamic random access memory DDR, non-volatile memory NVM.
It can be understood that, since the method embodiment and the apparatus embodiment are different presentation forms of the same technical concept, the content of the method embodiment portion in the present application should be synchronously adapted to the apparatus embodiment portion, and is not described herein again.
Referring to fig. 4, in accordance with the embodiment shown in fig. 2, fig. 4 is a schematic structural diagram of a calibration circuit 400 according to an embodiment of the present application, and as shown in the figure, the calibration circuit 400 includes a processor 410, a memory 420, an ADC sampling module 430, a system communication module 440, and one or more programs 421, where the one or more programs 421 are stored in the memory 420 and configured to be executed by the application processor 410, and the one or more programs 421 include instructions for executing any step of the method embodiment.
The above description has introduced the solution of the embodiment of the present application mainly from the perspective of the method-side implementation process. It will be appreciated that the calibration circuit, in order to perform the above-described functions, comprises corresponding hardware structures and software modules for performing the respective functions. Those of skill in the art will readily appreciate that the present application is capable of hardware or a combination of hardware and computer software implementing the various illustrative elements and algorithm steps described in connection with the embodiments provided herein. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiment of the present application, the calibration circuit may be divided into functional units according to the above method example, for example, each functional unit may be divided corresponding to each function, or two or more functions may be integrated into one processing unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit. It should be noted that the division of the unit in the embodiment of the present application is schematic, and is only a logic function division, and there may be another division manner in actual implementation.
Embodiments of the present application further provide a chip, where the chip includes a processor, configured to call and run a computer program from a memory, so that a device in which the chip is installed performs some or all of the steps described in the calibration circuit in the above method embodiments.
Embodiments of the present application also provide a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, the computer program enabling a computer to perform part or all of the steps of any one of the methods as described in the above method embodiments, and the computer includes a calibration circuit.
Embodiments of the present application also provide a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods as described in the above method embodiments. The computer program product may be a software installation package, said computer comprising calibration circuitry.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units is only one type of division of logical functions, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit may be stored in a computer readable memory if it is implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a memory, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the above-mentioned method of the embodiments of the present application. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.
The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (14)

1. A calibration method of an Integrated Circuit (IC) chip is characterized in that the calibration method is applied to a calibration circuit in a chip calibration system, the chip calibration system comprises the IC chip assembled on a finished Printed Circuit Board (PCB) and the calibration circuit, the calibration circuit comprises an ADC sampling module, a switch K1, a switch K2, a load resistor RL1, a load resistor RL2, a system communication module and a processor, a voltage output port of the IC chip is connected with a first end of the ADC sampling module, a first end of the switch K1 and a first end of the switch K2, a second end of the switch K1 is connected with a first end of the load resistor RL1, a second end of the switch K2 is connected with a first end of the load resistor RL2, a second end of the ADC sampling module, a second end of the load resistor RL1 and a second end of the load resistor RL2 are combined and then grounded, the processor is connected with the ADC sampling module and the system communication module, the IC chip is connected with the system communication module; the method comprises the following steps:
controlling the switch K1 and the switch K2 to be switched off, so that the output is unloaded;
setting the value of an internal output voltage register of the IC chip to VREG1 through the system communication module, and then obtaining the current actual output voltage VO1 through the ADC sampling module;
setting the value of the internal output voltage register of the IC chip to VREG2 through the system communication module, and then obtaining the current actual output voltage VO2 through the ADC sampling module;
the calibration values of the voltage parameters Voffset and Vstep to be calibrated are calculated by the following formula:
Vstep=（VO2－VO1）÷（VREG2－VREG1），
Voffset=VO1－[（VO2－VO1）÷（VREG2－VREG1）]×VREG1，
wherein an actual output voltage VO of the IC chip and a value VREG of the internal output voltage register of the IC chip satisfy a first linear relationship, the value of the internal output voltage register corresponding to an internal reference voltage of the IC chip, the first linear relationship satisfying the following formula:
VO= Voffset + Vstep×VREG，
voffset is the drift of the internal output voltage register, and Vstep is the voltage step size of the internal output voltage register;
the method further comprises the following steps:
setting a value of the internal output voltage register of the IC chip to VREG3 through the system communication module;
setting the value of an internal output current register of the IC chip as a maximum value, closing the switch K1, opening the switch K2, obtaining the current actual output voltage VO3 through the ADC sampling module, and calculating the current actual output current IO1 through the following formula:
IO1=VO3÷RL1，
setting the internal output current register of the IC chip, reducing and collecting output voltage step by step, triggering an overcurrent protection action until the current output voltage is reduced or completely closed, and obtaining a value IREG1 of the currently set internal output current register, wherein the value IREG1 of the currently set internal output current register corresponds to an overcurrent protection OCP point of the current output current;
setting the value of the internal output current register of the IC chip as a maximum value, opening the switch K1, closing the switch K2, obtaining the current actual output voltage VO4 through the ADC sampling module, and calculating the current actual output current IO2 through the following formula:
IO2=VO4÷RL2，
setting the internal output current register of the IC chip, reducing and collecting output voltage step by step, triggering an overcurrent protection action until the current output voltage is reduced or completely closed, and obtaining a value IREG2 of the currently set internal output current register, wherein the value IREG2 of the currently set internal output current register corresponds to an overcurrent protection OCP point of the current output current;
the calibration values of the current parameters IOffset and Istep to be calibrated are calculated by the following formula:
Istep=（IO2－IO1）÷（IREG2－IREG1），
IOffset=IO1－[（IO2－IO1）÷（IREG2－IREG1）]×IREG1，
wherein the actual output current IO of the IC chip and the value IREG of the internal output current register of the IC chip satisfy a second linear relationship, the value of the internal output current register corresponds to the output current when the IC chip reaches an overcurrent protection state, and the second linear relationship satisfies the following formula:
IO= IOffset + Istep×IREG，
the IOffset is the drift of the internal output current register, and the Istep is the current step size of the internal output current register.
2. The method of claim 1, wherein prior to the operation of the gear-wise reduction, the method further comprises:
acquiring historical detection data of a plurality of calibrated IC chips on the same production line;
determining a deviation of a target parameter of each of the plurality of IC chips from the historical inspection data, the target parameter comprising an output voltage and/or an output current;
determining at least one IC chip of the plurality of IC chips, the deviation of which is greater than a preset deviation;
determining an accuracy of the chip calibration system from the at least one IC chip and the plurality of IC chips;
determining a single-chip calibration reference acceleration duration set by a user;
and obtaining a target gear step length used for calibrating the batch of products according to the accuracy, the single-chip calibration reference acceleration time length, a preset reference gear step length, the reference accuracy and the single-chip calibration reference time length.
3. The method of claim 2, wherein obtaining a target gear step size for calibration of the batch of products according to the accuracy, the single calibration reference speed-up duration, the preset reference gear step size, the reference accuracy and the single calibration reference duration comprises:
updating the target gear step SG of the internal output current register by the following formula:
SG= SG0，τ≧τ0，
SG= SG0－[1+3ln(1+100×|τ－τ0|) ]+2|ΔT÷T0|，τ﹤τ0，
wherein SG represents the target gear step size, SG0 represents a reference gear step size, SG0 takes the value of 1/10 of the stroke of the internal output current register, τ represents the accuracy, τ 0 represents the reference accuracy, τ 0 takes the value of a value agreed by an industry standard specification, Δ T represents the monolithic calibration reference speed-up duration, and T0 represents the monolithic calibration reference duration.
4. The method according to any one of claims 1-3, further comprising:
and programming the calibrated voltage calibration value and/or current calibration value in an internal memory of the IC chip.
5. The method of claim 4, wherein the internal memory comprises any one of: random access memory RAM, double data rate synchronous dynamic random access memory DDR, non-volatile memory NVM.
6. A calibration circuit for use in a chip calibration system comprising an IC chip mounted on a finished printed circuit board PCB and the calibration circuit, the calibration circuit comprising an ADC sampling module, a switch K1, a switch K2, a load resistance RL1, a load resistance RL2, a system communication module, and a processor;
the voltage output port of the IC chip is connected with the first end of the ADC sampling module, the first end of the switch K1 and the first end of the switch K2, the second end of the switch K1 is connected with the first end of the load resistor RL1, the second end of the switch K2 is connected with the first end of the load resistor RL2, the second end of the ADC sampling module, the second end of the load resistor RL1 and the second end of the load resistor RL2 are grounded after being combined, the processor is connected with the ADC sampling module and the system communication module, and the IC chip is connected with the system communication module;
the calibration circuit is used for controlling the switch K1 and the switch K2 to be switched off, so that the output is unloaded;
the system communication module is used for setting the value of an internal output voltage register of the IC chip to VREG1, and then the ADC sampling module is used for obtaining the current actual output voltage VO 1;
the system communication module is used for setting the value of the internal output voltage register of the IC chip to VREG2, and then the ADC sampling module is used for obtaining the current actual output voltage VO 2;
and the calibration value for the voltage parameters Voffset and Vstep to be calibrated is calculated by the following formula:
Vstep=（VO2－VO1）÷（VREG2－VREG1），
Voffset=VO1－[（VO2－VO1）÷（VREG2－VREG1）]×VREG1，
wherein an actual output voltage VO of the IC chip and a value VREG of the internal output voltage register of the IC chip satisfy a first linear relationship, the value of the internal output voltage register corresponding to an internal reference voltage of the IC chip, the first linear relationship satisfying the following formula:
VO= Voffset + Vstep×VREG
voffset is the drift of the internal output voltage register, and Vstep is the voltage step size of the internal output voltage register;
the calibration circuit is further used for setting the value of the internal output voltage register of the IC chip to VREG3 through the system communication module; setting the value of an internal output current register of the IC chip as a maximum value, closing the switch K1, opening the switch K2, obtaining the current actual output voltage VO3 through the ADC sampling module, and calculating the current actual output current IO1 through the following formula:
IO1=VO3÷RL1，
setting the internal output current register of the IC chip, reducing and collecting output voltage step by step, triggering an overcurrent protection action until the current output voltage is reduced or completely closed, and obtaining a value IREG1 of the currently set internal output current register, wherein the value IREG1 of the currently set internal output current register corresponds to an overcurrent protection OCP point of the current output current; setting the value of the internal output current register of the IC chip as a maximum value, opening the switch K1, closing the switch K2, obtaining the current actual output voltage VO4 through the ADC sampling module, and calculating the current actual output current IO2 through the following formula:
IO2=VO4÷RL2，
setting the internal output current register of the IC chip, reducing and collecting output voltage step by step, triggering an overcurrent protection action until the current output voltage is reduced or completely closed, and obtaining a value IREG2 of the currently set internal output current register, wherein the value IREG2 of the currently set internal output current register corresponds to an overcurrent protection OCP point of the current output current;
the calibration values of the current parameters IOffset and Istep to be calibrated are calculated by the following formula:
Istep=（IO2－IO1）÷（IREG2－IREG1），
IOffset=IO1－[（IO2－IO1）÷（IREG2－IREG1）]×IREG1，
wherein the actual output current IO of the IC chip and the value IREG of the internal output current register of the IC chip satisfy a second linear relationship, the value of the internal output current register corresponds to the output current when the IC chip reaches an overcurrent protection state, and the second linear relationship satisfies the following formula:
IO= IOffset + Istep×IREG，
the IOffset is the drift of the internal output current register, and the Istep is the current step size of the internal output current register.
7. The calibration circuit of claim 6, further configured to obtain historical inspection data of the plurality of calibrated IC chips on the same production line before the step-by-step reduction operation of the calibration circuit; and determining a deviation of a target parameter of each of the plurality of IC chips from the historical detection data, the target parameter comprising an output voltage and/or an output current; and determining at least one of the plurality of IC chips having a deviation greater than a preset deviation; and determining an accuracy of the chip calibration system from the at least one IC chip and the plurality of IC chips; determining a single-chip calibration reference acceleration duration set by a user; and obtaining a target gear step length used for calibrating the batch of products according to the accuracy, the single-chip calibration reference acceleration time length, a preset reference gear step length, the reference accuracy and the single-chip calibration reference time length.
8. The calibration circuit of claim 7, wherein in obtaining the target gear step size for calibration of the batch of products according to the accuracy, the single-chip calibration reference speed-up duration, the preset reference gear step size, the reference accuracy, and the single-chip calibration reference duration, the calibration circuit is specifically configured to:
updating the target gear step SG of the internal output current register by the following formula:
SG= SG0，τ≧τ0，
SG= SG0－[1+3ln(1+100×|τ－τ0|) ]+2|ΔT÷T0|，τ﹤τ0，
wherein SG represents the target gear step size, SG0 represents a reference gear step size, SG0 takes the value of 1/10 of the stroke of the internal output current register, τ represents the accuracy, τ 0 represents the reference accuracy, τ 0 takes the value of a value agreed by an industry standard specification, Δ T represents the monolithic calibration reference speed-up duration, and T0 represents the monolithic calibration reference duration.
9. The calibration circuit of any of claims 6-8, wherein the calibration circuit is further configured to: and programming the calibrated voltage calibration value and/or current calibration value in an internal memory of the IC chip.
10. The calibration circuit of claim 9, wherein the internal memory comprises any one of: random access memory RAM, double data rate synchronous dynamic random access memory DDR, non-volatile memory NVM.
11. A calibration device of an IC chip is applied to a calibration circuit in a chip calibration system, the chip calibration system comprises the IC chip assembled on a finished Printed Circuit Board (PCB) and the calibration circuit, the calibration circuit comprises an ADC sampling module, a switch K1, a switch K2, a load resistor RL1, a load resistor RL2, a system communication module and a processor, a voltage output port of the IC chip is connected with a first end of the ADC sampling module, a first end of the switch K1 and a first end of the switch K2, a second end of the switch K1 is connected with a first end of the load resistor RL1, a second end of the switch K2 is connected with a first end of the load resistor RL2, a second end of the ADC sampling module, a second end of the load resistor RL1 and a second end of the load resistor RL2 are combined and then grounded, and the processor is connected with the ADC sampling module and the system communication module, the IC chip is connected with the system communication module; the device comprises:
the disconnection unit is used for controlling the disconnection of the switch K1 and the switch K2 so as to enable the output to be unloaded;
the sampling unit is used for setting the value of an internal output voltage register of the IC chip to VREG1 through the system communication module and then obtaining the current actual output voltage VO1 through the ADC sampling module; setting the value of the internal output voltage register of the IC chip to VREG2 through the system communication module, and then obtaining the current actual output voltage VO2 through the ADC sampling module;
a calculating unit, configured to calculate calibration values of the voltage parameters Voffset and Vstep to be calibrated by using the following formulas:
Vstep=（VO2－VO1）÷（VREG2－VREG1），
Voffset=VO1－[（VO2－VO1）÷（VREG2－VREG1）]×VREG1，
wherein an actual output voltage VO of the IC chip and a value VREG of the internal output voltage register of the IC chip satisfy a first linear relationship, the value of the internal output voltage register corresponding to an internal reference voltage of the IC chip, the first linear relationship satisfying the following formula:
VO= Voffset + Vstep×VREG，
voffset is the drift of the internal output voltage register, and Vstep is the voltage step size of the internal output voltage register;
the device further comprises:
a setting unit for setting a value of the internal output voltage register of the IC chip to VREG3 through the system communication module;
the sampling unit is further configured to set a value of an internal output current register of the IC chip to a maximum value, close the switch K1, open the switch K2, obtain a current actual output voltage VO3 through the ADC sampling module, and obtain a current actual output current IO1 through calculation by the following formula:
IO1=VO3÷RL1，
the sampling unit is further configured to set the internal output current register of the IC chip, reduce the internal output current register by steps, and acquire an output voltage, and trigger an overcurrent protection action until the current output voltage is reduced or completely turned off, so as to obtain a currently set value IREG1 of the internal output current register, where the currently set value IREG1 of the internal output current register corresponds to an overcurrent protection OCP point of the current output current;
the sampling unit is further configured to set a value of the internal output current register of the IC chip to a maximum value, open the switch K1, close the switch K2, obtain a current actual output voltage VO4 through the ADC sampling module, and obtain a current actual output current IO2 through calculation according to the following formula:
IO2=VO4÷RL2，
the sampling unit is further configured to set the internal output current register of the IC chip, reduce the internal output current register by steps, and acquire an output voltage, and trigger an overcurrent protection action until the current output voltage is reduced or completely turned off, so as to obtain a currently set value IREG2 of the internal output current register, where the currently set value IREG2 of the internal output current register corresponds to an overcurrent protection OCP point of the current output current;
the calculation unit is used for calculating and obtaining calibration values of current parameters IOffset and Istep to be calibrated through the following formula:
Istep=（IO2－IO1）÷（IREG2－IREG1），
IOffset=IO1－[（IO2－IO1）÷（IREG2－IREG1）]×IREG1，
wherein the actual output current IO of the IC chip and the value IREG of the internal output current register of the IC chip satisfy a second linear relationship, the value of the internal output current register corresponds to the output current when the IC chip reaches an overcurrent protection state, and the second linear relationship satisfies the following formula:
IO= IOffset + Istep×IREG，
the IOffset is the drift of the internal output current register, and the Istep is the current step size of the internal output current register.
12. A calibration circuit comprising a processor, a memory, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing the steps in the method of any of claims 1-5.
13. A quick-charging chip, which is an IC chip and is applied to the calibration method of the IC chip as claimed in any one of claims 1 to 5.
14. A computer-readable storage medium, characterized in that a computer program for electronic data exchange is stored, wherein the computer program causes a computer to perform the method according to any one of claims 1-5.
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