CN111916540A - LED chip with epitaxial insertion layer and manufacturing method thereof - Google Patents

LED chip with epitaxial insertion layer and manufacturing method thereof Download PDF

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Publication number
CN111916540A
CN111916540A CN202010961660.1A CN202010961660A CN111916540A CN 111916540 A CN111916540 A CN 111916540A CN 202010961660 A CN202010961660 A CN 202010961660A CN 111916540 A CN111916540 A CN 111916540A
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layer
led chip
epitaxial
insertion layer
substrate
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霍丽艳
吴洪浩
崔晓慧
彭露
刘兆
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Jiangxi Qianzhao Photoelectric Co ltd
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Jiangxi Qianzhao Photoelectric Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

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Abstract

The invention provides an LED chip with an epitaxial insertion layer and a manufacturing method thereof, wherein the epitaxial insertion layer is arranged at the tip position of V-pits, so that on one hand, the density and the size of the V-pits can be controlled, the V-pits are modulated, the non-radiative recombination of carriers is reduced, and the internal quantum efficiency is improved; on the other hand, the impedance at the V-pits tip can be increased, the breakdown of electrons at the threading dislocation position is reduced, the electric leakage is reduced, and the electric performance of the LED chip is improved; meanwhile, the surface of the epitaxial insertion layer adjacent to the shallow well layer is a rough surface, so that the light emitting angle of the LED chip can be changed, and the external quantum efficiency is improved.

Description

LED chip with epitaxial insertion layer and manufacturing method thereof
Technical Field
The invention relates to the technical field of LEDs, in particular to an LED chip with an epitaxial insertion layer and a manufacturing method thereof.
Background
GaN is used as a third-generation semiconductor material, and has a wide range of applications, such as solid-state lighting, liquid crystal display backlight sources, automobile lamps, and the like.
It is well known that the improvement of the luminous efficiency of the LED is a constant goal pursued by those skilled in the art. However, in the InGaN/GaN LED, due to the large lattice mismatch, the polarization effect is strong, the wave functions of electrons and holes are spatially separated, the recombination probability of the electrons and the holes is reduced, and the light emitting efficiency is further reduced. Secondly, since the mobility of the holes is much lower than that of the electrons, the mobility diffusion length of the holes in the quantum well is limited, which is also a main factor limiting the light efficiency of the LED. Finally, as the injected current increases, the luminous efficiency decreases significantly, i.e. the so-called "drop" effect, is also a major factor limiting the luminous efficiency of LEDs.
In recent years, the light efficiency of the LED can be effectively improved by the V-pits (V-pits) caused by the TD. As is known, the MQW structure with V-pits, the semipolar MQW structure formed in the (10-11) direction, can increase the light-emitting area of the LED, increase the channel of hole injection quantum well, can increase the diffusion length of the hole, raise the luminous efficiency.
However, the V-pits have negative effects while improving the optical efficiency, for example, the threading dislocation at the tip of the V-pits easily causes leakage, and carriers are easily non-radiatively recombined in the threading dislocation, thereby affecting the optical efficiency.
Disclosure of Invention
In view of the above, to solve the above problems, the present invention provides an LED chip with an epitaxial insertion layer and a manufacturing method thereof, and the technical solution is as follows:
an LED chip having an epitaxial insertion layer, the LED chip comprising:
a substrate;
the N-type semiconductor layer, the low-doped N-type gallium nitride layer, the shallow well layer, the multi-quantum well layer and the P-type semiconductor layer are sequentially arranged on the substrate in a first direction, and the first direction is perpendicular to the substrate and points to the N-type semiconductor layer from the substrate;
and the epitaxial insertion layer is arranged between the low-doped N-type gallium nitride layer and the shallow well layer.
Optionally, in the LED chip, the epitaxial insertion layer is a high resistance layer.
Optionally, in the LED chip, a surface of the epitaxial insertion layer is a rough surface.
Optionally, in the LED chip, the epitaxial insertion layer is an undoped gallium nitride layer.
Optionally, in the LED chip, the epitaxial insertion layer is a superlattice structure composed of GaN/AlN or GaN/AlGaN;
wherein the Al component is 0.005-0.01.
Optionally, in the LED chip, the epitaxial insertion layer is a multilayer undoped GaN overlapping structure with different growth rates;
or, multilayer GaN/AlGaN overlapped structures with different growth rates;
or, multilayer GaN/AlN overlap structures with different growth rates.
Optionally, in the LED chip, the growth temperature of the epitaxial insertion layer is 700 ℃ to 900 ℃.
Optionally, in the LED chip, a growth rate of the epitaxial insertion layer is 0.3 μm/h to 1 μm/h.
Optionally, in the LED chip, the thickness of the epitaxial insertion layer is 2nm to 30 nm.
A method of fabricating an LED chip with an epitaxial insertion layer, the method of fabrication comprising:
providing a substrate;
and sequentially growing an N-type semiconductor layer, a low-doped N-type gallium nitride layer, an epitaxial insertion layer, a shallow well layer, a multi-quantum well layer and a P-type semiconductor layer on the substrate in a first direction, wherein the first direction is vertical to the substrate and points to the N-type semiconductor layer from the substrate.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides an LED chip with an epitaxial insertion layer, which comprises: a substrate; the N-type semiconductor layer, the low-doped N-type gallium nitride layer, the shallow well layer, the multi-quantum well layer and the P-type semiconductor layer are sequentially arranged on the substrate in a first direction, and the first direction is perpendicular to the substrate and points to the N-type semiconductor layer from the substrate; and the epitaxial insertion layer is arranged between the low-doped N-type gallium nitride layer and the shallow well layer. Namely, the epitaxial insertion layer is positioned at the tip position of the V-pits, so that on one hand, the density and the size of the V-pits can be controlled, the V-pits are modulated, the non-radiative recombination of carriers is reduced, and the internal quantum efficiency is improved; on the other hand, the impedance at the V-pits tip can be increased, the breakdown of electrons at the threading dislocation position is reduced, the electric leakage is reduced, and the electric performance of the LED chip is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an LED chip with an epitaxial insertion layer according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another LED chip with an epitaxial insertion layer according to an embodiment of the present invention;
fig. 3 is a schematic flowchart of a method for manufacturing an LED chip with an epitaxial insertion layer according to an embodiment of the present invention;
FIG. 4 is an IR electrical diagram of an LED chip according to an embodiment of the present invention;
fig. 5 is a schematic diagram of brightness of an LED chip under different current densities according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an LED chip with an epitaxial insertion layer according to an embodiment of the present invention.
The LED chip includes:
a substrate 11.
The N-type semiconductor layer 12, the low-doped N-type gallium nitride layer 13, the shallow well layer 15, the multiple quantum well layer 16 and the P-type semiconductor layer 17 are sequentially arranged on the substrate 11 in a first direction, the first direction is perpendicular to the substrate 11, and the N-type semiconductor layer 12 is pointed by the substrate 11.
And an epitaxial insertion layer 14 arranged between the low-doped N-type gallium nitride layer 13 and the shallow well layer 15.
The low-doped N-type gan layer 13 is also referred to as an LD layer, and the shallow well layer 15 is also referred to as an SL layer.
In the embodiment, the epitaxial insertion layer 14 is arranged at the tip position of the V-pits, so that on one hand, the density and the size of the V-pits can be controlled, the V-pits are modulated, the non-radiative recombination of carriers is reduced, and the internal quantum efficiency is improved; on the other hand, the impedance at the V-pits tip can be increased, the breakdown of electrons at the threading dislocation position is reduced, the electric leakage is reduced, and the electric performance of the LED chip is improved.
Optionally, the N-type semiconductor layer 12 is an N-type gallium nitride layer.
Optionally, the P-type semiconductor layer 17 is a P-type gallium nitride layer.
Optionally, referring to fig. 2, fig. 2 is a schematic structural diagram of another LED chip with an epitaxial insertion layer according to an embodiment of the present invention.
The LED chip further includes:
a buffer layer 18 and a U-type gallium nitride layer 19 are sequentially disposed between the substrate 11 and the N-type semiconductor layer 12 in the first direction.
Wherein the U-type gallium nitride layer 19 is used for adjusting lattice mismatch between the N-type semiconductor layer 12 and the substrate 11.
Further, according to the above embodiment of the present invention, the epitaxial insertion layer 14 is a high resistance layer.
In this embodiment, the epitaxial insertion layer 14 is configured as a high resistance layer, which can increase the impedance at the tip of the V-pits, reduce the breakdown of electrons at the threading dislocation, reduce the leakage current, and improve the electrical performance of the LED chip.
Further, according to the above embodiment of the present invention, the surface of the epitaxial insertion layer 14 is rough.
Specifically, the surface of the epitaxial insertion layer 14 adjacent to the shallow well layer 15 is a rough surface.
In this embodiment, since the surface of the epitaxial insertion layer 14 adjacent to the shallow well layer 15 is a rough surface, the light-emitting angle of the LED chip can be changed, and the external quantum efficiency can be improved.
Further, according to the above embodiment of the present invention, the epitaxial insertion layer 14 is an undoped gallium nitride layer.
In this embodiment, the epitaxial-layer insertion layer 14 may be a single undoped gallium nitride layer, or may be a stacked structure of a plurality of undoped gallium nitride layers.
Further, according to the above embodiment of the present invention, the epitaxial insertion layer 14 has a superlattice structure composed of GaN/AlN or GaN/AlGaN.
Wherein the Al component is 0.005-0.01.
In this embodiment, a GaN layer is adjacent to the low N-doped gallium nitride layer 13.
Further, based on the above embodiment of the present invention, the epitaxial insertion layer 14 is a multi-layer undoped GaN stacked structure with different growth rates.
Or, multilayer GaN/AlGaN overlap structures with different growth rates.
Or, multilayer GaN/AlN overlap structures with different growth rates.
In this embodiment, the size and density of the V-pits can be controlled by controlling the growth rate of the epitaxial insertion layer 14, which acts as a modulation for the V-pits, reduces non-radiative recombination of carriers, and improves internal quantum efficiency.
Further, according to the above embodiment of the present invention, the growth temperature of the epitaxial insertion layer 14 is 700 ℃ -900 ℃.
In this embodiment, the growth temperature of the epitaxial insertion layer 14 is 730 ℃, 810 ℃, 867 ℃ or the like.
Further, based on the above embodiment of the present invention, the growth rate of the epitaxial insertion layer 14 is 0.3 μm/h to 1 μm/h.
In this embodiment, the growth rate of the epitaxial insertion layer 14 is 0.5 μm/h or 0.7 μm/h or 0.9 μm/h, etc.
Further, according to the above embodiment of the present invention, the thickness of the epitaxial insertion layer 14 is 2nm to 30 nm.
In this embodiment, the thickness of the epitaxial insertion layer 14 is 9nm or 10nm or 16nm or 23nm or 27nm, etc.
Further, based on all the above embodiments of the present invention, in another embodiment of the present invention, a method for manufacturing an LED chip with an epitaxial insertion layer is further provided, and referring to fig. 3, fig. 3 is a schematic flow chart of the method for manufacturing an LED chip with an epitaxial insertion layer according to the embodiment of the present invention.
The manufacturing method comprises the following steps:
s101: a substrate 11 is provided.
In this step, the substrate 11 includes, but is not limited to, a PSS AlN-plated substrate, a sapphire substrate, or the like.
S102: an N-type semiconductor layer 12, a low-doped N-type gallium nitride layer 13, an epitaxial insertion layer 14, a shallow well layer 15, a multi-quantum well layer 16 and a P-type semiconductor layer 17 are sequentially grown on the substrate 11 in a first direction, wherein the first direction is perpendicular to the substrate 11 and is directed to the N-type semiconductor layer 12 from the substrate 11.
In this step, before growing the N-type semiconductor layer 12, a buffer layer 18 and a U-type gallium nitride layer 19 are sequentially grown on the substrate 11 along the first direction.
In particular, the following examples are given in several different ways of fabrication:
a first LED chip fabrication method provides an LED chip that does not include an epitaxial layer insertion layer:
using MOCVD equipment, using MO source metal source, trimethyl gallium TMGa, triethyl gallium TEGa, trimethyl TMIn, magnesium cyclopentadienyl (CP2Mg), trimethyl aluminum (TMAl), TMGa and TEGa as Ga source, and gas source Silane (SiH)4) Ammonia (NH)3)、H2、N2Wherein NH3Is a source of N, H2、N2As carrier gas, the N-type and P-type doping sources are respectively SiH4And magnesium dicocene CP2Mg, AlN substrate plated with PSS.
Heating to 1100 deg.C, performing hydrogenation treatment for 5min to remove surface impurities, etc., and cleaning the substrate.
Introducing TMGa to grow a buffer layer with the growth thickness of 2nm and the growth temperature of 800 ℃.
Introducing TMGa to grow a U-shaped gallium nitride layer, wherein the growth thickness is 2300nm, and the growth temperature is 1120 ℃.
Introducing TMGa and SiH4Growing an N-type semiconductor layer (N-type GaN layer) at 1070 deg.C and SiH to a thickness of 2000nm4Has a concentration of 2E19/cm3。
Introducing TMGa and SiH4Growing a low-doped N-type gallium nitride layer (LD layer) at 1070 deg.C and 150nm in thickness and SiH4Has a concentration of 4E17/cm3。
Introducing TEGa, TMIn and SiH4And growing a multi-quantum well layer with the total growth thickness of 140nm, wherein the growth temperature of the well is 770 ℃, and the growth temperature of the barrier is 880 ℃.
Introducing TMGa and CP2Mg to grow a P-type semiconductor layer (P-type GaN layer) with a thickness of 0.4 μm, a growth temperature of 950 ℃ and a Mg concentration of 2E19/cm3。
A second LED chip fabrication method provides an LED chip including an epitaxial layer insertion layer:
using MOCVD equipment, using MO source metal source, trimethyl gallium TMGa, triethyl gallium TEGa, trimethyl TMIn, magnesium cyclopentadienyl (CP2Mg), trimethyl aluminum (TMAl), TMGa and TEGa as Ga source, and gas source Silane (SiH)4) Ammonia (NH)3)、H2、N2Wherein NH3Is a source of N, H2、N2As carrier gas, the N-type and P-type doping sources are respectively SiH4And magnesium dicocene CP2Mg, AlN substrate plated with PSS.
Heating to 1100 deg.C, performing hydrogenation treatment for 5min to remove surface impurities, etc., and cleaning the substrate.
Introducing TMGa to grow a buffer layer with the growth thickness of 2nm and the growth temperature of 800 ℃.
Introducing TMGa to grow a U-shaped gallium nitride layer, wherein the growth thickness is 2300nm, and the growth temperature is 1120 ℃.
Introducing TMGa and SiH4Growing an N-type semiconductor layer (N-type GaN layer) at 1070 deg.C and SiH to a thickness of 2000nm4Has a concentration of 2E19/cm3。
Introducing TMGa and SiH4Growing a low-doped N-type gallium nitride layer (LD layer) at 1070 deg.C and 150nm in thickness and SiH4Has a concentration of 4E17/cm3。
Introducing TEGa, and growing an epitaxial insertion layer at 880 ℃ (700-900 ℃) for 3nm (2-30 nm) for 3min (1-8 min).
Introducing TEGa, TMIn and SiH4And growing a multi-quantum well layer with the total growth thickness of 140nm, wherein the growth temperature of the well is 770 ℃, and the growth temperature of the barrier is 880 ℃.
Introducing TMGa and CP2Mg to grow a P-type semiconductor layer (P-type GaN layer) with a thickness of 0.4 μm, a growth temperature of 950 ℃ and a Mg concentration of 2E19/cm3。
Specifically, referring to fig. 4, fig. 4 is an IR electrical schematic diagram of an LED chip according to an embodiment of the present invention. Compared with the first LED chip manufacturing method, the second LED chip manufacturing method has the advantages that after the epitaxial insertion layer is added, the IR (electric leakage) yield of the LED chip is remarkably improved, and the epitaxial insertion layer is a non-doped semiconductor, so that the impedance is higher compared with a doped semiconductor, the current expansion can be improved, the breakdown of electrons at the threading dislocation position is reduced, the electric leakage is reduced, and the electrical property of the LED chip is improved.
Meanwhile, in the production process, the epitaxial insertion layer can play a role in modulating the density and the size of the V-pits, and the electrical difference caused by the size of the contrast pattern is reduced.
Referring to fig. 5, fig. 5 is a schematic diagram of the brightness of an LED chip under different current densities according to an embodiment of the present invention.
After the epitaxial insertion layer is added, the brightness of the LED chip is improved, the surface of the epitaxial insertion layer is rough through surface AFM photograph display, the light-emitting angle of the LED chip can be changed, total reflection of light in an LED material is reduced, the external quantum efficiency of the LED chip is improved, in addition, the epitaxial insertion layer is arranged at the tip position of V-pits, the non-radiative recombination of carriers can be reduced, and the internal quantum efficiency is improved.
The third LED chip fabrication method provides an LED chip including an epitaxial layer insertion layer:
using MOCVD equipment, using MO source metal source, trimethyl gallium TMGa, triethyl gallium TEGa, trimethyl TMIn, magnesium cyclopentadienyl (CP2Mg), trimethyl aluminum (TMAl), TMGa and TEGa as Ga source, and gas source Silane (SiH)4) Ammonia (NH)3)、H2、N2Wherein NH3Is a source of N, H2、N2As carrier gas, the N-type and P-type doping sources are respectively SiH4And magnesium dicocene CP2Mg, AlN substrate plated with PSS.
Heating to 1100 deg.C, performing hydrogenation treatment for 5min to remove surface impurities, etc., and cleaning the substrate.
Introducing TMGa to grow a buffer layer with the growth thickness of 2nm and the growth temperature of 800 ℃.
Introducing TMGa to grow a U-shaped gallium nitride layer, wherein the growth thickness is 2300nm, and the growth temperature is 1120 ℃.
Introducing TMGa and SiH4Growing an N-type semiconductor layer (N-type GaN layer) at 1070 deg.C and SiH to a thickness of 2000nm4Has a concentration of 2E19/cm3。
Introducing TMGa and SiH4Growing a low-doped N-type gallium nitride layer (LD layer) at 1070 deg.C and 150nm in thickness and SiH4Has a concentration of 4E17/cm3。
Introducing TEGa, and growing an epitaxial insertion layer at 880 ℃ (700-900 ℃), with a growth thickness of 5nm (2-30 nm) and a growth time of 3min (1-8 min).
Introducing TEGa, TMGa, TMIn and SiH4And a shallow well layer (SL layer) is grown, and the total growth thickness is 230 um.
Introducing TEGa, TMIn and SiH4And growing a multi-quantum well layer with the total growth thickness of 140nm, wherein the growth temperature of the well is 770 ℃, and the growth temperature of the barrier is 880 ℃.
Introducing TMGa and CP2Mg to grow a P-type semiconductor layer (P-type GaN layer) with a thickness of 0.4 μm, a growth temperature of 950 ℃ and a Mg concentration of 2E19/cm3。
Specifically, by comparing the third LED chip manufacturing method with the second LED chip manufacturing method, the thickness of the epitaxial insertion layer is thickened, so that the density of the V-pits is reduced, the size of the V-pits is reduced, and the size and the density of the V-pits can be regulated and controlled according to the process to meet actual requirements.
A fourth LED chip fabrication method, providing an LED chip comprising an epitaxial layer insertion layer:
using MOCVD equipment, using MO source metal source, trimethyl gallium TMGa, triethyl gallium TEGa, trimethyl TMIn, magnesium cyclopentadienyl (CP2Mg), trimethyl aluminum (TMAl), TMGa and TEGa as Ga source, and gas source Silane (SiH)4) Ammonia (NH)3)、H2、N2Wherein NH3Is a source of N, H2、N2As carrier gas, the N-type and P-type doping sources are respectively SiH4And magnesium dicocene CP2Mg, AlN substrate plated with PSS.
Heating to 1100 deg.C, performing hydrogenation treatment for 5min to remove surface impurities, etc., and cleaning the substrate.
Introducing TMGa to grow a buffer layer with the growth thickness of 2nm and the growth temperature of 800 ℃.
Introducing TMGa to grow a U-shaped gallium nitride layer, wherein the growth thickness is 2300nm, and the growth temperature is 1120 ℃.
Introducing TMGa and SiH4Growing an N-type semiconductor layer (N-type GaN layer) at 1070 deg.C and SiH to a thickness of 2000nm4Has a concentration of 2E19/cm3。
Introducing TMGa and SiH4Growing a low-doped N-type gallium nitride layer (LD layer) at 1070 deg.C and 150nm in thickness and SiH4Has a concentration of 4E17/cm3。
Introducing TEGa to grow the epitaxial insertion layer, wherein the growth temperature is 780 ℃ (the growth temperature range is 700 ℃ -900 ℃), the growth thickness is 3nm (the growth thickness range is 2nm-30nm), and the growth time is 3min (the growth time range is 1min-8 min).
Introducing TEGa, TMGa, TMIn and SiH4And a shallow well layer (SL layer) is grown, and the total growth thickness is 230 um.
Introducing TEGa, TMIn and SiH4And growing a multi-quantum well layer with the total growth thickness of 140nm, wherein the growth temperature of the well is 770 ℃, and the growth temperature of the barrier is 880 ℃.
Introducing TMGa and CP2Mg to grow a P-type semiconductor layer (P-type GaN layer) with a thickness of 0.4 μm, a growth temperature of 950 ℃ and a Mg concentration of 2E19/cm3。
Specifically, by comparing the fourth LED chip manufacturing method with the second LED chip manufacturing method, the growth temperature of the epitaxial insertion layer is reduced, the surface of the epitaxial insertion layer can be rougher, the density of V-pits can be increased, and therefore the density of V-pits and the roughness of the epitaxial insertion layer can be regulated according to the process so as to meet actual requirements.
The LED chip with an epitaxial insertion layer and the method for manufacturing the same provided by the present invention are described in detail above, and the principle and the implementation of the present invention are explained herein by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include or include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. An LED chip with an epitaxial insertion layer, the LED chip comprising:
a substrate;
the N-type semiconductor layer, the low-doped N-type gallium nitride layer, the shallow well layer, the multi-quantum well layer and the P-type semiconductor layer are sequentially arranged on the substrate in a first direction, and the first direction is perpendicular to the substrate and points to the N-type semiconductor layer from the substrate;
and the epitaxial insertion layer is arranged between the low-doped N-type gallium nitride layer and the shallow well layer.
2. The LED chip of claim 1, wherein said epitaxial insertion layer is a high resistance layer.
3. The LED chip of claim 1, wherein the surface of said epitaxial insertion layer is roughened.
4. The LED chip of claim 1, wherein said epitaxial insertion layer is an undoped gallium nitride layer.
5. The LED chip of claim 1, wherein said epitaxial insertion layer is a superlattice structure composed of GaN/AlN or GaN/AlGaN;
wherein the Al component is 0.005-0.01.
6. The LED chip of claim 1, wherein said epitaxial insertion layer is a multilayer undoped GaN overlap structure with different growth rates;
or, multilayer GaN/AlGaN overlapped structures with different growth rates;
or, multilayer GaN/AlN overlap structures with different growth rates.
7. The LED chip of claim 1, wherein the growth temperature of said epitaxial insertion layer is 700 ℃ -900 ℃.
8. The LED chip of claim 1, wherein said epitaxial insertion layer has a growth rate of 0.3 μ ι η/h to 1 μ ι η/h.
9. The LED chip of claim 1, wherein said epitaxial insertion layer has a thickness of 2nm to 30 nm.
10. A manufacturing method of an LED chip with an epitaxial insertion layer is characterized by comprising the following steps:
providing a substrate;
and sequentially growing an N-type semiconductor layer, a low-doped N-type gallium nitride layer, an epitaxial insertion layer, a shallow well layer, a multi-quantum well layer and a P-type semiconductor layer on the substrate in a first direction, wherein the first direction is vertical to the substrate and points to the N-type semiconductor layer from the substrate.
CN202010961660.1A 2020-09-14 2020-09-14 LED chip with epitaxial insertion layer and manufacturing method thereof Pending CN111916540A (en)

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