CN111916445A - Integrated circuit layout structure capable of shielding noise - Google Patents
Integrated circuit layout structure capable of shielding noise Download PDFInfo
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- CN111916445A CN111916445A CN202010845544.3A CN202010845544A CN111916445A CN 111916445 A CN111916445 A CN 111916445A CN 202010845544 A CN202010845544 A CN 202010845544A CN 111916445 A CN111916445 A CN 111916445A
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- 238000005859 coupling reaction Methods 0.000 abstract description 19
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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Abstract
The invention discloses an integrated circuit layout structure capable of shielding noise, which comprises a core layout, a first noise prevention net and a second noise prevention net, wherein the first noise prevention net is laid on a first surface of the core layout; the second noise-proof net is laid on the second surface of the core layout; the first noise-proof net and the second noise-proof net form a shielding cover used for shielding the core layout positioned in the middle from noise. According to the invention, the first anti-noise net and the second anti-noise net are respectively arranged on the upper surface and the lower surface of the core layout, so that the whole core layout is arranged in the shielding cover formed by the first anti-noise net and the second anti-noise net, the decoupling capacitance of the whole layout is increased, the decoupling noise is reduced, and the beneficial effect that the influence of external coupling noise on the layout is greatly reduced is realized.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to an integrated circuit layout structure capable of shielding noise.
Background
An integrated circuit is a miniature electronic device or component, and the components and wiring of transistor, diode, resistor, capacitor and inductor required in a circuit are interconnected together by a certain process, and then are made into a small piece or several small pieces of semiconductor wafers or medium substrates, and then are packaged in a package, so that the miniature structure with the required circuit function is formed. The various terminals of the integrated circuit are the input, output, power and ground of the circuit.
The layout is a set of geometric figures (usually rectangles or polygons) located on different layers, and the layout design refers to a process of laying out and routing a gate-level netlist generated by a front-end design through an EDA (Electronic design automation) design tool, performing physical verification, and finally generating GDSII (geographic Data Standard II) Data for manufacturing.
Noise refers to the fact that charge carriers thermally excited in a conductor constitute a randomly varying current, causing a random voltage, and any signal in the circuit other than the target signal, regardless of whether it affects the circuit, may be referred to as noise. The noise limits the minimum level signal which can be correctly processed by the circuit, and the noise is mutually restricted with power consumption, speed and linearity, so that the performance of the layout is greatly influenced. In the existing layout design, noise is usually isolated by adding a guard ring, i.e. adding a power ring and a ground ring.
In the process of implementing the technical scheme of the invention in the embodiment of the present application, the inventor of the present application finds that the above-mentioned technology has at least the following technical problems:
in the prior art, because the integrated circuit layout design isolates noise by adding the guard ring, only the noise around the circuit can be isolated, and the isolation effect on other coupling noise outside is not great.
Disclosure of Invention
The embodiment of the application provides a but integrated circuit layout structure of shielding noise, has solved among the prior art because integrated circuit layout design comes the isolated noise through increasing the protection ring, can only the noise around the isolated circuit for the little technical problem of the isolation of other coupling noises outside, through the upper and lower two sides of core layout set up respectively first noise control net with second noise control net, make whole core layout arranged in by first noise control net with the shield cover that second noise control net formed in, make the decoupling capacitance of whole layout strengthen, thereby reduced the decoupling noise, realized the beneficial effect that can greatly reduce the influence of external coupling noise to layout itself.
In order to solve the above problem, an embodiment of the present application provides an integrated circuit layout structure capable of shielding noise, where the layout includes:
a core layout;
the first noise-proof net is laid on the first surface of the core layout;
the second noise-proof net is laid on the second surface of the core layout;
the first noise-proof net and the second noise-proof net form a shielding cover used for shielding the core layout positioned in the middle from noise.
Further, the first noise-proof net completely covers the core layout.
Furthermore, the second noise-proof net completely covers the core layout.
Furthermore, the first noise-proof net is formed by the power line of the layout in a zigzag mode.
Furthermore, the second noise-proof net is formed by the ground wire of the layout in a zigzag mode.
Furthermore, the first noise-proof net comprises a plurality of first horizontal sections arranged at horizontal intervals and a plurality of first vertical sections arranged at vertical intervals, the first horizontal sections are perpendicular to the first vertical sections, and the first noise-proof net is a net grid formed by interweaving the first horizontal sections and the first vertical sections.
Furthermore, the second noise-proof net comprises a plurality of second horizontal sections arranged at horizontal intervals and a plurality of second vertical sections arranged at vertical intervals, the second horizontal sections are perpendicular to the second vertical sections, and the second noise-proof net is a net grid formed by interweaving the second horizontal sections and the second vertical sections.
Further, the first surface is a surface of the layout, and the second surface is a bottom surface of the layout.
Furthermore, the first anti-noise net is made of the same material as the metal material on the top layer of the layout.
Furthermore, the second anti-noise net is made of the same metal material as the second-level layer of the layout.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
(1) this application embodiment through the two sides of core territory set up respectively first noise control net with second noise control net for whole core territory is arranged in by first noise control net with the shield cover that second noise control net formed in, make the decoupling capacitance of whole territory strengthen, thereby reduced the noise of decoupling, effectively solved among the prior art because integrated circuit domain design comes the noise isolation through increasing the protection ring, consequently can only the noise around the isolation circuit, thereby make the little technical problem of other coupling noise isolation effect outside, realized can greatly reduce the beneficial effect of the influence of external coupling noise to the territory itself.
(2) The embodiment of the application first noise control net cover completely the core territory, second noise control net cover completely the core territory, make the core territory be located completely by first noise control net with the second noise control net form among the shield cover to better isolated noise of decoupling, effectively solved among the prior art because integrated circuit territory design comes isolation noise through increasing the protection ring, consequently can only keep apart the noise around the circuit, thereby make the little technical problem of coupling noise isolation effect to other outside, realized can greatly reduce the beneficial effect of external coupling noise to the influence of territory itself.
(3) The first anti-noise net is directly formed by the power line of the layout in a zigzag mode, and the second anti-noise net is directly formed by the ground wire of the layout in a zigzag mode, so that the layout structure is more compact. The whole layout is arranged in a shielding cover formed by a power line and a ground line, so that the decoupling capacitance of the whole layout is increased, the decoupling noise is reduced, and meanwhile, the influence of other modules on the core layout is small due to the fact that the whole layout is fully distributed with a grid-shaped ground.
(4) The first anti-noise net is the horizontal and vertical grid formed by the power line in a zigzag mode, and the second anti-noise net is the horizontal and vertical grid formed by the ground line in a zigzag mode, so that the whole layout is horizontal and vertical, clear in arrangement and more attractive.
Drawings
Fig. 1 is a first schematic diagram of a layout structure (not shown) of an integrated circuit capable of shielding noise according to this embodiment;
fig. 2 is a second schematic diagram of the layout structure of the integrated circuit capable of shielding noise according to the present embodiment;
fig. 3 is a schematic structural diagram of a first noise-prevention net of an integrated circuit layout structure capable of shielding noise according to this embodiment;
fig. 4 is a schematic structural diagram of a second noise-prevention net of the integrated circuit layout structure capable of shielding noise according to this embodiment;
fig. 5 is an equivalent circuit diagram of an integrated circuit layout structure capable of shielding noise according to this embodiment.
Description of reference numerals: the core layout 100, the shielding case 200, the first noise-proof net 210, the second noise-proof net 220, the VDD power supply terminal, and the VSS ground terminal.
Detailed Description
The embodiment of the application provides an integrated circuit layout structure capable of shielding noise, and solves the technical problem that in the prior art, because the integrated circuit layout design isolates the noise by adding a protection ring, the noise around a circuit can only be isolated, and the isolation effect on other coupling noises outside is not high.
In order to solve the technical problem of the crosstalk, the technical scheme in the embodiment of the present application has the following general idea: through the upper and lower two sides of core territory set up respectively first noise control net with second noise control net for whole core territory is arranged in by first noise control net with the shield cover that second noise control net formed in, make the decoupling capacitance of whole territory strengthen, thereby reduced the noise of decoupling, effectively solved among the prior art because integrated circuit territory design comes the isolated noise through increasing the protection ring, consequently only can the noise around the isolated circuit, thereby make little technical problem of other coupling noise isolation effects outside, realized can greatly reduce the beneficial effect of the influence of external coupling noise to the territory itself.
In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.
Fig. 2 is a first schematic diagram of an integrated circuit layout structure (a shielding case is not shown) capable of shielding noise provided in this embodiment, and fig. 2 is a second schematic diagram of an integrated circuit layout structure capable of shielding noise provided in this embodiment, as shown in fig. 1 and 2, where the layout includes a core layout 100, a first noise-prevention net 210, and a second noise-prevention net 220.
The core layout 100 refers to a corresponding structure of each element and wiring of the integrated circuit in the layout. The first noise-proof net 210 is laid on a first surface of the core layout 100; the second noise-proof net 220 is laid on the second surface of the core layout 100; the first noise-proof net 210 and the second noise-proof net 220 form a shielding cover 200 for shielding the core layout 100 from noise, and both the first noise-proof net 210 and the second noise-proof net 220 are metal nets.
Fig. 5 is an equivalent circuit diagram of an integrated circuit layout structure capable of shielding noise according to this embodiment, as shown in fig. 5, in this embodiment, the first noise-prevention net 210 and the second noise-prevention net 220 are respectively located on the upper and lower surfaces of the core layout 100, and the entire core layout 100 is placed in the shielding enclosure 200 formed by the first noise-prevention net 210 and the second noise-prevention net 220, so that the decoupling capacitor 300 of the entire layout is increased, thereby reducing the decoupling noise, and effectively solving the technical problem that in the prior art, since the integrated circuit layout design isolates the noise by adding the protection ring, the noise around the circuit can only be isolated, so that the isolation effect of the external coupling noise on other coupling noise is not great, and achieving the beneficial effect of greatly reducing the influence of the external coupling noise on the layout itself.
Further, the first noise-proof net 210 completely covers the core layout 100, and the second noise-proof net 220 completely covers the core layout 100.
Specifically, the first noise-prevention net 210 completely covers the core layout 100, and the second noise-prevention net 220 completely covers the core layout 100, so that the core layout 100 is completely located in the shielding case 200 formed by the first noise-prevention net 210 and the second noise-prevention net 220, thereby better isolating decoupling noise and achieving the beneficial effect of greatly reducing the influence of external coupling noise on the layout itself.
Further, fig. 3 is a schematic structural diagram of a first noise-prevention net of the integrated circuit layout structure capable of shielding noise provided in this embodiment, and fig. 4 is a schematic structural diagram of a second noise-prevention net of the integrated circuit layout structure capable of shielding noise provided in this embodiment, as shown in fig. 3 and 4, the first noise-prevention net 210 is formed by a power line of the layout being meandered, and the second noise-prevention net 220 is formed by a ground line of the layout being meandered.
Specifically, in this embodiment, as shown in fig. 5, the first noise-prevention mesh 210 is directly formed by the power line meander of the layout, and the second noise-prevention mesh 220 is directly formed by the ground line meander of the layout, so that the layout structure is more compact; meanwhile, the whole layout is placed in the shielding case 200 formed by the power line and the ground line, so that the decoupling capacitance of the whole layout is increased, and the decoupling noise is reduced; and the core layout 100 is also slightly affected by other modules due to the fact that the grid-shaped ground is fully distributed.
Further, as shown in fig. 3, the first noise-proof net 210 includes a plurality of first horizontal segments arranged at horizontal intervals and a plurality of first vertical segments arranged at vertical intervals, the first horizontal segments are perpendicular to the first vertical segments, and the first noise-proof net is a net grid formed by interweaving the first horizontal segments and the first vertical segments.
Further, as shown in fig. 4, the second noise-proof net 220 includes a plurality of second horizontal segments arranged at horizontal intervals, and also includes a plurality of second vertical segments arranged at vertical intervals, the second horizontal segments are perpendicular to the second vertical segments, and the second noise-proof net is a net grid formed by interweaving the second horizontal segments and the second vertical segments.
Specifically, the first noise-proof net 210 is a horizontal, flat and vertical grid formed by the zigzag of the power line, and the second noise-proof net 220 is a horizontal, flat and vertical grid formed by the zigzag of the ground line, so that the whole layout is horizontal, flat and vertical, clear in arrangement and more attractive.
Further, the first surface is a surface of the layout, and the second surface is a bottom surface of the layout.
Further, the first anti-noise net 210 is made of the same metal material as the top layer of the layout, and the second anti-noise net 220 is made of the same metal material as the second top layer of the layout.
Specifically, since the bottom metal is fully used, in the embodiment of the present application, the power line and the ground line are respectively routed on the surface of the core layout 100 by using the metal on the top layer and the metal on the second layer of the layout, so as to form the shielding case 200.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
(1) this application embodiment through the two sides of core territory 100 set up respectively first noise control net 210 with second noise control net 220 for whole core territory 100 is arranged in by first noise control net 210 with second noise control net 220 in the shield cover 200 that forms, make the decoupling capacitance 300 of whole territory strengthen, thereby reduced the noise of decoupling, effectively solved among the prior art because integrated circuit layout design comes the noise isolation through increasing the protection ring, consequently can only the noise around the buffer circuit, thereby make the little technical problem of other coupling noise isolation effect outside, realized can greatly reducing the beneficial effect of the influence of external coupling noise to the territory itself.
(2) First noise control net 210 cover completely core layout 100, second noise control net 220 cover completely core layout 100, make core layout 100 be located completely by first noise control net 210 with second noise control net 220 among the shield 200 that forms to better isolated noise of decoupling, effectively solved among the prior art because integrated circuit layout design is through increasing the protection ring isolation noise, consequently can only the noise around the isolation circuit, thereby make the little technical problem of other coupling noise isolation effect outside, realized can greatly reduce the beneficial effect of the influence of external coupling noise to layout itself.
(3) The first noise-proof net 210 is directly formed by the power line of the layout in a zigzag manner, and the second noise-proof net 220 is directly formed by the ground line of the layout in a zigzag manner, so that the layout structure is more compact. The whole layout is placed in a shielding case 200 formed by a power line and a ground line, so that the decoupling capacitance of the whole layout is increased, the decoupling noise is reduced, and meanwhile, the influence of other modules on the core layout 100 is small due to the fact that the whole layout is fully distributed with a grid-shaped ground.
(4) The first noise-proof net 210 is a horizontal and vertical grid formed by the power line in a zigzag manner, and the second noise-proof net 220 is a horizontal and vertical grid formed by the ground line in a zigzag manner, so that the whole layout is horizontal and vertical, clear in arrangement and more attractive.
It should be understood that terms of orientation such as outer, middle, inner, etc., referred to or as may be referred to in this specification are defined relative to the configuration shown in the drawings and are relative terms, such that the terms may be changed correspondingly according to the position and the use state of the terms. Therefore, these and other directional terms should not be construed as limiting terms.
While the foregoing is directed to the preferred embodiment of the present application, and not to the limiting thereof in any way and any way, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims. Those skilled in the art can make various changes, modifications and equivalent arrangements to those skilled in the art without departing from the spirit and scope of the present application; moreover, any equivalent alterations, modifications and variations of the above-described embodiments according to the spirit and techniques of this application are intended to be within the scope of the claims of this application.
Claims (10)
1. An integrated circuit layout structure capable of shielding noise, the layout structure comprising:
a core layout;
the first noise-proof net is laid on the first surface of the core layout;
the second noise-proof net is laid on the second surface of the core layout;
the first noise-proof net and the second noise-proof net form a shielding cover used for shielding the core layout positioned in the middle from noise.
2. The integrated circuit layout structure capable of shielding noise according to claim 1, wherein said first noise net completely covers said core layout.
3. The integrated circuit layout structure capable of shielding noise according to claim 1, wherein said second noise net completely covers said core layout.
4. The layout structure of an integrated circuit capable of shielding noise according to claim 1, wherein said first noise-preventing net is formed by meandering of a power supply line of said layout.
5. The layout structure of an integrated circuit capable of shielding noise according to claim 1, wherein said second noise net is formed by a ground meander of said layout.
6. The integrated circuit layout structure capable of shielding noise according to claim 1, wherein the first noise-proof mesh comprises a plurality of first horizontal segments arranged at horizontal intervals and a plurality of first vertical segments arranged at vertical intervals, the first horizontal segments are perpendicular to the first vertical segments, and the first noise-proof mesh is a mesh grid formed by interweaving the first horizontal segments and the first vertical segments.
7. The integrated circuit layout structure capable of shielding noise according to claim 1, wherein the second noise-proof net comprises a plurality of second horizontal segments arranged at horizontal intervals and a plurality of second vertical segments arranged at vertical intervals, the second horizontal segments are perpendicular to the second vertical segments, and the second noise-proof net is a net grid formed by interweaving the second horizontal segments and the second vertical segments.
8. The integrated circuit layout structure capable of shielding noise according to claim 1, wherein said first surface is a surface of said layout, and said second surface is a bottom surface of said layout.
9. The layout structure of an integrated circuit capable of shielding noise according to claim 1, wherein the first noise-proof net is made of the same material as the metal material of the top layer of the layout.
10. The layout structure of an integrated circuit capable of shielding noise according to claim 1, wherein the second noise-proof net is made of the same material as the metal material of the second top layer of the layout.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010845544.3A CN111916445A (en) | 2020-08-20 | 2020-08-20 | Integrated circuit layout structure capable of shielding noise |
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| CN202010845544.3A CN111916445A (en) | 2020-08-20 | 2020-08-20 | Integrated circuit layout structure capable of shielding noise |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115983196A (en) * | 2023-03-17 | 2023-04-18 | 卓捷创芯科技（深圳）有限公司 | Method for analyzing chip physical layout noise coupling and shielding through LVS (Low Voltage differential Signal) inspection |
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2020
- 2020-08-20 CN CN202010845544.3A patent/CN111916445A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115983196A (en) * | 2023-03-17 | 2023-04-18 | 卓捷创芯科技（深圳）有限公司 | Method for analyzing chip physical layout noise coupling and shielding through LVS (Low Voltage differential Signal) inspection |
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