CN111916392A - 半导体装置的制备方法 - Google Patents

半导体装置的制备方法 Download PDF

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Publication number
CN111916392A
CN111916392A CN201911016679.2A CN201911016679A CN111916392A CN 111916392 A CN111916392 A CN 111916392A CN 201911016679 A CN201911016679 A CN 201911016679A CN 111916392 A CN111916392 A CN 111916392A
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China
Prior art keywords
wafer
substrate
layer
conductors
opening
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CN201911016679.2A
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English (en)
Inventor
吴珮甄
丘世仰
施江林
张庆弘
罗翊仁
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Nanya Technology Corp
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Nanya Technology Corp
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Publication of CN111916392A publication Critical patent/CN111916392A/zh
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Abstract

本公开提供一种半导体装置的制备方法。该制备方法包括提供一第一晶圆，该第一晶圆具有一第一基底以及多个第一导体，所述多个导体配置在该第一基底上方；形成一第一互连结构，以穿经该第一基底并接触所述多个导体其中之一；在该第一基底与该第一互连结构上形成一接合介电质；将一第二晶圆接合在该第一晶圆上，其中该第二晶圆具有一第二基底、一第二层间介电层以及多个第二导体，该第二层间介电层配置在该第二基底的一第二前表面上，所述多个第二导体配置在该第二层间介电层内，其中该第二层间介电层接触该接合介电质；以及形成一第二互连结构，以穿经该第二基底，并穿入该第二层间介电层，且接触该第二导体与该第一互连结构。

Description

半导体装置的制备方法
技术领域
本公开主张2019/05/07申请的美国正式申请案第16/404,830号的优先权及益处，该美国正式申请案的内容以全文引用的方式并入本文中。
背景技术
当集成电路技术持续进步，不间断的努力寻找提升效能与密度、改善形状因数(form factor)，并降低成本。由许多设计者所探索出来的实现如此优势的一方法是由层叠式三维(3D)集成电路所实现。三维集成电路的一些区域为一适合考虑的事，其是具有二或多个芯片的叠置，所述的叠置是使用不同制造流程(fabrication process)所制造，或者是经电的叠置是使用相同的制造流程所制造，以减少集成电路设备的占用面积(footprint)。
上文的“现有技术”说明仅是提供背景技术，并未承认上文的“现有技术”说明公开本公开的标的，不构成本公开的现有技术，且上文的“现有技术”的任何说明均不应作为本公开的任一部分。
发明内容
本公开的一实施例提供一种半导体装置的制备方法。该制备方法包括提供一第一晶圆，该晶圆包括一第一基底、一第一层间介电层(first inter-layer dielectric(ILD)layer)以及多个第一导体，该第一层间介电层配置在该第一基底的一第一前表面，所述多个第一导体配置在该第一层间介电层内；形成一第一互连结构，该互连结构穿经该第一基底并穿入该第一层间介电层，且接触所述多个第一导体的其中之一；在相对该第一前表面设置的一第一后表面上以及在该第一互连结构上形成一接合介电质；在该第一晶圆上接合一第二晶圆，其中该第二晶圆包括一第二基底、一第二层间介电层以及多个第二导体，该第二层间介电层配置在该第二基底的一第二前表面上，所述多个第二导体配置在该第二层间介电层内，其中该第二层间介电层接触该接合介电质；以及形成一第二互连结构，该第二互连结构穿经该第二基底并穿入该第二层间介电层，且接触所述多个第二导体其中之一以及该第一互连结构。
依据本公开的一些实施例，该第一互连结构的形成步骤包括：形成一第一开口，该第一开口穿经该第一基底并穿入该第一层间介电层，以暴露所述多个第一导体其中之一；以及在该第一开口内沉积一第一金属材料。
依据本公开的一些实施例，该第二互连结构的形成步骤还包括：形成一第一切槽，该第一切槽穿经该第二基底、该第二层间介电层以及该接合介电质，以暴露该第一金属材料；形成一第二切槽，该第二切槽穿经该第二基底并穿入该第二层间介电层，以暴露所述多个第二导体其中之一；形成一凹口，该凹口连通该第一切槽与该第二切槽；以及在该第一切槽、该第二切槽以及该凹口内沉积一第二金属材料。
依据本公开的一些实施例，该制备方法还包括：在沉积该第一金属材料之前，沿着该第一后表面与该第一开口沉积一第一隔离层；移除该第一隔离层的一部分，以暴露所述多个第一导体其中之一；在该第二金属材料沉积之前，沿着该第二基底的一第二后表面、该凹口、该第一切槽以及该第二切槽沉积一第二隔离层；以及移除该第二隔离层的多个部分，以暴露所述多个第二导体其中之一以及该第一金属材料。
依据本公开的一些实施例，该制备方法还包括：在该第一金属材料沉积之前，在该第一隔离层上与所述多个第一导体其中之一上沉积一第一阻障层(first barrierlayer)；以及在该第二金属材料沉积之前，在该第二金属材料上与所述多个第二金属接触点其中之一上沉积一第二阻障层(second barrier layer)。
依据本公开的一些实施例，该制备方法还包括：执行一第一平坦化工艺，以移除位在该第一隔离层上的该第一金属材料与该第一阻障层的所述多个部分；以及执行一第二平坦化工艺，以移除位在该第二隔离层上的该第二金属材料与该第二阻障层的所述多个部分。
依据本公开的一些实施例，该第一互连结构的形成步骤还包括：在该第一金属材料沉积之前，形成一第二开口，该第二开口连通在该第一基底内的该第一开口；以及在该第二开口内沉积该第一金属材料。
依据本公开的一些实施例，该第二开口具有一大致前后一致的直径，且该第一开口具有一直径，其是朝向远离该第一后表面的方向递减，其中该第一开口的该直径小于该第二开口的该直径。
依据本公开的一些实施例，该第一开口具有一中线，其是偏离该第二开口的一中线。
依据本公开的一些实施例，该制备方法还包括：在该第二后表面上沉积一钝化层(passivation layer)；以及形成一外部接触点(external contact)，该外部接触点接触该第二互连结构。
依据本公开的一些实施例，该制备方法还包括：在提供该第一晶圆之前，提供一载体晶圆(carrier wafer)；在该载体晶圆上形成一接合层(bonding layer)；以及在该载体晶圆上接合该第一晶圆，其中该第一层间介电层接触该接合层。
依据本公开的一些实施例，该制备方法还包括在将该第一晶圆接合到该载体晶圆之后，使该第一基底变薄。
依据本公开的一些实施例，该制备方法还包括在该第二金属材料形成之后，研磨该载体晶圆。
依据本公开的一些实施例，该第一互连结构(first interconnect structure)包括：一平台(mesa)；以及一突出物(protrusion)，从该平台延伸并接触该第一导体。
依据本公开的一些实施例，该第二互连结构(second interconnect structure)包括：一基座(base)；一第一支脚(first leg)，从该基座延伸并接触所述多个第二导体其中之一；以及一第二支脚(second leg)，从该基座延伸并接触该第一互连结构。
上文已相当广泛地概述本公开的技术特征及优点，从而使下文的本公开详细描述得以获得优选了解。构成本公开的权利要求标的的其它技术特征及优点将描述于下文。本公开所属技术领域中技术人员应了解，可相当容易地利用下文公开的概念与特定实施例可作为修改或设计其它结构或工艺而实现与本公开相同的目的。本公开所属技术领域中技术人员亦应了解，这类等效建构无法脱离权利要求所界定的本公开的构思和范围。
附图说明
参阅实施方式与权利要求合并考量附图时，可得以更全面了解本申请的公开内容，附图中相同的元件符号是指相同的元件。
图1为依据本公开一些实施例的一种半导体装置的剖视示意图。
图2为依据本公开一些实施例的一种半导体装置的制备方法的流程示意图。
图3至图28为依据本公开一些实施例一半导体装置于制备的各中间阶段的剖视示意图。
附图标记说明：
10 半导体装置
20 第一晶圆
30 第二晶圆
40 接合层
42 载体晶圆
44 接合介电质
46 钝化层
48 外部接触点
50 制备方法
62 第一光刻胶图案
64 第二光刻胶图案
66 光刻胶材料
68 光刻胶材料
210 第一基底
212 前表面
214 后表面
214' 后表面
220 第一层间介电层
230 第一导体
240 第一开口
242 中线
250 第二开口
252 中线
260 阶层孔
270 第一隔离层
280 第一阻障层
292 第一互连结构
310 第二基底
312 前表面
314 后表面
320 第二层间介电层
330 第二导体
340 第一切槽
342 第二切槽
350 凹口
370 第二隔离层
380 第二阻障层
392 第二互连结构
422 第一表面
424 第二表面
502 步骤
504 步骤
506 步骤
508 步骤
510 步骤
512 步骤
514 步骤
516 步骤
518 步骤
520 步骤
522 步骤
524 步骤
526 步骤
528 步骤
530 步骤
532 步骤
534 步骤
536 步骤
538 步骤
540 步骤
2920 平台
2921 侧壁
2922 突出物
2923 侧壁
3920 基座
3921 侧壁
3922 第一支脚
3923 侧壁
3924 第二支脚
3925 侧壁
D1 直径
D2 直径
T1 厚度
T2 厚度
具体实施方式
本公开的以下说明伴随并入且组成说明书的一部分的附图，说明本公开的实施例，然而本公开并不受限于该实施例。此外，以下的实施例可适当整合以下实施例以完成另一实施例。
“一实施例”、“实施例”、“例示实施例”、“其他实施例”、“另一实施例”等是指本公开所描述的实施例可包含特定特征、结构或是特性，然而并非每一实施例必须包含该特定特征、结构或是特性。再者，重复使用“在实施例中”一语并非必须指相同实施例，然而可为相同实施例。
为了使得本公开可被完全理解，以下说明提供详细的步骤与结构。显然，本公开的实施不会限制该技艺中的技术人士已知的特定细节。此外，已知的结构与步骤不再详述，以免不必要地限制本公开。本公开的优选实施例详述如下。然而，除了详细说明之外，本公开亦可广泛实施于其他实施例中。本公开的范围不限于详细说明的内容，而是由权利要求定义。
本文中使用的术语仅是为了实现描述特定实施例的目的，而非意欲限制本发明。如本文中所使用，单数形式“一(a)”、“一(an)”，及“该(the)”意欲亦包括多个形式，除非上下文中另作明确指示。将进一步理解，当术语“包括(comprises)”及/或“包括(comprising)”用于本说明书中时，所述多个术语规定所陈述的特征、整数、步骤、操作、元件，及/或组件的存在，但不排除存在或增添一或更多个其他特征、整数、步骤、操作、元件、组件，及/或上述各者的群。
图1为依据本公开一些实施例的一种半导体装置10的剖视示意图。请参考图1，半导体装置10包括一第一晶圆(first wafer)20以及一第二晶圆(second wafer)30，第二晶圆30叠置(stacked)并接合(bonded)在第一晶圆20的一顶部(top)。在一些实施例中，第一晶圆20与第二晶圆30是可使用相同的制造流程(fabrication process)进行制造。举例来说，第一晶圆20与第二晶圆30可形成一存储器堆叠(memory stack)。在一些实施例中，第一晶圆20与第二晶圆30可使用不同制造流程进行制造。举例来说，第一晶圆20与第二晶圆30其中之一可为一存储器堆叠，第一晶圆20与第二晶圆30其中的另一个是可为一处理器(processor)、一影像感测器(image sensor)或是一应用专用集成电路(application-specific integrated circuit，ASIC)装置。
第一晶圆20与第二晶圆30是可使用介电质与介电质接合(dielectric-to-dielectric bonding)工艺进行接合。举例来说，第二晶圆30以一氧化物与氧化物接合(oxide-to-oxide bonding)工艺接合在第一晶圆20上。在一些实施例中，第一晶圆20的一后表面(back surface)214可涂布一或多个接合介电质(bonding dielectrics)44，所述接合介电质44包含氧化物，以提供一高品质接合界面(high-quality bonding interface)。在一些实施例中，第一晶圆20是可以一介电质与介电质接合工艺叠置且接合在一载体晶圆42上，其中一接合层40可夹置在第一晶圆20与载体晶圆40之间，以提供一高品质接合界面。
在一些实施例中，第一晶圆20具有一第一基底210、一第一层间介电层(firstinter-layer dielectric(ILD)layer)220以及多个第一导体230，基底210具有相对后表面214设置的一前表面212，第一层间介电层220配置在前表面212上，多个导体230配置在第一层间介电层220内。在一些实施例中，第一基底210可还包括多个不同层，其并未分开描绘，而是组合在一起，以形成不同微电子元件(microelectronic elements)，微电子元件可包括晶体管(transistors)、电阻器(resistors)、二极管(diodes)、电容器(capacitors)、电感器(inductors)、熔丝(fuses)，或其他适合元件，或是其组合。所述多个不同层可包括高介电常数(high-k)的介电层(dielectric layers)、栅极层(gate layers)、接口层(interfacial layers)、扩散/阻障层(diffusion/barrier layers)、介电层(dielectriclayers)、导电层(conductive layers)、其他适合层，或是其组合。第一基底210的多个不同层亦可包括不同掺杂区(doped regions)、隔离特征(isolation features)、其他特征，或是其组合。再者，如此的微电子元件可互相互连(interconnect)，以形成第一基底210的一部分，例如一逻辑装置(logicdevice)、一存储器装置(memory device)、一射频(radiofrequency)装置、一输入/输出(input/output)装置、一系统整合芯片(system-on-chip)装置、其他适合形态的装置，或是其组合。在一些实施例中，第一层间介电层220覆盖所述微电子元件、所述掺杂区以及所述格离特征。
第一晶圆20还包括至少一第一互连结构292，穿经第一基底210并穿入第一层间介电层220，且接触所述多个第一导体230其中之一。在一些实施例中，第一互连结构292具有一平台2920以及一突出物2922，突出物2922从平台2920延伸并接触所述多个第一导体230其中之一。在一些实施例中，第一互连结构292包含金属，例如铜(copper)或铝(aluminum)。
在一些实施例中，第一晶圆20还包括一第一隔离层(first insulating layer)270，沿着第一后表面214延伸，并贴合到平台2920的侧壁2921、2923以及突出物2922。形成第一隔离层270以避免扩散尖峰(diffusion spikes)，而所述的扩散尖峰造成穿过第一基底210与第一互连结构292的短路(shorts)。
在一些实施例中，第一晶圆20可还包括一第一阻障层(first barrier layer)280，夹置在第一互连结构292与第一隔离层270之间，以及夹置在第一互连结构292与第一导体230之间。在一些实施例中，第一阻障层280的作用如一胶粘层(glue layer)。在一些实施例中，耐火金属(refractory metals)、耐火金属氮化物(refractory metal nitrides)、耐火金属氮化硅(refractory metal silicon nitrides)，以及其组合，是典型地使用于第一阻障层280。在一些实施例中，第一阻障层280可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)、氮化硅钛(titanium silicon nitride，TiSiN)、氮化硅钽(tantalum siliconnitride，TaSiN)，或其类似物。
第二晶圆30具有一第二基底310、一第二层间介电层320以及多个第二导体330，第二层间介电层320配置在第二基底310的一前表面312上，所述多个第二导体330配置在第二层间介电层320内。在一些实施例中，第二基底310可还包括多个不同层，其并未分开描绘，而是组合在一起，以形成如上所述的不同微电子元件、掺杂区、隔离特征。在一些实施例中，第二层间介电层320覆盖所述微电子元件、所述掺杂区以及所述格离特征。
第二晶圆30还包括至少一第二互连结构392，是连接所述多个第一导体230其中之一，以提供一外部电性连接(external electrical connection)，且所述至少一第二互连结构392亦连接所述多个第二导体330其中之一，以提供一内部连接(internalconnection)。在一些实施例中，第二互连结构392具有一基座3920、一第一支脚3922以及一第二支脚3924，第一支脚3922从基座3920延伸并接触第二导体330，第二支脚3824从基座3920延伸并接触第一互连结构292。在一些实施例中，基座3920、第一支脚3922以及第二支脚3924为一体成形(integrated)，且由包含如铜或铝的金属的材料所形成。
第二晶圆30还包括一第二隔离层370，第二隔离层370配置在第二基底310的前表面312上，第二隔离层370亦配置在基座3920的侧壁3921上、配置在第一支脚3922的侧壁3923上以及配置在第二支脚3924的侧壁3925上。形成第二隔离层370以避免扩散尖峰，而所述的扩散尖峰造成穿过第二基底310与第二互连结构392的短路(shorts)。
第二晶圆30可还包括一第二阻障层380，配置在第二互连结构392与第二隔离层370之间以及配置在第二互连结构392与第二导体330之间。
在一些实施例中，半导体装置10还包括一钝化层46以及至少一外部接触点48，钝化层46配置在第二隔离层370上，所述至少一外部接触点48是配置在第二互连结构392上。钝化层36使用来保护第二晶圆30避免受到环境影响。
图2为依据本公开一些实施例的一种半导体装置10的制备方法50的流程示意图。图3至图28为依据本公开一些实施例一半导体装置10于所述制备方法50的各中间阶段的剖视示意图。接下来的讨论中，在图3至图28中的各制备阶段是参考图2中的流程步骤进行讨论。
请参考图3，依据图2中一步骤502，提供一载体晶圆42。在一些实施例中，载体晶圆42可为一赤裸硅晶圆(bare silicon wafer)，没有任何电路配置在其上。在一些实施例中，载体晶圆42具有一第一表面422以及一第二表面424，第二表面424与第一表面422相对设置。在一些实施例中，载体晶圆42具有一厚度T1，举例来说，厚度T1可大于750μm，例如775μm。
接下来，依据图2中一步骤504，在第一表面422上形成一接合层40。在一些实施例中，接合层40包含氧化物，例如氧化硅。在一些实施例中，接合层40是可由一热氧化工艺(thermal oxidation process)或是一化学气相沉积(chemical vapor deposition，CVD)工艺所形成。
请参考图4及图5，依据图2中一步骤506，提供接合在在体晶圆42上的一第一晶圆20。在一些实施例中，第一晶圆20是以介电质与介电质接合(dielectric-to-dielectricbonding)工艺接合在载体晶圆42上，例如一氧化物融熔接合(oxide fusion bonding)工艺。在一些实施例中，第一晶圆20具有一第一基底210、一第一层间介电层220以及多个第一导体230，第一层间介电层220配置在第一基底210的一第一前表面212上，所述多个第一导体230配置在第一层间介电层220内。在第一晶圆20与载体晶圆42接合后，第一晶圆20叠置在载体晶圆42上，且第一层间介电层220接触接合层40。举例来说，第一基底210可包含掺杂或未掺杂块状硅(doped or undoped bulk silicon)，或是一半导体上绝缘体(semiconductor-on-insulator，SOI)基底的一主动层(active layer)。在一些实施例中，第一基底210可还包括多个不同层，其并未分开描绘，而是组合在一起，以形成如上所述的不同微电子元件、掺杂区、隔离特征。在一些实施例中，第一层间介电层220覆盖所述微电子元件、所述掺杂区以及所述格离特征。
请参考图6，依据图2中一步骤508，可执行一薄化工艺(thinningprocess)，以使第一晶圆20变薄。据此，暴露一第一后表面214'。在一些实施例中，在相对前表面212设置的一初始后表面214(如图4及图5所示)上执行所述薄化工艺，以使第一基底210变薄。在图6中，虚线表示第一基底210的一原始厚度(original thickness)。所述薄化工艺是可使用适合的技术实现，例如一磨制工艺(grinding process)、一研磨工艺(polishing process)及/或一化学蚀刻工艺(chemical etching process)。
请参考图7及图8，依据图2中一步骤510，在一些实施例中，形成一第一开口(firstopening)240，以暴露所述多个第一导体230其中之一。在一些实施例中，通过在第一后表面214'上涂布一第一光刻胶图案62，并执行一蚀刻工艺以移除第一基底210与第一层间介电层220的一些部分来形成第一开口240。在一些实施例中，第一光刻胶图案62的形成可以在完全覆盖第一后表面214'的一第一光刻胶材料上执行一曝光工艺(exposure process)以及一显影工艺(develop process)所实现。在一些实施例中，通过第一光刻胶图案62暴露第一后表面214'被蚀刻的一部分。在一些实施例中，第一开口240停止在所述多个第一导体230的其中之一。在一些实施例中，第一蚀刻工艺可利用多个蚀刻剂(etchants)来蚀刻第一基底210与第一层间介电层220，其中所述蚀刻剂根据被蚀刻的材料来选择。在一些实施例中，可使用一干蚀刻工艺、一非等向性湿蚀刻工艺(anisotropic wet etching process)或任何其他适合的非等向性蚀刻工艺蚀刻第一基底210与第一层间介电层220。在第一蚀刻工艺之后，举例来说，以一灰化工艺(ashing process)或一湿式剥除工艺(wet stripprocess)移除第一光刻胶图案62，其中所述湿式剥除工艺可在化学上改变第一光刻胶图案62，以使其不再贴合第一基底210。
请参考图9及图10，依据图2中一步骤512，在一些实施例中，形成连通第一开口240的一第二开口250。在一些实施例中，通过在第一后表面214'上涂布一第二光刻胶图案64并执行一第二蚀刻工艺以移除第一基底210的一部分来形成第二开口250。在一些实施例中，通过第二光刻胶图案64暴露第一开口240以及第一后表面214'的一部分。在一些实施例中，第一开口240与第二开口250构成一阶层孔(stepped hole)260。在一些实施例中，第一开口240具有一直径D1，是朝向远离第一后表面214'的方递减。在一些实施例中，第二开口250具有一大致前后一致的直径D2，其大于第一开口240的直径D1。在一些实施例中，第一开口240具有一中线242，且第二开口250具有一中线252，中线252偏离中线242。在第二蚀刻工艺之后，举例来说，是以一灰化工艺(ashing process)或一湿式剥除工艺(wet strip process)移除第二光刻胶图案64。
请参考图11，依据图2中一步骤514，一第一隔离层270沉积在第一后表面214'上，并沉积在阶层孔260内。在此结构中，第一隔离层270是覆盖通过阶层孔260暴露的第一导体230。在一些实施例中，第一隔离层270为一大致保形层(conformal layer)。在一些实施例中，第一隔离层270包含氧化物，例如氧化硅。在一些实施例中，可以一高密度等离子体化学气相沉积工艺(high-density plasma CVD process)形成第一隔离层270。
接下来，如图12所示，移除第一隔离层270的一部分，以暴露第一导体230。在一些实施例中，是通过例如一些蚀刻工艺的一适合的工艺移除第一隔离层270的所述部分。
请参考图13，依据图2中一步骤516，在一些实施例中，一第一阻障层280可选择地沉积在第一隔离层270与第一导体230上。在一些实施例中，第一阻障层280为一大致保形层(conformal layer)。在一些实施例中，第一阻障层280是可为一单层结构，其包含耐火金属、耐火金属氮化物或耐火金属氮化硅。在一些实施例中，第一阻障层280可具有一多层结构，其包含一或多个耐火金属、耐火金属氮化物或耐火金属氮化硅。在一些实施例中，举例来说，可使用一物理气相沉积(physical vapor deposition，PVD)工艺或一原子层沉积(atomic layer deposition)工艺形成第一阻障层280。
请参考图14，依据图2中一步骤518，一第一金属材料290沉积在第一阻障层280上。在一些实施例中，第一金属材料290具有一厚度，其足以填满阶层孔260。在一些实施例中，以一镀覆工艺(plating process)形成第一金属材料290。
请参考图15，依据图2中一步骤520，执行一第一平坦化工艺以暴露第一隔离层270。据此，形成一第一互连结构292。在一些实施例中，平坦化第一金属材料290与第一阻障层280，以暴露第一隔离层270。在一些实施例中，第一平坦化工艺包括一化学机械研磨(chemical mechanical polishing，CMP)工艺。
请参考图16，依据图2中一步骤522，在一些实施例中，一接合介电质(bondingdielectric)44是沉积在第一隔离层270、第一阻障层280与第一互连结构292上。在一些实施例中，接合介电质44包含氧化物，例如氧化硅。在一些实施例中，以类似于使用来形成接合层40的方法形成接合介电质44。
请参考图17，依据图2中一步骤524，提供一第二晶圆30，并使用接合介电质44接合在第一晶圆20上。在一些实施例中，第二晶圆30以介电质与介电质接合工艺接合在第一晶圆20上。在一些实施例中，第二晶圆30包括一第二基底310、一第二层间介电层320以及多个第二导体330，第二层间介电层320配置在第二基底310的一第二前表面312上，所述多个第二导体330配置在第二层间介电层320内。在第二晶圆30接合到第一晶圆20之后，第二晶圆30叠置在第一晶圆20上，且第二层间介电层320接触接合介电质44。
请参考图18及图19，依据图2中一步骤526，在一些实施例中，形成一第一切槽(first trench)340以暴露所述多个第二导体330其中之一，并形成一第二切槽342以暴露第一互连结构292。在一些实施例中，使用光刻技术(photolithography techniques)形成第一切槽340与第二切槽342。详而言之，光刻技术包含在第二后表面314上沉积一光刻胶材料66，其按序地照射(曝光)并显影，以移除光刻胶材料66的一部分。在后续的蚀刻工艺期间，余留的光刻胶材料66保护下层第二基底310。执行例如反应性离子束蚀刻(reactiveion beam etch，RIE)工艺的蚀刻工艺，以移除第二基底310与第二层间介电层320铺设在第二导体330与第一互连结构292其中之一的所述部分。举例来说，之后，以一灰化工艺或一湿式剥除工艺移除余留的光刻胶材料66。
请参考图20及图21，依据图2中一步骤528，在一些实施例中，在第二基底310内形成连通第一切槽340与第二切槽342的一凹口(recess)350。在一些实施例中，举例来说，使用光刻技术形成凹口350，以沉积并图案化在第二后表面314上的一光刻胶材料68，以暴露第二后表面314、第一切槽340以及第二切槽342的所述部分。可使用例如非等向性干蚀刻工艺的一蚀刻工艺，以在第二基底310内产生凹口350。举例来说，之后以一灰化工艺或一湿式剥除工艺移除光刻胶材料68。
请参考图22，依据图2中一步骤530，一大致保形第二隔离层370沉积在第二后表面314上，并沉积在第一切槽340、第二切槽342以及凹口350内。在一些实施例中，以类似于使用来形成第一隔离层270的方法形成第二隔离层370。
请参考图23，以例如一蚀刻工艺的一适合的工艺，移除沉积在第一互连结构292与第二导体330上的第二隔离层370的一些部分。
请参考图24，依据图2中一步骤532，一大致保形的第二阻障层380可选择地沉积在第一互连结构292、第二导体330以及第二隔离层370上。在一些实施例中，使用类似于形成第一阻障层280的方法形成第二阻障层380。
请参考图25，依据图2中一步骤534，一第二金属材料390沉积在第二阻障层380上。在一些实施例中，第二金属材料390具有一厚度，是足以填满第一切槽340、第二切槽342以及凹口350。在一些实施例中，是以使用类似于形成第一金属材料290的方法形成第二金属材料390。
请参考图26，依据图2中一步骤536，在一些实施例中，执行一第二平坦化工艺，以暴露第二隔离层370。据此，形成一第二互连结构392。在一些实施例中，平坦化第二将属材料390与第二阻障层380，以暴露第二隔离层370。
请参考图27，依据图2中一步骤538，一或多个钝化层46形成在第二隔离层270上，且一或多个外部接触点48形成在第二互连结构392上。在一些实施例中，外部接触点48使用来传送第一晶圆20与第二晶圆30的输入/输出、接地，或电源信号。
请参考图28，依据图2中一步骤540，执行一磨覆工艺(grinding process)，以使载体晶圆42变薄。据此，完整地形成半导体装置10。在一些实施例中，薄化载体晶圆42至一厚度T2，例如小于或等于50μm。
本公开的一实施例提供一种半导体装置的制备方法。该制备方法包括提供一第一晶圆，该晶圆包括一第一基底、一第一层间介电层(first inter-layer dielectric(ILD)layer)以及多个第一导体，该第一层间介电层配置在该第一基底的一第一前表面，所述多个第一导体配置在该第一层间介电层内；形成一第一互连结构，该互连结构穿经该第一基底并穿入该第一层间介电层，且接触所述多个第一导体的其中之一；在相对该第一前表面设置的一第一后表面上以及在该第一互连结构上形成一接合介电质；在该第一晶圆上接合一第二晶圆，其中该第二晶圆包括一第二基底、一第二层间介电层以及多个第二导体，该第二层间介电层配置在该第二基底的一第二前表面上，所述多个第二导体配置在该第二层间介电层内，其中该第二层间介电层接触该接合介电质；以及形成一第二互连结构，该第二互连结构穿经该第二基底并穿入该第二层间介电层，且接触所述多个第二导体其中之一以及该第一互连结构。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的构思与范围。例如，可用不同的方法实施上述的许多工艺，并且以其他工艺或其组合替代上述的许多工艺。
再者，本公开的范围并不受限于说明书中所述的工艺、机械、制造、物质组成物、手段、方法与步骤的特定实施例。该技艺的技术人士可自本公开的公开内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质上相同结果的现存或是未来发展的工艺、机械、制造、物质组成物、手段、方法、或步骤。据此，这些工艺、机械、制造、物质组成物、手段、方法、或步骤是包含于本公开的权利要求内。

Claims (15)

1.一种半导体装置的制备方法，包括：
提供一第一晶圆，该晶圆包括一第一基底、一第一层间介电层以及多个第一导体，该第一层间介电层配置在该第一基底的一第一前表面，所述多个第一导体配置在该第一层间介电层内；
形成一第一互连结构，该互连结构穿经该第一基底并穿入该第一层间介电层，且接触所述多个第一导体的其中之一；
在相对该第一前表面设置的一第一后表面上以及在该第一互连结构上形成一接合介电质；
在该第一晶圆上接合一第二晶圆，其中该第二晶圆包括一第二基底、一第二层间介电层以及多个第二导体，该第二层间介电层配置在该第二基底的一第二前表面上，所述多个第二导体配置在该第二层间介电层内，其中该第二层间介电层接触该接合介电质；以及
形成一第二互连结构，该第二互连结构穿经该第二基底并穿入该第二层间介电层，且接触所述多个第二导体其中之一以及该第一互连结构。
2.如权利要求1所述的制备方法，其中该第一互连结构的形成步骤包括：
形成一第一开口，该第一开口穿经该第一基底并穿入该第一层间介电层，以暴露所述多个第一导体其中之一；以及
在该第一开口内沉积一第一金属材料。
3.如权利要求2所述的制备方法，其中该第二互连结构的形成步骤还包括：
形成一第一切槽，该第一切槽穿经该第二基底、该第二层间介电层以及该接合介电质，以暴露该第一金属材料；
形成一第二切槽，该第二切槽穿经该第二基底并穿入该第二层间介电层，以暴露所述多个第二导体其中之一；
形成一凹口，该凹口连通该第一切槽与该第二切槽；以及
在该第一切槽、该第二切槽以及该凹口内沉积一第二金属材料。
4.如权利要求3所述的制备方法，还包括：
在沉积该第一金属材料之前，沿着该第一后表面与该第一开口沉积一第一隔离层；
移除该第一隔离层的一部分，以暴露所述多个第一导体其中之一；
在该第二金属材料沉积之前，沿着该第二基底的一第二后表面、该凹口、该第一切槽以及该第二切槽沉积一第二隔离层；以及
移除该第二隔离层的多个部分，以暴露所述多个第二导体其中之一以及该第一金属材料。
5.如权利要求4所述的制备方法，还包括：
在该第一金属材料沉积之前，在该第一隔离层上与所述多个第一导体其中之一上沉积一第一阻障层；以及
在该第二金属材料沉积之前，在该第二金属材料上与所述多个第二金属接触点其中之一上沉积一第二阻障层。
6.如权利要求5所述的制备方法，还包括：
执行一第一平坦化工艺，以移除位在该第一隔离层上的该第一金属材料与该第一阻障层的所述多个部分；以及
执行一第二平坦化工艺，以移除位在该第二隔离层上的该第二金属材料与该第二阻障层的所述多个部分。
7.如权利要求2所述的制备方法，其中该第一互连结构的形成步骤还包括：
在该第一金属材料沉积之前，形成一第二开口，该第二开口连通在该第一基底内的该第一开口；以及
在该第二开口内沉积该第一金属材料。
8.如权利要求7所述的制备方法，其中该第二开口具有一大致前后一致的直径，且该第一开口具有一直径，其是朝向远离该第一后表面的方向递减，其中该第一开口的该直径小于该第二开口的该直径。
9.如权利要求8所述的制备方法，其中该第一开口具有一中线，其是偏离该第二开口的一中线。
10.如权利要求1所述的制备方法，还包括：
在第二后表面上沉积一钝化层；以及
形成一外部接触点，该外部接触点接触该第二互连结构。
11.如权利要求1所述的制备方法，还包括：
在提供该第一晶圆之前，提供一载体晶圆；
在该载体晶圆上形成一接合层；以及
在该载体晶圆上接合该第一晶圆，其中该第一层间介电层接触该接合层。
12.如权利要求11所述的制备方法，还包括在将该第一晶圆接合到该载体晶圆之后，使该第一基底变薄。
13.如权利要求12所述的制备方法，还包括在第二金属材料形成之后，研磨该载体晶圆。
14.如权利要求1所述的制备方法，其中该第一互连结构包括：
一平台；以及
一突出物，从该平台延伸并接触该第一导体。
15.如权利要求1所述的制备方法，其中该第二互连结构包括：
一基座；
一第一支脚，从该基座延伸并接触所述多个第二导体其中之一；以及
一第二支脚，从该基座延伸并接触该第一互连结构。
CN201911016679.2A 2019-05-07 2019-10-24 半导体装置的制备方法 Pending CN111916392A (zh)

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