CN111900992A - Analog-digital converter based on incremental modulation - Google Patents
Analog-digital converter based on incremental modulation Download PDFInfo
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- 239000013598 vector Substances 0.000 claims description 3
- 238000000605 extraction Methods 0.000 abstract description 9
- 238000013075 data extraction Methods 0.000 abstract description 2
- 238000013139 quantization Methods 0.000 description 11
- 238000004364 calculation method Methods 0.000 description 4
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/02—Delta modulation, i.e. one-bit differential modulation
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Abstract
The invention discloses an analog-to-digital converter based on delta modulation, which comprises an anti-aliasing filter, a delta modulator and a digital decimation filtering module; the input end of the anti-aliasing filter receives an analog signal to be converted, the output end of the anti-aliasing filter is connected with the incremental modulator, and the output end of the incremental modulator outputs an obtained digital signal through the digital decimation filtering module. When the incremental modulator is designed, firstly, the first integrator is used for integrating the input signal, so that the amplitude of the high-frequency component of the signal is reduced, the slope of the signal is reduced, and then, the incremental modulator is used for carrying out incremental modulation, so that the problem of signal slope overload is effectively avoided; when the digital extraction filtering module is designed, multiple cascade accumulation operations are carried out on data at a high sampling rate, then data extraction is carried out in a down-sampling mode, and multiple cascade differential operations are carried out, so that effective combination of digital filtering and extraction is realized, and the stability of data processing can be ensured.
Description
Technical Field
The present invention relates to analog-to-digital conversion, and more particularly, to an analog-to-digital converter based on delta modulation.
Background
In an ADC (sigma-delta ADC) including a sigma-delta modulator (also called a sigma-delta modulator), if a sampling interval is small, the signal amplitude between adjacent sampling points does not change much for a continuous signal, and if the difference between two points before and after the sampling point is quantized, the information included in the continuous signal can be replaced by the difference. In a delta modulator, a quantizer is used to quantize the difference between two sample points and the quantized difference is summed by an integrator to form a final sample value. The quantization noise of the delta modulator consists of two parts, namely ordinary quantization noise and overload quantization noise. When the sampling interval is small enough and the signal amplitude variation does not exceed the quantization step delta, the quantization noise is common quantization noise. In a sampling interval, the amplitude change of the signal exceeds a quantization step, namely when the slope overload exists and the integrator cannot track the change of the signal, the quantization noise is overload noise, obviously, the slope overload of the signal influences the performance of the incremental modulator;
meanwhile, for the signal output by the delta modulator, after the sigma-delta modulator shapes the quantization noise, the quantization noise is moved out of the frequency band of interest, and the shaped quantization noise can be filtered out by using a digital filter. In sigma-delta ADCs, decimation is often combined with digital filtering. This may improve computational efficiency. As is well known, a Finite Impulse Response (FIR) filter simply performs a flow weighted average calculation on input sample values (the weight is determined by each coefficient of the filter). In the usual case, one filter output should be applied for each input sample value. However, if decimation of the filter output is desired, i.e., resampling of the filter output at a lower frequency, it is not necessary to perform the filter output calculation for each sampled input. In this case, the calculation is performed only at the rate of extraction, which can greatly improve the efficiency of the calculation process. However, if an Infinite Impulse Response (IIR) filter is used, it is not possible to combine digital filtering with decimation because of the feedback contained therein.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide an analog-to-digital converter based on delta modulation, which can effectively avoid the influence of signal slope overload on a delta modulator, realize the effective combination of digital filtering and extraction and ensure the stability of data processing.
The purpose of the invention is realized by the following technical scheme: an analog-to-digital converter based on delta modulation comprises an anti-aliasing filter, a delta modulator and a digital decimation filtering module;
the input end of the anti-aliasing filter receives an analog signal to be converted, the output end of the anti-aliasing filter is connected with the incremental modulator, and the output end of the incremental modulator outputs an obtained digital signal through the digital decimation filtering module.
The delta modulator comprises a first integrator, a differential amplifier, a quantizer, a second integrator, a differentiator, a third integrator and a 1-bit DAC;
the input end of the first integrator is connected with an analog signal output by the anti-aliasing filter, the output end of the first integrator is connected with the non-inverting input end of the differential amplifier, the output end of the differential amplifier is connected with the quantizer, the output end of the quantizer is respectively connected with the second integrator and the third integrator, the output end of the third integrator is connected with the inverting input end of the differential amplifier through a 1-bit DAC, the output end of the second integrator is connected with the differentiator, and the differentiator outputs a signal outwards and transmits the signal to the digital decimation filtering module.
The digital decimation filtering module comprises a down sampler, an accumulation filtering module and a differential filtering module;
the accumulation filtering module comprises a plurality of cascaded accumulation filtering units; each accumulation filtering unit comprises an adder and a first low-pass filter;
in each accumulation filtering unit, a first input end of an adder is connected with a signal input port connected to the accumulation filtering unit, an output end of the adder is connected with a first low-pass filter, an output end of the first low-pass filter is connected with a signal output port of the accumulation filtering unit, and an output end of the first low-pass filter is also connected with a second output end of the adder;
in any two adjacent accumulation filter units, the signal output port of the last accumulation filter unit is connected with the signal input port of the next accumulation filter unit, the signal input port of the first accumulation filter unit receives a signal from an incremental modulator, and the output port of the last accumulation filter unit is connected with a down sampler; the output end of the down sampler is connected with the differential filtering module;
the differential filtering module comprises a plurality of cascaded differential filtering units, and each differential filtering unit comprises a differentiator and a second low-pass filter;
in each differential filtering unit, the input end of a second low-pass filter and the non-inverting input end of a differentiator are connected to the input port of the differential filtering unit, the output end of the second low-pass filter is connected with the inverting input end of the differentiator, and the output end of the differentiator is connected to the output port of the differential filtering unit;
in the differential filter units of any two vectors, the output port of the last differential filter unit is connected to the input port of the next differential filter unit, the input port of the first differential filter unit is connected with the output end of the down sampler, and the output port of the last differential filter unit outputs the processed signal to the outside.
The invention has the beneficial effects that: when the incremental modulator is designed, firstly, the first integrator is used for integrating an input signal to reduce the amplitude of a high-frequency component of the signal and reduce the slope of the signal, then, the incremental modulator is used for carrying out incremental modulation, so that the problem of signal slope overload is effectively avoided, and before a final result is output, the differentiator is used for carrying out primary differentiation on the signal and then outputting the signal, so that the frequency loss caused by integration is effectively compensated; when the digital extraction filtering module is designed, multiple cascade accumulation operations are carried out on data at a high sampling rate, then data extraction is carried out in a down-sampling mode to obtain signals at a low sampling rate, and multiple cascade differential operations are carried out, so that effective combination of digital filtering and extraction is realized, and the stability of data processing can be ensured.
Drawings
FIG. 1 is a functional block diagram of the present invention;
FIG. 2 is a schematic diagram of a delta modulator;
fig. 3 is a functional block diagram of a digital decimation filtering module.
Detailed Description
The technical solutions of the present invention are further described in detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the following.
As shown in fig. 1, an analog-to-digital converter based on delta modulation includes an anti-aliasing filter, a delta modulator and a digital decimation filtering module;
the input end of the anti-aliasing filter receives an analog signal to be converted, the output end of the anti-aliasing filter is connected with the incremental modulator, and the output end of the incremental modulator outputs an obtained digital signal through the digital decimation filtering module.
As shown in fig. 2, the delta modulator includes a first integrator, a differential amplifier, a quantizer, a second integrator, a differentiator, a third integrator, and a 1-bit DAC;
the input end of the first integrator is connected with an analog signal output by the anti-aliasing filter, the output end of the first integrator is connected with the non-inverting input end of the differential amplifier, the output end of the differential amplifier is connected with the quantizer, the output end of the quantizer is respectively connected with the second integrator and the third integrator, the output end of the third integrator is connected with the inverting input end of the differential amplifier through a 1-bit DAC, the output end of the second integrator is connected with the differentiator, and the differentiator outputs a signal outwards and transmits the signal to the digital decimation filtering module.
In the embodiment of the present application, the quantizer adopts a latching comparator, and the function of the 1-bit ADC is realized by the latching comparator. The non-inverting input end of the latching comparator is connected with the output end of the differential amplifier, the inverting input end of the latching comparator is grounded, and the output ends of the latching comparator are respectively connected with the second integrator and the third integrator. The delta modulator further comprises a sampling clock input port, wherein the sampling clock input port is connected with a clock port of the latching comparator and used for receiving an external sampling clock and providing a clock base for the latching comparator.
As shown in fig. 3, the digital decimation filtering module includes a down sampler, an accumulation filtering module and a differential filtering module;
the accumulation filtering module comprises a plurality of cascaded accumulation filtering units; each accumulation filtering unit comprises an adder and a first low-pass filter;
in each accumulation filtering unit, a first input end of an adder is connected with a signal input port connected to the accumulation filtering unit, an output end of the adder is connected with a first low-pass filter, an output end of the first low-pass filter is connected with a signal output port of the accumulation filtering unit, and an output end of the first low-pass filter is also connected with a second output end of the adder;
in any two adjacent accumulation filter units, the signal output port of the last accumulation filter unit is connected with the signal input port of the next accumulation filter unit, the signal input port of the first accumulation filter unit receives a signal from an incremental modulator, and the output port of the last accumulation filter unit is connected with a down sampler; the output end of the down sampler is connected with the differential filtering module;
the differential filtering module comprises a plurality of cascaded differential filtering units, and each differential filtering unit comprises a differentiator and a second low-pass filter;
in each differential filtering unit, the input end of a second low-pass filter and the non-inverting input end of a differentiator are connected to the input port of the differential filtering unit, the output end of the second low-pass filter is connected with the inverting input end of the differentiator, and the output end of the differentiator is connected to the output port of the differential filtering unit;
in the differential filter units of any two vectors, the output port of the last differential filter unit is connected to the input port of the next differential filter unit, the input port of the first differential filter unit is connected with the output end of the down sampler, and the output port of the last differential filter unit outputs the processed signal to the outside.
For an input analog signal, the input analog signal is firstly filtered through an anti-aliasing filter, then the obtained signal is subjected to primary integration (equivalent to low-pass filtering) through a first integrator, the amplitude of a high-frequency component of the signal is reduced, the slope of the signal is reduced, then incremental modulation is carried out, and primary differentiation is inevitably carried out before a final result is output so as to compensate frequency loss caused by integration; assuming that the sampling clock of the external output is Kfs, the quantizer converts the input signal into modulated pulses of a continuous serial bit stream of 1's and 0's at a sampling rate of Kfs; at a certain sampling point, the signal output by the quantizer is transmitted to the differentiator through the second differentiator and is output by the differentiator; after signals output by the quantizer are simultaneously transmitted to a third integrator for integration, the signals are converted by a 1-bit DAC and fed back to the inverting input end of the differential amplifier, and then the differential amplifier transmits the difference value between the fed back signals and the signals of the next sampling point to the quantizer; the modulation pulse output by the modulator already contains all information of signal amplitude, the information is expressed as the duty ratio of the modulation pulse, and a digital signal (modulation pulse) obtained by modulation is transmitted to the digital extraction filtering module; in the digital extraction filtering module, the accumulation filtering module is composed of a plurality of cascaded accumulation filtering units, each stage accumulates input data, the obtained signal is sent to a down sampler for down sampling, the signal obtained by down sampling is sent to a differential filtering module, and the final filtering result is obtained by three times of differential processing in the differential filtering module. Because the data is subjected to multiple cascade accumulation operations at a high sampling rate, then the data is extracted in a down-sampling mode to obtain a signal with a low sampling rate, and then the differential operations of multiple cascade are carried out, the effective combination of digital filtering and extraction is realized, and the stability of data processing can be ensured.
Finally, it should be noted that the above is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, many modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (6)
1. An analog-to-digital converter based on delta modulation, characterized by: the system comprises an anti-aliasing filter, a delta modulator and a digital decimation filtering module;
the input end of the anti-aliasing filter receives an analog signal to be converted, the output end of the anti-aliasing filter is connected with the incremental modulator, and the output end of the incremental modulator outputs an obtained digital signal through the digital decimation filtering module.
2. A delta modulation based analog to digital converter according to claim 1, characterized in that: the delta modulator comprises a first integrator, a differential amplifier, a quantizer, a second integrator, a differentiator, a third integrator and a 1-bit DAC;
the input end of the first integrator is connected with an analog signal output by the anti-aliasing filter, the output end of the first integrator is connected with the non-inverting input end of the differential amplifier, the output end of the differential amplifier is connected with the quantizer, the output end of the quantizer is respectively connected with the second integrator and the third integrator, the output end of the third integrator is connected with the inverting input end of the differential amplifier through a 1-bit DAC, the output end of the second integrator is connected with the differentiator, and the differentiator outputs a signal outwards and transmits the signal to the digital decimation filtering module.
3. A delta modulation based analog to digital converter according to claim 2, characterized in that: the quantizer adopts a latching comparator, and the function of the 1-bit ADC is realized through the latching comparator.
4. A delta modulation based analog to digital converter according to claim 1, characterized in that: the non-inverting input end of the latching comparator is connected with the output end of the differential amplifier, the inverting input end of the latching comparator is grounded, and the output ends of the latching comparator are respectively connected with the second integrator and the third integrator.
5. A delta modulation based analog to digital converter according to claim 1, characterized in that: the delta modulator further comprises a sampling clock input port, wherein the sampling clock input port is connected with a clock port of the latching comparator and used for receiving an external sampling clock and providing a clock base for the latching comparator.
6. A delta modulation based analog to digital converter according to claim 1, characterized in that: the digital decimation filtering module comprises a down sampler, an accumulation filtering module and a difference filtering module;
the accumulation filtering module comprises a plurality of cascaded accumulation filtering units; each accumulation filtering unit comprises an adder and a first low-pass filter;
in each accumulation filtering unit, a first input end of an adder is connected with a signal input port connected to the accumulation filtering unit, an output end of the adder is connected with a first low-pass filter, an output end of the first low-pass filter is connected with a signal output port of the accumulation filtering unit, and an output end of the first low-pass filter is also connected with a second output end of the adder;
in any two adjacent accumulation filter units, the signal output port of the last accumulation filter unit is connected with the signal input port of the next accumulation filter unit, the signal input port of the first accumulation filter unit receives a signal from an incremental modulator, and the output port of the last accumulation filter unit is connected with a down sampler; the output end of the down sampler is connected with the differential filtering module;
the differential filtering module comprises a plurality of cascaded differential filtering units, and each differential filtering unit comprises a differentiator and a second low-pass filter;
in each differential filtering unit, the input end of a second low-pass filter and the non-inverting input end of a differentiator are connected to the input port of the differential filtering unit, the output end of the second low-pass filter is connected with the inverting input end of the differentiator, and the output end of the differentiator is connected to the output port of the differential filtering unit;
in the differential filter units of any two vectors, the output port of the last differential filter unit is connected to the input port of the next differential filter unit, the input port of the first differential filter unit is connected with the output end of the down sampler, and the output port of the last differential filter unit outputs the processed signal to the outside.
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Cited By (3)
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| CN112968703A (en) * | 2021-05-18 | 2021-06-15 | 北京思凌科半导体技术有限公司 | Control circuit of analog-to-digital converter and electronic equipment |
| CN115694511A (en) * | 2022-12-30 | 2023-02-03 | 深圳芯盛思技术有限公司 | Continuous time Sigma-Delta analog-to-digital conversion system and operation method and application thereof |
| CN117526957A (en) * | 2024-01-04 | 2024-02-06 | 秦玄汉(苏州)信息科技有限公司 | Analog-to-digital converter with optimal quantization bit number |
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