CN212969612U - Incremental modulator capable of avoiding signal slope overload - Google Patents
Incremental modulator capable of avoiding signal slope overload Download PDFInfo
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- CN212969612U CN212969612U CN202021915222.3U CN202021915222U CN212969612U CN 212969612 U CN212969612 U CN 212969612U CN 202021915222 U CN202021915222 U CN 202021915222U CN 212969612 U CN212969612 U CN 212969612U
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Abstract
The utility model discloses an incremental modulator for avoiding signal slope overload, which comprises a first integrator, a differential amplifier, a quantizer, a second integrator, a differentiator, a third integrator and a 1-bit DAC; the input end of the first integrator is connected with an analog signal to be processed, the output end of the first integrator is connected with the non-inverting input end of the differential amplifier, the output end of the differential amplifier is connected with the quantizer, the output end of the quantizer is respectively connected with the second integrator and the third integrator, the output end of the third integrator is connected with the inverting input end of the differential amplifier through a 1-bit DAC, the output end of the second integrator is connected with the differentiator, and the differentiator outputs a signal outwards. The utility model discloses at first carry out the integral to input signal through first integrator, make signal high frequency component amplitude descend, reduce the slope of signal, then carry out the incremental modulation again, and then effectively avoided the overloaded problem of signal slope.
Description
Technical Field
The present invention relates to analog-to-digital conversion, and more particularly to a delta modulator for avoiding signal slope overload in an analog-to-digital converter.
Background
In an ADC including a sigma-delta modulator (also referred to as an integrated delta modulator), if the sampling interval is small, the signal amplitude between adjacent sampling points does not change much for a continuous signal, and if the difference between two points before and after the sampling interval is quantized, the information included in the continuous signal can be replaced. In a delta modulator, a quantizer is used to quantize the difference between two sample points and the quantized difference is summed by an integrator to form a final sample value. The quantization noise of the delta modulator consists of two parts, namely ordinary quantization noise and overload quantization noise. When the sampling interval is small enough and the signal amplitude variation does not exceed the quantization step delta, the quantization noise is common quantization noise.
In a sampling interval, the amplitude change of the signal exceeds the quantization step, that is, when slope overload exists and the integrator cannot track the change of the signal, the quantization noise is overload noise, and obviously, the slope overload of the signal affects the performance of the delta modulator.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to overcome prior art not enough, provide an avoid overloaded incremental modulator of signal slope, at first carry out the integral to input signal through first integrator, make signal high frequency component amplitude descend, reduce the slope of signal, then carry out incremental modulation again, and then effectively avoided the overloaded problem of signal slope.
The purpose of the utility model is realized through the following technical scheme: a delta modulator for avoiding signal slope overload comprises a first integrator, a differential amplifier, a quantizer, a second integrator, a differentiator, a third integrator and a 1-bit DAC;
the input end of the first integrator is connected with an analog signal to be processed, the output end of the first integrator is connected with the non-inverting input end of the differential amplifier, the output end of the differential amplifier is connected with the quantizer, the output end of the quantizer is respectively connected with the second integrator and the third integrator, the output end of the third integrator is connected with the inverting input end of the differential amplifier through a 1-bit DAC, the output end of the second integrator is connected with the differentiator, and the differentiator outputs a signal outwards.
The quantizer adopts a latching comparator, and the function of the 1-bit ADC is realized through the latching comparator. The non-inverting input end of the latching comparator is connected with the output end of the differential amplifier, the inverting input end of the latching comparator is grounded, and the output ends of the latching comparator are respectively connected with the second integrator and the third integrator. The delta modulator further comprises a sampling clock input port, wherein the sampling clock input port is connected with a clock port of the latching comparator and used for receiving an external sampling clock and providing a clock base for the latching comparator.
The utility model has the advantages that: the utility model discloses at first carry out the integration through first integrator to input signal, make signal high frequency component amplitude descend, reduce the slope of signal, then carry out the incremental modulation again, and then effectively avoided the overloaded problem of signal slope, before final result output, carry out the differential back output through the differentiator to the signal, effectively compensated the frequency loss that the integration arouses.
Drawings
Fig. 1 is a schematic block diagram of the present invention.
Detailed Description
The technical solution of the present invention is described in further detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the following description.
As shown in fig. 1, a delta modulator for avoiding signal slope overload comprises a first integrator, a differential amplifier, a quantizer, a second integrator, a differentiator, a third integrator, and a 1-bit DAC;
the input end of the first integrator is connected with an analog signal to be processed, the output end of the first integrator is connected with the non-inverting input end of the differential amplifier, the output end of the differential amplifier is connected with the quantizer, the output end of the quantizer is respectively connected with the second integrator and the third integrator, the output end of the third integrator is connected with the inverting input end of the differential amplifier through a 1-bit DAC, the output end of the second integrator is connected with the differentiator, and the differentiator outputs a signal outwards.
In the embodiment of the present application, the quantizer adopts a latching comparator, and the function of the 1-bit ADC is realized by the latching comparator. The non-inverting input end of the latching comparator is connected with the output end of the differential amplifier, the inverting input end of the latching comparator is grounded, and the output ends of the latching comparator are respectively connected with the second integrator and the third integrator. The delta modulator further comprises a sampling clock input port, wherein the sampling clock input port is connected with a clock port of the latching comparator and used for receiving an external sampling clock and providing a clock base for the latching comparator.
The utility model discloses carry out the integration once (being equivalent to low pass filtering) with the signal through first integrator, make signal high frequency component amplitude descend, reduce the slope of signal, then carry out the incremental modulation again, must carry out the differentiation once more before final result is exported in order to compensate the frequency loss that the integration arouses; assuming that the sampling clock of the external output is Kfs, the quantizer converts the input signal into modulated pulses of a continuous serial bit stream of 1's and 0's at a sampling rate of Kfs; at a certain sampling point, the signal output by the quantizer is transmitted to the differentiator through the second differentiator and is output by the differentiator; after signals output by the quantizer are simultaneously transmitted to a third integrator for integration, the signals are converted by a 1-bit DAC and fed back to the inverting input end of the differential amplifier, and then the differential amplifier transmits the difference value between the fed back signals and the signals of the next sampling point to the quantizer; the modulation pulse output by the modulator already contains all the information of the signal amplitude, and is represented as the duty ratio of the modulation pulse.
Finally, it should be noted that the above is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.
Claims (4)
1. A delta modulator for avoiding signal slope overload, comprising: the DAC comprises a first integrator, a differential amplifier, a quantizer, a second integrator, a differentiator, a third integrator and 1 bit;
the input end of the first integrator is connected with an analog signal to be processed, the output end of the first integrator is connected with the non-inverting input end of the differential amplifier, the output end of the differential amplifier is connected with the quantizer, the output end of the quantizer is respectively connected with the second integrator and the third integrator, the output end of the third integrator is connected with the inverting input end of the differential amplifier through a 1-bit DAC, the output end of the second integrator is connected with the differentiator, and the differentiator outputs a signal outwards.
2. A delta modulator for avoiding signal slope overload as claimed in claim 1, wherein: the quantizer adopts a latching comparator, and the function of the 1-bit ADC is realized through the latching comparator.
3. A delta modulator for avoiding signal slope overload as claimed in claim 2, wherein: the non-inverting input end of the latching comparator is connected with the output end of the differential amplifier, the inverting input end of the latching comparator is grounded, and the output ends of the latching comparator are respectively connected with the second integrator and the third integrator.
4. A delta modulator for avoiding signal slope overload as claimed in claim 1, wherein: the delta modulator further comprises a sampling clock input port, wherein the sampling clock input port is connected with a clock port of the latching comparator and used for receiving an external sampling clock and providing a clock base for the latching comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021915222.3U CN212969612U (en) | 2020-09-04 | 2020-09-04 | Incremental modulator capable of avoiding signal slope overload |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021915222.3U CN212969612U (en) | 2020-09-04 | 2020-09-04 | Incremental modulator capable of avoiding signal slope overload |
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| CN212969612U true CN212969612U (en) | 2021-04-13 |
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| CN202021915222.3U Active CN212969612U (en) | 2020-09-04 | 2020-09-04 | Incremental modulator capable of avoiding signal slope overload |
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