CN111224669A - Design method of sigma-delta modulator for realizing wide input - Google Patents

Design method of sigma-delta modulator for realizing wide input Download PDF

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CN111224669A
CN111224669A CN202010161861.3A CN202010161861A CN111224669A CN 111224669 A CN111224669 A CN 111224669A CN 202010161861 A CN202010161861 A CN 202010161861A CN 111224669 A CN111224669 A CN 111224669A
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output
gain unit
integrator
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CN111224669B (en
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袁冰
杨永存
王炳源
霍艳丽
项婷婷
来新泉
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Xidian University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/414—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
    • H03M3/51—Automatic control for modifying converter range

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Abstract

the invention provides a design method of a sigma-delta modulator for realizing wide input, which aims to widen the amplitude range of analog signals received by a receiving end of the sigma-delta modulator and comprises the steps of constructing a sigma-delta modulator model, setting the type of an integrator, setting the parameters of the sigma-delta modulator and estimating the gain coefficient of each gain unit.

Description

Design method of sigma-delta modulator for realizing wide input
Technical Field
The invention belongs to the technical field of integrated circuits, and relates to a design method for realizing a sigma-delta modulator with a wide amplitude range, which can be used for designing the sigma-delta modulator.
Background
Sigma-delta modulators have a wide range of applications in integrated circuits, in particular microelectromechanical digital microphones. An acquisition unit in the micro-electro-mechanical digital microphone converts an acoustic signal into an electric signal and outputs the electric signal to a sigma-delta modulator, and a receiving end of the sigma-delta modulator receives the electric signal to modulate and output a high-frequency low-precision digital signal. At present, the range of the amplitude of the signal received by the receiving end of most sigma-delta modulators is small, when the amplitude of the electrical signal output by the acquisition unit in the mems digital microphone is large, the sigma-delta modulator is easy to enter an unstable state, and once the sigma-delta modulator enters the unstable state, the receiving end signal cannot be operated again even if the signal is reduced to a small value.
The traditional sigma-delta modulator comprises a feedforward structure and a feedback structure according to structural classification, wherein the feedforward structure comprises a cascade integral feedforward structure CIFF and a cascade resonance feedforward structure CRFF, and the feedback structure comprises a cascade integral feedback structure CIFB and a cascade resonance feedback structure CRFB; the sigma-delta modulator comprises a receiving end, an integrator, an adder, a gain unit, a sampling unit, a quantizer and a digital-to-analog converter (DAC), quantization noise is introduced into the quantizer in the quantization process, the sampling unit samples at a sampling rate far greater than the Nyquist sampling frequency, so that the quantization noise is distributed in a wider frequency band, the adder, the integrator and the ADC form a feedback loop or a feedforward loop to realize noise shaping, the more the integrators, the more components which are used for pushing the quantization noise out of a signal frequency band, the better the realized noise shaping effect and the larger the signal-to-noise distortion ratio (SNDR);
most of the existing design methods of Sigma-Delta modulators firstly construct a feedforward type or feedback type Sigma-Delta modulator model, then set various parameters of an integrator type and the Sigma-Delta modulator, and obtain the Sigma-Delta modulators of CIFF, CRFF, CIFB or CRFB types through a Sigma-Delta toolkit according to gain coefficients of various gain units of the constructed model, and the signal-to-noise ratio SNDR and the effective digit ENOB of the designed Sigma-Delta modulator can be measured by connecting a power spectrum analyzer PSD at the output end of a quantizer, so that the first-order and second-order Sigma-Delta modulators realized by the method are unconditionally stable, and the signal amplitude range of a receiving end is very wide;
however, when the amplitude of the signal received by the quantizer is low at the receiving end of the high-order sigma-delta modulator implemented by such a method, the amplitude of the signal received by the quantizer is within the quantization range of the quantizer, that is, the quantizer does not generate an overload phenomenon, but when the amplitude of the signal received by the receiving end is large, because of the large number of integrators, the amplitude of the integrated signal obtained after filtering by each stage of integrator is further increased, and the integrated signal of each stage of integrator is added by the last stage of adder and directly output to the sampling unit for sampling, the amplitude of the output signal of the last stage of adder is large, and easily exceeds the quantization range of the quantizer, that is, the quantizer generates an overload phenomenon, so that the sigma-delta modulator enters an unstable state, and the signal-to-noise-distortion ratio SNDR is sharply reduced; currently, for a sigma-delta modulator design which mainly realizes a wider input signal amplitude range by setting a smaller out-of-band gain, the noise shaping effect of the sigma-delta modulator obtained by the smaller out-of-band gain design is poorer, and the signal-to-noise-distortion ratio SNDR and the effective number ENOB of the sigma-delta modulator are sacrificed; for example, a patent application with publication number CN 109635393 a entitled "a Sigma-Delta modulator design method and system based on distributed algorithm" discloses a Sigma-Delta modulator design method based on distributed algorithm, which sets parameters of a modulator by constructing existing CIFF, CRFF, CIFB, and CRFB type Sigma-Delta modulator models in a Sigma-Delta tool package, acquires gain coefficients of gain units of corresponding structures by using the Sigma-Delta tool package, and performs shift addition conversion on the gain coefficients of the gain units of each stage according to a distributed algorithm substitution formula to acquire binary weighted gain coefficients corresponding to the gain units, thereby implementing the gain unit coefficients. The method can be used for designing the traditional feedforward type or feedback type sigma-delta modulator, and overcomes the defects of complex calculation process and low calculation speed in the prior art; the method has the following disadvantages: according to the method, the integrated signals of the multi-stage integrators are added and directly output to the sampling unit for sampling, so that the amplitude of the signal received by the sampling unit is too large, the amplitude of the discrete signal received by the quantizer cascaded at the output end of the sampling unit exceeds the quantization range of the quantizer, and the designed sigma-delta modulator has the defect of narrow input amplitude range.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a design method for implementing a wide-input sigma-delta modulator, which is intended to widen the amplitude range of an analog signal received by a receiving end of the sigma-delta modulator.
In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:
(1) constructing a sigma-delta modulator model:
constructing a receiving end and L-stage integrator JF comprising cascade connection1,JF2,…JFk,…JFL-1,JFLSampling unit and N-bit quantizer, and L +1 stage adder ADD1,ADD2,…ADDk,…ADDL-1,ADDL,ADDL+1Sigma-delta modulator model of (JF)kRepresenting integrators, ADD, of the k-th orderkRepresents a k-th stage adder; the L + 1-stage adder is sequentially loaded at a receiving end and a first-stage integrator JF1Inter-integrator, inter-adjacent integrator and L-th stage integrator JFLAnd a sampling unit, wherein the adder ADD of the first stage1An N-bit digital-to-analog converter DAC is loaded between the quantizer and the output end of the quantizer and is used for converting the N-bit digital signals quantized by the quantizer into analog signals; the receiving end and the k-th-stage adder ADDkADD of intermediate and L-th stageLAdder ADD of intermediate and L +1 stageL+1Loaded with a k-th stage receiving feedforward gain unit BkL-th stage receiving feedforward gain unit BLL +1 stage receiving feedforward gain unit BL+1(ii) a The kth stage integrator JFkL-th order integrationDevice JFLAnd L +1 th stage adder ADDL+1Between which the kth stage integral feedforward gain unit A is respectively loadedkL-th stage integral feedforward gain unit AL(ii) a The DAC output end and the first-stage adder ADD1A feedback gain unit D is loaded between the two units; the kth stage integrator JFkAnd (k + 1) th stage adder ADDk+1Loaded with a k-th stage forward gain unit C in betweenk(ii) a An amplitude reduction gain unit T is loaded between the L-th stage integrator and the sampling unit and is used for adding an L + 1-th stage adder ADDL+1The output signal of (2) is subjected to amplitude reduction and output; wherein L is an integer of more than or equal to 3, N is an integer of more than or equal to 1, and k is 1,2, … L-1;
(2) setting integrator type:
setting L-stage integrator JF1,JF2,…JFk,…JFL-1,JFLThe middle odd-numbered stage integrator is a delay integrator, the even-numbered stage integrator is a delay integrator or a non-delay integrator, and the Z-domain transfer function of the delay integrator is
Figure BDA0002406083950000031
The Z-domain transfer function of the non-delay integrator is
Figure BDA0002406083950000032
Wherein Z is a Z-domain component.
(3) Setting parameters of the sigma-delta modulator:
let the out-of-band gain and the oversampling ratio of the sigma-delta modulator be | NTF | and OSR, respectively, the gain coefficient of the amplitude reduction gain unit T be β, the minimum quantization level of the quantizer be Δ P, and the amplitude range and frequency of the analog signal Q (T) received by the receiving end be [ -V ] respectivelyrequire,+Vrequire]And finThe bandwidth is BW, the amplitude is V, and the sampling frequency of the sampling unit is fs，fs2 × OSR × BW, and let V ═ Vrequirewhere, NTF is the noise transfer function of the sigma-delta modulator, | | is the modulus, t is the time domain component, OSR > 1, 0 < fin≤BW；
(4) Estimating the gain factor of each gain unit:
(4a) estimating a kth stage receiving feedforward gain unit B by adopting a Sigma-Delta toolkit of MatlabkGain coefficient b ofkL-th stage receiving feedforward gain unit BLGain coefficient b ofLL +1 stage receiving feedforward gain unit BL+1Gain coefficient b ofL+1Kth stage integral feedforward gain unit AkA gain coefficient ofkL-th stage integral feedforward gain unit ALA gain coefficient ofLA gain coefficient D of a feedback gain unit D and a k-th stage forward gain unit CkGain coefficient c ofk；
(4b) L +1 stage adder ADD for measuring gain coefficient beta of amplitude reduction gain unit T by oscilloscopeL+1Peak amplitude END of the output sum signalβAnd determines the peak amplitude | END of the reduction signal DEC (T) output by the amplitude reduction gain unit Tβx β |, maximum quantization level 2 of the quantizerN-1X Δ P, secondary quantization level 2 of the quantizerN-1Whether | END is satisfied between XDeltaP-DeltaPβ×β|∈[2N-1×ΔP-ΔP,2N-1×ΔP]if yes, obtaining the sigma-delta modulator with the gain coefficient of the amplitude reduction gain unit T being beta, otherwise, executing the step (4 c);
(4c) let β be β - Δ β, and perform step (4b), where Δ β is the step size of β.
Compared with the prior art, the invention has the following advantages:
based on the existing sigma-delta modulator, the amplitude reduction gain unit is loaded between the adder at the last stage and the sampling unit, the amplitude of the summation signal output by the adder at the last stage is reduced by β times, and then the reduction signal is output to the sampling unit, so that the amplitude of the signal received by the quantizer cascaded with the output end of the sampling unit is ensured to be within the quantization range of the quantizer, and the reduction of the number of bits of the digital signal output by the quantizer is avoided by ensuring that the peak amplitude of the reduction signal is between the maximum quantization level and the secondary quantization level of the quantizer.
Drawings
FIG. 1 is a flow chart of an implementation of the present invention;
fig. 2 is a schematic structural diagram of a sigma-delta modulator model adopted in the embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and specific examples.
Referring to fig. 1, the present invention includes the steps of:
step 1) constructing a sigma-delta modulator model:
the sigma-delta modulator model shown in fig. 2 is constructed, and includes a receiving end, an L-level integrator, a sampling unit, an N-bit quantizer, an L + 1-level adder, an L + 1-level receiving feedforward gain unit, an L-level integrating feedforward gain unit, an L-1-level forward gain unit, a feedback gain unit D, N bit digital-to-analog converter DAC, and an amplitude reduction gain unit T. In this embodiment, L is 4, and N is 2, and the specific structure is as follows:
receiving end, four-stage integrator JF1,JF2,JF3,JF4The sampling unit and the two-bit quantizer are cascaded in sequence, and the adder ADD at the first stage1Loaded at receiving end and first stage integrator JF1Between, the second-stage adder ADD2Loaded in the first-stage integrator JF1And second stage integrator JF2Between, the third stage adder ADD3Loaded in second stage integrator JF2And a third stage integrator JF3Between, the fourth-stage adder ADD4Loaded in third-stage integrator JF3And a fourth-stage integrator JF4Between, the fifth stage adder ADD5Loaded in fourth-stage integrator JF4And a sampling unit; first stage adder ADD1An N-bit digital-to-analog converter DAC is loaded between the quantizer and the output end of the quantizer and is used for converting the N-bit digital signals quantized by the quantizer into analog signals and outputting the analog signals; receiving end and five-stage adder ADD1,ADD2,ADD3,ADD4,ADD5A first stage receiving feedforward gain unit B is respectively loaded between1Second stage receiving feedforward gain unit B2Third stage receptionFeedforward gain unit B3Fourth stage receiving feedforward gain unit B4A fifth stage receiving feedforward gain unit B5(ii) a Four-stage integrator JF1,JF2,JF3,JF4And fifth stage adder ADD5A first-stage integral feedforward gain unit A is respectively loaded between1Second stage integral feedforward gain unit A2Third stage integral feedforward gain unit A3Fourth stage integral feedforward gain unit A4(ii) a DAC output end of digital-to-analog converter and first-stage adder ADD1A feedback gain unit D is loaded between the two units; first stage integrator JF1And second stage adder ADD2Loaded with a first stage forward gain unit C in between1Second stage integrator JF2And third stage adder ADD3Loaded with a second stage forward gain unit C in between2Third stage integrator JF3And fourth-stage adder ADD2Loaded with a third stage forward gain unit C in between3(ii) a Fourth-stage integrator JF4An amplitude reduction gain unit T is loaded between the sampling unit and the adder ADD of the fifth stage5The output signal of (2) is amplitude-reduced and output.
Step 2) setting the integrator type:
setting a first stage integrator JF1And a third stage integrator JF3For the delay integrator, the Z-domain transfer function is
Figure BDA0002406083950000061
Setting second stage integrator JF2And the fourth-stage integrator is a non-delay integrator, and the Z-domain transfer function is
Figure BDA0002406083950000062
Step 3) setting parameters of the sigma-delta modulator:
the method comprises the steps of setting out-of-band gain and oversampling rate of a sigma-delta modulator to be 1.4 and 64 respectively, setting a gain coefficient β of an amplitude reduction gain unit T, setting an initial value of β to be 1, and enabling β to be gradually changed by step length 0.05, wherein the sigma-delta modulator with the gain coefficient of the amplitude reduction gain unit being 1 is equivalent to a CRFF sigma-delta modulator with a cascade resonance feedforward structure, the sigma-delta modulator has the same signal amplitude range received by a receiving end as a traditional CRFF sigma-delta modulator, setting the amplitude range and frequency of an analog signal Q (T) received by the receiving end to be [ -1.2V, +1.2V ] and 5250Hz respectively, and setting a bandwidth to be 8000Hz, the sampling frequency of the sampling unit to be 1.024MHz, and the minimum quantization level of a quantizer to be 0.5V, wherein V is a voltage unit volt, Hz is a frequency unit Hertz, and MHz is a frequency unit megahertz.
Step 4) estimating the gain coefficient of each gain unit:
step 4a) estimating a first-stage receiving feedforward gain unit B by adopting a Sigma-Delta toolkit of MATLAB1Has a gain coefficient of 0.335, and a second-stage receiving feedforward gain unit B2Third stage receiving feedforward gain unit B3And a fourth stage receiving feedforward gain unit B4All gain coefficients of (1) are 0, and a fifth stage receiving feedforward gain unit B5Has a gain coefficient of 1, and a first-stage integral feedforward gain unit A1Has a gain coefficient of 1.463, and a second stage integral feedforward gain unit A2Has a gain coefficient of 2.009, and a third stage integral feedforward gain unit A3Has a gain coefficient of 1.414, and a fourth-stage integral feedforward gain unit A3Has a gain coefficient of 0.962, a gain coefficient of-0.33 for the feedback gain unit D, and a first stage forward gain unit C1Has a gain coefficient of 0.268, and a second-stage gain unit C2Has a gain coefficient of 0.253, and a third stage gain unit C3Has a gain factor of 0.143.
step 4b) measuring the gain coefficient beta of the amplitude reduction gain unit T by an oscilloscope, and then adding the adder ADD at the fifth stage5Peak amplitude END of the output sum signalβAnd determines the peak amplitude | END of the reduction signal DEC (T) output by the amplitude reduction gain unit Tβif x β | is between the secondary quantization level 0.5V and the maximum quantization level 1V of the quantizer, if yes, the sigma-delta modulator with the gain factor β of the amplitude reduction gain cell T is obtained, otherwise, step 4c) is performed.
step 4c) is to make β -0.05 and step 4b) is performed, i.e. the step of variation of β Δ β is 0.05.
The following are exemplified:
when the step 4b) is executed for the first time, the fifth-stage adder ADD when the gain coefficient of the amplitude reduction gain unit T is 1 is obtained by oscilloscope measurement5Peak amplitude END of the output sum signal1when x 1 is 1.4V, the peak amplitude of the clipping signal DEC (T) output by the amplitude clipping gain unit T is 1.4V, and the peak amplitude of the clipping signal DEC (T) is not between 0.5V and 1V, step 4c) is performed for the first time, that is, β is decreased from 1 to 0.95 and step 4b is performed for the second time;
when the step 4b) is executed for the second time, the fifth-stage adder ADD when the gain coefficient of the amplitude reduction gain unit T is 0.95 is obtained through measurement of an oscilloscope5Peak amplitude END of the output sum signal0.95When the peak amplitude of the reduction signal DEC (T) output from the amplitude reduction gain unit T is equal to 1.35V, END is the peak amplitude0.95when x 0.95 is 1.2825V, the peak amplitude of the clipping signal DEC (t) is not between the secondary quantization level 0.5V and the maximum quantization level 1V of the quantizer, step 4c) is performed for the second time, i.e., β is decreased from 0.95 to 0.9 and step 4b is performed for the third time);
circulating in this way, acquiring END in sequence1,END1-0.05,END1-0.05×2,…END1-0.05×λ…, fifth-stage adder ADD measured the lambda times when step 4b) is performed5The peak amplitude of the output sum signal is END1-0.05×λLambda is an integer of 1 or more and is judged to be |1-0.05 lambda |. END1-0.05×λWhether or not it is in the interval [0.5,1]The above.
Finally, the sigma-delta modulator with the gain coefficient of the amplitude reduction gain unit T being 0.71 is obtained, the amplitude range of the analog signal received by the receiving end of the sigma-delta modulator is [ -1.2V, +1.2V ], which is 33% wider than the amplitude range [ -0.9V, +0.9V ] of the analog signal received by the receiving end of the sigma-delta modulator of the traditional cascade resonance feed-forward CRFF structure.
The operating principle of the sigma-delta modulator with the gain factor of the amplitude reduction gain unit T of 0.71 is as follows:
sigma-delta modulator passing four stagesThe method comprises the steps that a feed-forward path is formed by an integrator, a five-stage adder, an amplitude reduction gain unit, a sampling unit and a quantizer, at the initial moment of power supply, the amplitude of discrete signals received by the quantizer far exceeds the quantization range of the quantizer due to the accumulation effect of a multi-stage integrator, modulation signals cannot be obtained at the output end of the quantizer, a feedback path is formed by loading an analog-to-digital converter and a feedback gain unit D between the output end of the quantizer and a first-stage adder, and the gain coefficient of the feedback gain unit D is a negative value, so that the first-stage adder ADD is enabled to be a negative value1The amplitude of the output sum signal is reduced from the previous time, and therefore the amplitude of the signal loaded into the feed-forward path at the next time is reduced, so that the amplitude of the discrete signal received by the quantizer returns to the quantizer range, and the modulation signal realized by the sigma-delta modulator is obtained at the output end of the quantizer.
Specifically, the receiving end receives and outputs the analog signal Q (t); four-stage integrator JF1,JF2,JF3,JF4Respectively receiving four-stage adder ADD1,ADD2,ADD3,ADD4Output sum signal AD1(t),AD2(t),AD3(t),AD4(t) performing a filtering process and outputting an integrated signal J1(t),J2(t),J3(t),J4(t); three-stage forward gain unit C1,C2,C3Integrator JF1,JF2,JF3Output integral signal J1(t),J2(t),J3(t) amplifying the amplitudes by 0.268,0.253 and 0.143 times respectively and outputting; first-stage receiving feedforward gain unit B1Amplifying the amplitude of the signal Q (t) output by the receiving end by 0.335 times and outputting the signal Q (t), and receiving a feedforward gain unit B2,B3,B4All amplify the amplitude of the signal Q (t) output by the receiving end by 0 times and output, and the fifth stage receiving feedforward gain unit B5Amplifying the amplitude of a signal Q (t) output by a receiving end by 1 time and outputting the signal Q (t); four-stage integral feedforward gain unit A1,A2,A3,A4Will four-stage integrator JF1,JF2,JF3,JF4Output integral signal J1(t),J2(t),J3(t),J4The amplitude of (t) is amplified by 1.463,2.009,1.414 and 0.962 times and output; the sampling unit carries out time domain sampling on a reduced signal DEC (T) output by the amplitude reduction gain unit T at a sampling frequency of 1.024Mhz and outputs a discrete signal; the N-bit quantizer performs amplitude quantization on the discrete signal output by the sampling unit and outputs the discrete signal when the amplitude LS of the discrete signal isdownSatisfy LSdown∈[-1,+1]Then, the quantizer outputs a two-bit digital signal; the digital-to-analog converter DAC converts the two-bit digital signal output by the quantizer into an analog signal DAC (t) and outputs the analog signal DAC (t); the feedback gain unit D amplifies the amplitude of the analog signal DAC (t) output by the digital-to-analog converter DAC by-0.33 times and outputs a feedback signal FOD(t); the amplitude reduction gain unit T ADDs the adder ADD of the fifth stage5Output sum signal AD5(t) the amplitude is reduced by a factor of 0.71 and a reduction signal DEC (t) is output, the amplitude DE of the amplitude reduction signal DEC (t) then being presentdown∈[-1,+1](ii) a First stage adder ADD1Feedback signal FO output by feedback gain unit DD(t) and first stage receive feedforward gain block B1Output received feedforward signal FOB 1(t) add and output so that the next time instant is input to the first stage integrator JF1Is added to the sum signal AD1(t) amplitude reduction, further reducing the amplitude LS of the discrete signal received by the quantizerdown(ii) a Second stage adder ADD2Feed forward gain unit B for receiving second stage2Output received feedforward signal FOB 1(t) and first stage forward gain unit C1Output forward signal FOC 1(t) summing and outputting; third stage adder ADD3Feed forward gain unit B for receiving third stage3Output received feedforward signal FOB 2(t) and a second stage forward gain unit C2Output forward signal FOC 2(t) summing and outputting; fourth stage adder ADD4Feed forward gain unit B for receiving the fourth stage4Output received feedforward signal FOB 3(t) and third stage forward gain unit C2Output forward signal FOC 3(t) summing and outputting; fifth aspect of the inventionStage adder ADD5For integrating four stages by a feed-forward gain unit A1,A2,A3,A4Output integral feedforward signal FOA 1(t),FOA 2(t)，FOA 3(t),FOA 4(t) and fifth stage receiving feedforward gain unit B5Output received feedforward signal FOB 5(t) adding and outputting.

Claims (2)

1. A method for designing a sigma-delta modulator for achieving wide input, comprising the steps of:
(1) constructing a sigma-delta modulator model:
constructing a receiving end and L-stage integrator JF comprising cascade connection1,JF2,…JFk,…JFL-1,JFLSampling unit and N-bit quantizer, and L +1 stage adder ADD1,ADD2,…ADDk,…ADDL-1,ADDL,ADDL+1Sigma-delta modulator model of (JF)kRepresenting integrators, ADD, of the k-th orderkRepresents a k-th stage adder; the L + 1-stage adder is sequentially loaded at a receiving end and a first-stage integrator JF1Inter-integrator, inter-adjacent integrator and L-th stage integrator JFLAnd a sampling unit, wherein the adder ADD of the first stage1An N-bit digital-to-analog converter DAC is loaded between the quantizer and the output end of the quantizer and is used for converting the N-bit digital signals quantized by the quantizer into analog signals; the receiving end and the k-th-stage adder ADDkADD of intermediate and L-th stageLAdder ADD of intermediate and L +1 stageL+1Loaded with a k-th stage receiving feedforward gain unit BkL-th stage receiving feedforward gain unit BLL +1 stage receiving feedforward gain unit BL+1(ii) a The kth stage integrator JFkStage L integrator JFLAnd L +1 th stage adder ADDL+1Between which the kth stage integral feedforward gain unit A is respectively loadedkL-th stage integral feedforward gain unit AL(ii) a The DAC output end and the first-stage adder ADD1A feedback gain unit D is loaded between the two units; the above-mentionedKth stage integrator JFkAnd (k + 1) th stage adder ADDk+1Loaded with a k-th stage forward gain unit C in betweenk(ii) a An amplitude reduction gain unit T is loaded between the L-th stage integrator and the sampling unit and is used for adding an L + 1-th stage adder ADDL+1The output signal of (2) is subjected to amplitude reduction and output; wherein L is an integer of more than or equal to 3, N is an integer of more than or equal to 1, and k is 1,2, … L-1;
(2) setting integrator type:
setting L-stage integrator JF1,JF2,…JFk,…JFL-1,JFLThe middle odd-numbered stage integrator is a delay integrator, the even-numbered stage integrator is a delay integrator or a non-delay integrator, and the Z-domain transfer function of the delay integrator is
Figure FDA0002406083940000011
The Z-domain transfer function of the non-delay integrator is
Figure FDA0002406083940000012
Wherein Z is a Z-domain component.
(3) Setting parameters of the sigma-delta modulator:
let the out-of-band gain and the oversampling ratio of the sigma-delta modulator be | NTF | and OSR, respectively, the gain coefficient of the amplitude reduction gain unit T be β, the minimum quantization level of the quantizer be Δ P, and the amplitude range and frequency of the analog signal Q (T) received by the receiving end be [ -V ] respectivelyrequire,+Vrequire]And finThe bandwidth is BW, the amplitude is V, and the sampling frequency of the sampling unit is fs，fs2 × OSR × BW, and let V ═ Vrequirewhere, NTF is the noise transfer function of the sigma-delta modulator, | | is the modulus, t is the time domain component, OSR > 1, 0 < fin≤BW；
(4) Estimating the gain factor of each gain unit:
(4a) estimating a kth stage receiving feedforward gain unit B by adopting a Sigma-Delta toolkit of MatlabkGain coefficient b ofkL-th stage receiving feedforward gain unit BLGain coefficient b ofLL +1 th stage receive feedforwardGain unit BL+1Gain coefficient b ofL+1Kth stage integral feedforward gain unit AkA gain coefficient ofkL-th stage integral feedforward gain unit ALA gain coefficient ofLA gain coefficient D of a feedback gain unit D and a k-th stage forward gain unit CkGain coefficient c ofk；
(4b) L +1 stage adder ADD for measuring gain coefficient beta of amplitude reduction gain unit T by oscilloscopeL+1Peak amplitude END of the output sum signalβAnd determines the peak amplitude | END of the reduction signal DEC (T) output by the amplitude reduction gain unit Tβx β |, maximum quantization level 2 of the quantizerN-1X Δ P, secondary quantization level 2 of the quantizerN-1Whether | END is satisfied between XDeltaP-DeltaPβ×β|∈[2N-1×ΔP-ΔP,2N-1×ΔP]if yes, obtaining the sigma-delta modulator with the gain coefficient of the amplitude reduction gain unit T being beta, otherwise, executing the step (4 c);
(4c) let β be β - Δ β, and perform step (4b), where Δ β is the step size of β.
2. a method for designing a wide-input sigma-delta modulator according to claim 1, wherein said gain factor β sigma-delta modulator in step (4b) operates according to the following principle:
the receiving end receives and outputs the analog signal Q (t);
kth stage integrator JFkReceiving a k-th stage adder ADDkOutput sum signal ADk(t) performing a filtering process and outputting an integrated signal Jk(t), L-th stage integrator JFLReceiving an L-th stage adder ADDLOutput sum signal ADL(t) performing a filtering process and outputting an integrated signal JL(t)；
Kth stage forward gain unit CkIntegrating signal J output by kth stage integratork(t) amplitude amplification ckMultiplying and outputting;
kth stage receiving feedforward gain unit BkL-th stage receiving feedforward gain unit BLL + C1-stage receiving feedforward gain unit BL+1For amplifying the amplitude b of the signal Q (t) output by the receiving endk、bL、bL+1Multiplying and outputting;
kth stage integral feedforward gain unit AkL-th stage integral feedforward gain unit ALIntegrating the kth stage of integrator JFkOutput integral signal Jk(t) amplitude of each amplification ak、aLMultiplying and outputting;
the sampling unit samples the reduced signal DEC (T) output by the amplitude reduction gain unit T at a sampling frequency fsPerforming time domain sampling and outputting a discrete signal;
the N-bit quantizer performs amplitude quantization on the discrete signal output by the sampling unit and outputs the discrete signal when the amplitude LS of the discrete signal isdownSatisfy LSdown∈[-2N-1×ΔP,+2N-1×ΔP]Then, the quantizer outputs an N-bit digital signal;
the digital-to-analog converter DAC converts the N-bit digital signal output by the quantizer into an analog signal DAC (t) and outputs the analog signal DAC (t);
the feedback gain unit D amplifies the amplitude of the analog signal DAC (t) output by the digital-to-analog converter DAC by D times and outputs a feedback signal FOD(t)；
The amplitude reduction gain unit T ADDs an L +1 stage adder ADDL+1Output sum signal ADL+1(t) reducing the amplitude by a factor of beta and outputting a reduction signal DEC (t), the amplitude DE of whichdown∈[-2N-1×ΔP,+2N-1×ΔP]；
First stage adder ADD1Feedback signal FO output by feedback gain unit DD(t) and first stage receive feedforward gain block B1Output received feedforward signal FOB 1(t) add and output so that the next time instant is input to the first stage integrator JF1Is added to the sum signal AD1(t) amplitude reduction, further reducing the amplitude of the discrete signal received by the quantizer;
when k > 1, the k-th stage adder ADDkFeed forward gain unit B for receiving k stagekOutput received feedforward signal FOB k(t) and (k-1) th stage forward gainUnit Ck-1Output forward signal FOC k-1(t) summing and outputting;
lth-stage adder ADDLFeed-forward gain unit B for receiving L-th stageLOutput received feedforward signal FOB L(t) and L-1 stage forward gain unit CL-1Output forward signal FOC L-1(t) summing and outputting;
adder ADD of L +1 stageL+1Unit A for integrating L-stage feedforward gain1，A2,…Ak…AL-1,ALOutput integral feedforward signal FOA 1(t),FOA 2(t),…FOA k(t),…FOA L-1(t),FOA L(t) and L +1 stage receiving feedforward gain unit BL+1Output received feedforward signal FOB L+1(t) adding and outputting.
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