CN114900189B - MASH delta-sigma modulator with low noise leakage - Google Patents
MASH delta-sigma modulator with low noise leakage Download PDFInfo
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Abstract
A low noise leakage MASH delta sigma modulator comprises a first-stage loop, a second-stage loop and a digital filter, wherein the first-stage loop is cascaded in two stages, the first-stage loop adopts a discrete time structure, the second-stage loop is a continuous time structure running at a higher clock frequency, and a back-end digital filter is matched according to signal transfer functions and noise transfer functions in the two loops: noise transfer function of first-stage loopL 1 represents the order of the first-stage loop, the signal transfer function STF 2a (z) =1 of the second-stage loop, then the first-stage digital filter transfer function H 1 (z) =1, the second-stage digital filter transfer functionOr a signal transfer function of a second-stage loopL 2 represents the order of the second-stage loop, then the first-stage digital filter transfer functionThe transfer function of the second digital filter is stillThe first-stage quantization error E 1 can be eliminated by setting the digital filter according to the above conditions. The sensitivity to noise leakage is low; while effectively increasing the equivalent OSR of the system, thereby enhancing the system's ability to reject quantization noise.
Description
Technical Field
The present invention relates to mixed signal integrated circuits, and more particularly to a low noise leakage MASH delta sigma modulator.
Background
With the continuous progress of digital audio technology, more and more products are carried with analog-to-digital converter (ADC) chips, and the requirements on the ADC are also higher and higher. The commonly-seen ADCs for audio codec require conversion accuracy of at least 13 bits, and mostly belong to the oversampling ADC. As an important component in an oversampling ADC, a delta-sigma modulator (DSM) can enable the system to achieve very high conversion accuracy, while avoiding the requirement for excessive matching accuracy of circuit devices, and in addition, the requirement for anti-aliasing filters is not high, so that the delta-sigma modulator is widely used in the field of audio processing.
Delta-sigma modulators typically employ noise shaping techniques and oversampling techniques to reduce in-band noise of the audio signal and improve conversion accuracy. The effect of noise shaping is positively correlated with the order of the system, but the use of a system above second order to achieve noise shaping causes serious instability problems, considering that higher order systems are nonlinear feedback systems. A delta-sigma modulator of multi-stage noise shaping (MASH) architecture can guarantee high quality noise shaping and good stability and can greatly reduce spurious chordal phenomena. But the performance of this structure is greatly reduced by noise leakage due to mismatch between the analog circuit and the digital filter.
Document [1] (see M.Sanchez-Renedo,S.Paton and L.Hernandez,"A2-2Discrete Time CascadedΣΔModulator with NTF Zero Using Interstage Feedback,"2006 13th IEEE International Conference on Electronics,Circuits and Systems,2006,pp.954-957.) for a discrete-time (DISCRETE TIME, DT) MASH architecture, where the first stage quantization error is easier to extract, and where the sensitivity of the discrete-time integrator to process, voltage and temperature (PVT) variations is low, thus noise leakage effects are low, but where the sampling rate of the architecture is limited by the discrete-time integrator, and thus the oversampling rate (oversampling ratio, OSR) is limited.
Disclosure of Invention
The invention aims to solve the technical problems that: in order to overcome the problems of high sensitivity of the conventional CT MASH structure to noise leakage and limited speed of the conventional DT MASH, a MASH delta sigma modulator with low noise leakage is proposed.
The technical scheme of the invention is as follows:
a low noise leakage MASH delta sigma modulator comprising a two-stage cascaded first stage loop, second stage loop and digital filter, characterized in that:
The first-stage loop comprises a first sampling holder, a first adder, a discrete time loop filter, a first quantizer, a first digital-to-analog converter and a third adder, wherein the output end of the first sampling holder is connected with the first input end of the first adder, the output end of the first adder is connected with the input end of the discrete time loop filter, the discrete time loop filter is provided with a first output end and a second output end, the first output end of the discrete time loop filter is connected with the input end of the first quantizer, the first quantizer is provided with two output ends, the first output end is respectively connected with the input end of the first digital-to-analog converter and the first input end of the third adder, the output end of the first digital-to-analog converter is connected with the second input end of the first adder, and the second output end of the discrete time loop filter is connected with the second input end of the third adder;
The second-stage loop comprises a second adder, a continuous time loop filter, a second sampling holder, a second quantizer and a second digital-to-analog converter, wherein the output end of the third adder is connected with the first input end of the second adder, the output end of the second adder is connected with the input end of the continuous time loop filter, the output end of the continuous time loop filter is connected with the input end of the second sampling holder, the output end of the second sampling holder is connected with the input end of the second quantizer, the second quantizer is provided with two output ends, the first output end of the second quantizer is connected with the input end of the second digital-to-analog converter, and the output end of the second digital-to-analog converter is connected with the second input end of the second adder;
The digital filter comprises an N-times up-sampler, a first-stage digital filter, a second-stage digital filter and a fourth adder, wherein the input end of the N-times up-sampler is connected with the second input end of the first quantizer, the output end of the N-times up-sampler is connected with the first input end of the fourth adder through the first-stage digital filter, the input end of the second-stage digital filter is connected with the second output end of the second quantizer, the output end of the second-stage digital filter is connected with the second input end of the fourth adder, and the output end of the fourth adder is the output end of the modulator;
The signal transfer function of the first-stage loop is STF 1a (z), and the noise transfer function is NTF 1a (z); the signal transfer function of the second-stage loop is STF 2a (z), and the noise transfer function is NTF 2a (z); the quantization noise of the first-stage loop is E 1, the quantization noise of the second-stage loop is E 2, and the quantization noise E 1 of the first-stage loop is used as an input signal of the second-stage loop;
The transfer function of the first stage digital filter of the digital filter is H 1 (z), and the transfer function of the second stage digital filter is H 2 (z); the output Y MASH of the fourth adder is the output of the present MASH delta sigma modulator.
The first stage loop operates at frequency F S1 and the second stage loop operates at frequency F S2＝N·FS1, where N is a constant greater than 1, which may generally be an integer, particularly a power of 2, that is easier to implement.
The transfer function of the first stage digital filter H 1(z)＝STF2a (z), the transfer function of the second stage digital filter H 2(z)＝NTF1a(zN).
Noise transfer function of the first-stage loopL 1 represents the order of the first-stage loop, the signal transfer function STF 2a (z) =1 of the second-stage loop, then the transfer function H 1 (z) =1 of the first-stage digital filter, the second-stage digital filter transfer function/>Or the signal transfer function/>, of the second-stage loopL 2 represents the order of the second-stage loop, the first-stage digital filter transfer function/>The second order digital filter transfer function is still/>
Compared with the prior art, the invention has the beneficial effects that:
1) The invention relates to a MASH delta-sigma modulator with low noise leakage, wherein a first-stage loop adopts a discrete time structure, a second-stage loop adopts a continuous time structure running at a higher clock frequency, and a back-end digital filter is matched according to signal transfer functions and noise transfer functions in the two loops so as to eliminate quantization noise of the first stage. The MASH delta sigma modulator with low noise leakage has low sensitivity to noise leakage; while effectively increasing the equivalent OSR of the system, thereby enhancing the system's ability to reject quantization noise.
2) Compared with the traditional multi-rate DT MASH structure, the structure does not need an additional up-sampler before the second stage, thereby reducing the complexity of the circuit and hardware cost and system power consumption.
3) Compared with the traditional single-rate CT MASH structure, the sensitivity to the change of the integrator coefficient is greatly reduced.
Drawings
Fig. 1 is a schematic diagram of a conventional MASH delta sigma modulator.
Fig. 2 is a schematic diagram of the structure of a multi-rate DT MASH delta-sigma modulator.
Fig. 3 is a schematic diagram of a low noise leakage MASH delta sigma modulator according to the present invention.
Detailed Description
The following detailed description of the embodiments of the present invention, together with the accompanying drawings, is given by way of illustration only, and not by way of limitation. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
In the structural schematic diagram of the conventional MASH delta-sigma modulator shown in fig. 1, two independent low-order loop delta-sigma modulators are connected to realize the high-order noise shaping function, and avoid the instability problem in the loop structure. At the digital back end, the two digital outputs are combined by cascading corresponding digital filters to produce the final output.
The architecture diagram of the multi-rate DT MASH delta-sigma modulator shown in fig. 2. In this configuration, since the second stage is a discrete time loop, a capacitive array based up-sampler is required at the sampling front end of the second stage, first to sample the quantization error of the first stage, and then to hold the sampled state for the next few clock cycles to achieve multi-rate operation.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a MASH delta-sigma modulator according to the present invention, and as can be seen from the drawing, the MASH delta-sigma modulator with low noise leakage according to the present invention includes a first-stage loop, a second-stage loop and a digital filter, which are cascaded in two stages, and is characterized in that:
The first-stage loop comprises a first sampling holder, a first adder, a discrete time loop filter, a first quantizer, a first digital-to-analog converter and a third adder, wherein the output end of the first sampling holder is connected with the first input end of the first adder, the output end of the first adder is connected with the input end of the discrete time loop filter, the discrete time loop filter is provided with a first output end and a second output end, the first output end of the discrete time loop filter is connected with the input end of the first quantizer, the first quantizer is provided with two output ends, the first output end is respectively connected with the input end of the first digital-to-analog converter and the first input end of the third adder, the output end of the first digital-to-analog converter is connected with the second input end of the first adder, and the second output end of the discrete time loop filter is connected with the second input end of the third adder;
The second-stage loop comprises a second adder, a continuous time loop filter, a second sampling holder, a second quantizer and a second digital-to-analog converter, wherein the output end of the third adder is connected with the first input end of the second adder, the output end of the second adder is connected with the input end of the continuous time loop filter, the output end of the continuous time loop filter is connected with the input end of the second sampling holder, the output end of the second sampling holder is connected with the input end of the second quantizer, the second quantizer is provided with two output ends, the first output end of the second quantizer is connected with the input end of the second digital-to-analog converter, and the output end of the second digital-to-analog converter is connected with the second input end of the second adder;
The digital filter comprises an N-times up-sampler, a first-stage digital filter, a second-stage digital filter and a fourth adder, wherein the input end of the N-times up-sampler is connected with the second input end of the first quantizer, the output end of the N-times up-sampler is connected with the first input end of the fourth adder through the first-stage digital filter, the input end of the second-stage digital filter is connected with the second output end of the second quantizer, the output end of the second-stage digital filter is connected with the second input end of the fourth adder, and the output end of the fourth adder is the output end of the modulator;
The signal transfer function of the first-stage loop is STF 1a (z), and the noise transfer function is NTF 1a (z); the signal transfer function of the second-stage loop is STF 2a (z), and the noise transfer function is NTF 2a (z); the quantization noise of the first-stage loop is E 1, the quantization noise of the second-stage loop is E 2, and the quantization noise E 1 of the first-stage loop is used as an input signal of the second-stage loop;
The transfer function of the first-stage digital filter of the digital filter is H 1 (z), and the transfer function of the second-stage digital filter is H 2 (z); the output Y MASH of the fourth adder is the output of the present MASH delta sigma modulator.
The first stage loop operates at frequency F S1 and the second stage loop operates at frequency F S2＝N·FS1, where N is a constant greater than 1, which may generally be an integer, particularly a power of 2, that is easier to implement.
The transfer function H 1(z)＝STF2a (z) of the first-stage digital filter and the transfer function H 2(z)＝NTF1a(zN of the second-stage digital filter.
Noise transfer function of the first-stage loopL 1 represents the order of the first-stage loop, the signal transfer function STF 2a (z) =1 of the second-stage loop, then the transfer function H 1 (z) =1 of the first-stage digital filter, the second-stage digital filter transfer function/>Or the signal transfer function/>, of the second-stage loopL 2 represents the order of the second-stage loop, the first-stage digital filter transfer function/>The second order digital filter transfer function is still/>
Examples
Operating at sampling frequency F S1, while the second stage loop employs a continuous time delta sigma modulator operating at clock frequency F S2＝N·FS1 (N > 1).
The original analog signal is firstly input into a first-stage loop, is processed by a first-stage discrete time loop filter after passing through a sample holder 1, and is then transmitted to a first quantizer 1 for quantization to become a digital signal, and a first-stage digital output Y 1 is generated. At the same time, the output signal Y 1 is converted into an analog signal via the first digital-to-analog converter 1 and is fed back to the input via the adder 1. In addition, the signal after passing through the first digital-to-analog converter 1 and the signal at the front end of the first quantizer 1 generate a first-stage quantization error E 1 by the adder 3.
The first stage quantization error is directly the input signal to the second stage continuous time loop. In the architecture provided by the invention, as the second stage is a continuous time loop, the sampling action of the signal is realized through the following sample and hold module, so that an up-sampler is not needed between the first stage loop and the second stage loop, and the hardware area and the power consumption of the system are reduced.
After the signal input to the second stage by the first stage is processed by the continuous time loop filter, the signal passes through the second sampling holder 2, the module operates with F S2＝N·FS1, the advantage of high speed of the continuous time delta sigma modulator can be fully exerted, and finally the signal passes through the second quantizer 2 to generate a second digital output signal Y 2. Similarly to the first stage, the output signal Y 2 is converted into an analog signal via the second digital-to-analog converter 2 and is fed back to the input via the adder 2.
Next, the digital signal output from the first stage and the digital signal output from the second stage are sent to a specified digital filter for processing. The digital signal Y 1 output by the first stage passes through the up sampler and then is input to the first stage digital filter H 1, the digital signal Y 2 output by the second stage is directly input to the second stage digital filter H 2, and finally the two signals are output to a final system through the fourth adder 4, and the first stage quantization error in the final output is eliminated by selecting a specific digital filter, so that the effects of reducing the system quantization error and improving the resolution are achieved.
Defining STF 1a (z) and NTF 1a (z) as signal transfer function and noise transfer function in the first-stage loop, respectively, STF 2a (z) and NTF 2a (z) as signal transfer function and noise transfer function in the second-stage loop, respectively, and subscript "a" indicates implementation of the corresponding transfer functions in the analog domain.
Further, the digital outputs Y 1 and Y 2 of the two-stage loop can be expressed as:
Y1＝STF1a(z)X+NTF1a(z)E1 (1)
Y2＝STF2a(z)E1+NTF2a(z)E2 (2)
The digital signal Y 1 output by the first stage passes through the up sampler and then is input to the first stage digital filter, the digital signal Y 2 output by the second stage is directly input to the second stage digital filter, the transfer functions of the first stage digital filter and the second stage digital filter are set to be H 1(z)＝STF2d(z),H2(z)＝NTF1d (z) respectively, and the subscript "d" indicates the realization of the corresponding transfer function in the digital domain.
Further, the output signal of the digital filter is passed through a fourth adder 4 to produce the final system output Y MASH:
wherein, the noise leakage term is:
Under the condition NTF 1a(zN)＝NTF1d(z),STF2a(z)＝STF2d (z), the first-stage quantization error E 1 in the final output is eliminated, the noise leakage term becomes zero, and the final output is:
YMASH＝STF1a(zN)STF2d(z)X+NTF2a(z)NTF1d(z)E2 (5)
in this embodiment, the noise transfer function of the first-stage loop L 1 represents the order of the first-stage loop, the signal transfer function STF 2a (z) =1 of the second-stage loop, then the first-stage digital filter transfer function H 1 (z) =1, the second-stage digital filter transfer function/>Or a signal transfer function of a second-stage loopL 2 denotes the order of the second-stage loop, the first-stage digital filter transfer functionThe second order digital filter transfer function is still/>The first-stage quantization error E 1 can be eliminated by setting the digital filter according to the above conditions.
When the actual circuit is implemented, both the digital domain filter functions NTF 1d (z) and STF 2d (z) in equation (4) can be accurately implemented, while the analog domain transfer functions NTF 1a (z) and STF 2a (z) can be affected by PVT variations, which makes NTF 1a(zN)≠NTF1d(z),STF2a(z)≠STF2d (z), E 1, not completely eliminated to generate noise leakage. In addition, NTF 1d (z) in equation (4) has a noise shaping effect, and can shape and suppress noise leakage generated by inaccurate analog domain transfer function STF 2a (z), while STF 2d (z) is a signal transfer function, the gain of which is approximately unity, and noise leakage generated by NTF 1a(zN) according to PVT variations is not suppressed, so that it is important to ensure the accuracy of noise transfer function NTF 1a (z) in the first-stage loop. The first stage of the structure of the invention adopts a discrete time loop filter with low sensitivity to PVT, thus being capable of obtaining more accurate NTF 1a (z) and greatly relieving the noise leakage problem caused by mismatch of an analog filter and a digital filter in a MASH architecture delta-sigma modulator. While the first stage of the conventional DT MASH also employs a discrete time loop to alleviate the noise leakage problem, the structure has poor performance under high frequency clock, and thus the OSR that can be achieved is limited. The invention adopts a continuous time loop with high-speed performance for the second-stage loop, so that the system has higher equivalent OSR.
In summary, the MASH delta sigma modulator with low noise leakage can have higher OSR while relieving the problem of noise leakage, thus greatly increasing the system precision of the modulator.
The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (4)
1. A low noise leakage MASH delta sigma modulator comprising a two-stage cascaded first stage loop, second stage loop and digital filter, characterized by:
The first-stage loop comprises a first sampling holder, a first adder, a discrete time loop filter, a first quantizer, a first digital-to-analog converter and a third adder, wherein the output end of the first sampling holder is connected with the first input end of the first adder, the output end of the first adder is connected with the input end of the discrete time loop filter, the discrete time loop filter is provided with a first output end and a second output end, the first output end of the discrete time loop filter is connected with the input end of the first quantizer, the first quantizer is provided with two output ends, the first output end is respectively connected with the input end of the first digital-to-analog converter and the first input end of the third adder, the output end of the first digital-to-analog converter is connected with the second input end of the first adder, and the second output end of the discrete time loop filter is connected with the second input end of the third adder;
The second-stage loop comprises a second adder, a continuous time loop filter, a second sampling holder, a second quantizer and a second digital-to-analog converter, wherein the output end of the third adder is connected with the first input end of the second adder, the output end of the second adder is connected with the input end of the continuous time loop filter, the output end of the continuous time loop filter is connected with the input end of the second sampling holder, the output end of the second sampling holder is connected with the input end of the second quantizer, the second quantizer is provided with two output ends, the first output end of the second quantizer is connected with the input end of the second digital-to-analog converter, and the output end of the second digital-to-analog converter is connected with the second input end of the second adder;
The digital filter comprises an N-times up-sampler, a first-stage digital filter, a second-stage digital filter and a fourth adder, wherein the input end of the N-times up-sampler is connected with the second input end of the first quantizer, the output end of the N-times up-sampler is connected with the first input end of the fourth adder through the first-stage digital filter, the input end of the second-stage digital filter is connected with the second output end of the second quantizer, the output end of the second-stage digital filter is connected with the second input end of the fourth adder, and the output end of the fourth adder is the output end of the modulator;
the signal transfer function of the first-stage loop is STF 1a (z), and the noise transfer function is NTF 1a (z); the signal transfer function of the second-stage loop is STF 2a (z), and the noise transfer function is NTF 2a (z); wherein the quantization noise of the first stage loop is E 1,
The quantization noise of the second-stage loop is E 2, and the quantization noise E 1 of the first-stage loop is used as an input signal of the second-stage loop;
The transfer function of the first stage digital filter of the digital filter is H 1 (z), and the transfer function of the second stage digital filter is H 2 (z); the output Y MASH of the fourth adder is the output of the present MASH delta sigma modulator.
2. The low noise leakage MASH delta sigma modulator of claim 1, wherein said first stage loop operates at frequency F S1 and said second stage loop operates at frequency F S2＝N·FS1, wherein N is a constant greater than 1.
3. The low noise leakage MASH delta sigma modulator of claim 1, wherein the transfer function of the first stage digital filter H 1(z)＝STF2a (z), the transfer function of the second stage digital filter H 2(z)＝NTF1a(zN).
4. The low noise leakage MASH delta sigma modulator of claim 1, wherein the noise transfer function of the first stage loopL 1 represents the order of the first-stage loop, the signal transfer function STF 2a (z) =1 of the second-stage loop, the transfer function H 1 (z) =1 of the first-stage digital filter, and the second-stage digital filter transfer functionOr the signal transfer function/>, of the second-stage loopL 2 represents the order of the second-stage loop, the first-stage digital filter transfer function/>The transfer function of the second digital filter is still
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