CN114900189B - MASH delta-sigma modulator with low noise leakage - Google Patents

Abstract

A low noise leakage MASH delta sigma modulator comprises a first-stage loop, a second-stage loop and a digital filter, wherein the first-stage loop is cascaded in two stages, the first-stage loop adopts a discrete time structure, the second-stage loop is a continuous time structure running at a higher clock frequency, and a back-end digital filter is matched according to signal transfer functions and noise transfer functions in the two loops: noise transfer function of first-stage loopL ₁ represents the order of the first-stage loop, the signal transfer function STF _2a (z) =1 of the second-stage loop, then the first-stage digital filter transfer function H ₁ (z) =1, the second-stage digital filter transfer functionOr a signal transfer function of a second-stage loopL ₂ represents the order of the second-stage loop, then the first-stage digital filter transfer functionThe transfer function of the second digital filter is stillThe first-stage quantization error E ₁ can be eliminated by setting the digital filter according to the above conditions. The sensitivity to noise leakage is low; while effectively increasing the equivalent OSR of the system, thereby enhancing the system's ability to reject quantization noise.

Description

MASH ΔΣ modulator with low noise leakage

Technical Field

The invention relates to a mixed signal integrated circuit, in particular to a MASH delta-sigma modulator with low noise leakage.

Background technique

With the continuous advancement of digital audio technology, more and more products are equipped with analog-to-digital converter (ADC) chips, and the requirements for ADC are getting higher and higher. The common ADC used for audio encoding and decoding needs to achieve at least 13-bit conversion accuracy, and most of them are oversampling ADCs. As an important component of oversampling ADCs, the delta-sigma modulator (DSM) can enable the system to achieve very high conversion accuracy while avoiding the excessive matching accuracy requirements for circuit components. In addition, its requirements for anti-aliasing filters are not high, so it is widely used in the field of audio processing.

ΔΣ modulators usually use noise shaping technology and oversampling technology to reduce the in-band noise of audio signals and improve conversion accuracy. The effect of noise shaping is positively correlated with the order of the system, but considering that the high-order system is a nonlinear feedback system, using a second-order system or above to implement noise shaping will cause serious instability problems. The ΔΣ modulator with a multi-stage noise shaping (MASH) structure can ensure high-quality noise shaping and good stability, and can greatly reduce the phenomenon of stray string sounds. However, the performance of this structure will be greatly reduced due to the noise leakage caused by the mismatch between the analog circuit and the digital filter.

Reference [1] (see M. Sanchez-Renedo, S. Paton and L. Hernandez, "A2-2 Discrete Time Cascaded ΣΔ Modulator with NTF Zero Using Interstage Feedback," 2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006, pp. 954-957.) adopts a discrete time (DT) MASH structure. The first-level quantization error of this structure is relatively easy to extract, and the discrete time integrator is less sensitive to process, voltage and temperature (PVT) changes, so the noise leakage effect is relatively low. However, the sampling rate of this structure is limited by the discrete time integrator, so the oversampling ratio (OSR) is limited. In order to further improve the oversampling rate, the literature [2] (see L. Qi, S. Sin, S. U, F. Maloberti and R. P. Martins, "A4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1MASHΔΣModulator With Multirate Opamp Sharing," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 10, pp. 2641-2654, Oct. 2017.) adopts a multi-rate DT MASH architecture. However, the multi-rate DT MASH architecture requires the addition of a capacitor array-based upsampler between the two stages, which increases the power consumption and area requirements. Reference [3] (see A. Edward et al., "A 43-mW MASH 2-2CTΣΔModulator Attaining74.4/75.8/76.8dB of SNDR/SNR/DRand 50MHz of BW in 40-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 52, no. 2, pp. 448-459, Feb. 2017.) uses a continuous time (CT) MASH structure to achieve a higher sampling rate. However, the continuous time integrator used in this structure has coefficients that are very sensitive to PVT changes, resulting in serious noise leakage, which limits the final effective accuracy. In addition, in the CT MASH architecture, due to the propagation delay of the quantizer module, it is difficult to accurately extract the first-level quantization error.

Summary of the invention

The technical problem to be solved by the present invention is: in order to overcome the high sensitivity of the traditional CT MASH structure to noise leakage and the problem of limited speed of the traditional DT MASH, a MASH ΔΣ modulator with low noise leakage is proposed.

The technical solution of the present invention is as follows:

A low noise leakage MASH ΔΣ modulator includes a two-stage cascaded first-stage loop, a second-stage loop and a digital filter, and has the following characteristics:

The first-stage loop includes a first sample holder, a first adder, a discrete time loop filter, a first quantizer, a first digital-to-analog converter and a third adder, the output end of the first sample holder is connected to the first input end of the first adder, the output end of the first adder is connected to the input end of the discrete time loop filter, the discrete time loop filter has a first output end and a second output end, the first output end of the discrete time loop filter is connected to the input end of the first quantizer, the first quantizer has two output ends, the first output end is respectively connected to the input end of the first digital-to-analog converter and the first input end of the third adder, the output end of the first digital-to-analog converter is connected to the second input end of the first adder, and the second output end of the discrete time loop filter is connected to the second input end of the third adder;

The second-stage loop includes a second adder, a continuous-time loop filter, a second sample holder, a second quantizer, and a second digital-to-analog converter, the output end of the third adder is connected to the first input end of the second adder, the output end of the second adder is connected to the input end of the continuous-time loop filter, the output end of the continuous-time loop filter is connected to the input end of the second sample holder, the output end of the second sample holder is connected to the input end of the second quantizer, the second quantizer has two output ends, the first output end is connected to the input end of the second digital-to-analog converter, and the output end of the second digital-to-analog converter is connected to the second input end of the second adder;

The digital filter comprises an N-fold upsampler, a first-stage digital filter, a second-stage digital filter and a fourth adder, wherein the input end of the N-fold upsampler is connected to the second input end of the first quantizer, the output end of the N-fold upsampler is connected to the first input end of the fourth adder via the first-stage digital filter, the input end of the second-stage digital filter is connected to the second output end of the second quantizer, the output end of the second-stage digital filter is connected to the second input end of the fourth adder, and the output end of the fourth adder is the output end of the modulator;

The signal transfer function of the first-stage loop is STF _1a (z), and the noise transfer function is NTF _1a (z); the signal transfer function of the second-stage loop is STF _2a (z), and the noise transfer function is NTF _2a (z); wherein the quantization noise of the first-stage loop is E ₁ , and the quantization noise of the second-stage loop is E ₂ , and the quantization noise E ₁ of the first-stage loop is used as the input signal of the second-stage loop;

The transfer function of the first-stage digital filter of the digital filter is H ₁ (z), and the transfer function of the second-stage digital filter is H ₂ (z); the output Y _MASH of the fourth adder is the output of the present MASH ΔΣ modulator.

The first loop operates at a frequency of F _S1 , and the second loop operates at a frequency of F _S2 =N·F _S1 , wherein N is a constant greater than 1, and can generally be an integer, especially a power of 2, which is easier to implement.

The transfer function of the first-stage digital filter is H ₁ (z)=STF _2a (z), and the transfer function of the second-stage digital filter is H ₂ (z)=NTF _1a (z ^N ).

The noise transfer function of the first-stage loop is _L1 represents the order of the first-stage loop. The signal transfer function of the second-stage loop is STF _2a (z) = 1. Then the transfer function of the first-stage digital filter is _H1 (z) = 1. The transfer function of the second-stage digital filter is Or the signal transfer function of the second-level loop/> _L2 represents the order of the second-stage loop, then the first-stage digital filter transfer function is The transfer function of the second-stage digital filter is still / >

The beneficial effects of the present invention compared with the prior art are:

1) The low-noise-leakage MASHΔΣ modulator of the present invention has a discrete-time structure for the first-stage loop and a continuous-time structure for the second-stage loop running at a higher clock frequency. The back-end digital filter matches the signal transfer function and the noise transfer function in the two loops to eliminate the quantization noise of the first stage. The low-noise-leakage MASHΔΣ modulator of the present invention has low sensitivity to noise leakage and effectively improves the equivalent OSR of the system, thereby enhancing the system's ability to suppress quantization noise.

2) Compared with the traditional multi-rate DT MASH structure, the structure of the present invention does not require an additional up-sampler before the second stage, thereby reducing circuit complexity, hardware overhead and system power consumption.

3) Compared with the traditional single-rate CT MASH structure, the sensitivity of the present invention to the change of the integrator coefficient is greatly reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a conventional MASHΔΣ modulator.

FIG. 2 is a schematic diagram of the structure of a multi-rate DT MASH ΔΣ modulator.

FIG3 is a structural schematic diagram of a low noise leakage MASH ΔΣ modulator according to the present invention.

Detailed ways

The following is a detailed and complete description of the technical solutions in the embodiments of the present invention in conjunction with the diagrams in the embodiments of the present invention. The embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of the present invention.

In the structural schematic diagram of the traditional MASH ΔΣ modulator shown in Figure 1, two independent low-order loop ΔΣ modulators are connected to achieve high-order noise shaping functions and avoid instability problems in the loop structure. In the digital backend, the two digital outputs are combined to produce the final output by cascading the corresponding digital filters.

The structural principle diagram of the multi-rate DT MASHΔΣ modulator is shown in Figure 2. In this structure, because the second stage is a discrete time loop, a capacitor array-based upsampler is required at the sampling front end of the second stage to first sample the first-stage quantization error and then maintain the sampling state in the next few clock cycles to achieve multi-rate operation.

Please refer to FIG. 3 , which is a structural principle diagram of the MASH ΔΣ modulator of the present invention. As can be seen from the figure, the MASH ΔΣ modulator with low noise leakage of the present invention comprises a two-stage cascaded first-stage loop, a second-stage loop and a digital filter, and its characteristics are:

The first-stage loop includes a first sample holder, a first adder, a discrete time loop filter, a first quantizer, a first digital-to-analog converter and a third adder, the output end of the first sample holder is connected to the first input end of the first adder, the output end of the first adder is connected to the input end of the discrete time loop filter, the discrete time loop filter has a first output end and a second output end, the first output end of the discrete time loop filter is connected to the input end of the first quantizer, the first quantizer has two output ends, the first output end is respectively connected to the input end of the first digital-to-analog converter and the first input end of the third adder, the output end of the first digital-to-analog converter is connected to the second input end of the first adder, and the second output end of the discrete time loop filter is connected to the second input end of the third adder;

The second-stage loop includes a second adder, a continuous-time loop filter, a second sample holder, a second quantizer, and a second digital-to-analog converter, the output end of the third adder is connected to the first input end of the second adder, the output end of the second adder is connected to the input end of the continuous-time loop filter, the output end of the continuous-time loop filter is connected to the input end of the second sample holder, the output end of the second sample holder is connected to the input end of the second quantizer, the second quantizer has two output ends, the first output end is connected to the input end of the second digital-to-analog converter, and the output end of the second digital-to-analog converter is connected to the second input end of the second adder;

The digital filter comprises an N-fold upsampler, a first-stage digital filter, a second-stage digital filter and a fourth adder, wherein the input end of the N-fold upsampler is connected to the second input end of the first quantizer, the output end of the N-fold upsampler is connected to the first input end of the fourth adder via the first-stage digital filter, the input end of the second-stage digital filter is connected to the second output end of the second quantizer, the output end of the second-stage digital filter is connected to the second input end of the fourth adder, and the output end of the fourth adder is the output end of the modulator;

The signal transfer function of the first-stage loop is STF _1a (z), and the noise transfer function is NTF _1a (z); the signal transfer function of the second-stage loop is STF _2a (z), and the noise transfer function is NTF _2a (z); wherein the quantization noise of the first-stage loop is E ₁ , and the quantization noise of the second-stage loop is E ₂ , and the quantization noise E ₁ of the first-stage loop is used as the input signal of the second-stage loop;

The transfer function of the first-stage digital filter of the digital filter is H ₁ (z), and the transfer function of the second-stage digital filter is H ₂ (z); the output Y _MASH of the fourth adder is the output of the MASH ΔΣ modulator.

The first-stage loop operates at a frequency of F _S1 , and the second-stage loop operates at a frequency of F _S2 =N·F _S1 , wherein N is a constant greater than 1, and can generally be an integer, especially a power of 2, which is easier to implement.

The transfer function of the first-stage digital filter is H ₁ (z)=STF _2a (z), and the transfer function of the second-stage digital filter is H ₂ (z)=NTF _1a (z ^N ).

The noise transfer function of the first-stage loop is _L1 represents the order of the first-stage loop. The signal transfer function of the second-stage loop is STF _2a (z) = 1. Then the transfer function of the first-stage digital filter is _H1 (z) = 1. The transfer function of the second-stage digital filter is Or the signal transfer function of the second-level loop/> _L2 represents the order of the second-stage loop, then the first-stage digital filter transfer function is The transfer function of the second-stage digital filter is still / >

Example

It operates at sampling frequency F _S1 , while the second-stage loop adopts a continuous-time ΔΣ modulator and operates at clock frequency F _S2 =N·F _S1 (N>1).

The original analog signal is first input to the first-stage loop, and after passing through the sample-and-hold device 1, it is processed by the first-stage discrete-time loop filter, and then transmitted to the first quantizer 1 for quantization, and becomes a digital signal, generating the first-stage digital output Y ₁ . At the same time, the output signal Y ₁ is converted into an analog signal through the first digital-to-analog converter 1, and then fed back to the input end with the help of the adder 1. In addition, the signal after passing through the first digital-to-analog converter 1 and the signal at the front end of the first quantizer 1 are added by the adder 3 to generate the first-stage quantization error E ₁ .

The first-stage quantization error directly becomes the input signal of the second-stage continuous-time loop. In the architecture proposed by the present invention, since the second stage is a continuous-time loop, the sampling behavior of the signal is realized by the subsequent sample-and-hold module, so there is no need for an upsampler between the first-stage loop and the second-stage loop, which reduces the hardware area and power consumption of the system.

The signal input from the first stage to the second stage is processed by the continuous time loop filter and then passes through the second sample holder 2. The module operates at _FS2 = N· _FS1 , which can give full play to the advantage of the fast speed of the continuous time ΔΣ modulator. Finally, the signal passes through the second quantizer 2 to generate the second stage digital output signal _Y2 . Similar to the first stage, the output signal _Y2 is converted into an analog signal by the second digital-to-analog converter 2 and then fed back to the input end with the help of the adder 2.

Next, the digital signal output from the first stage and the digital signal output from the second stage are sent to the designated digital filter for processing. The digital signal _Y1 output from the first stage is first passed through the upsampler and then input to the first stage digital filter _H1 , and the digital signal _Y2 output from the second stage is directly input to the second stage digital filter _H2 , and finally these two signals are passed through the fourth adder 4 to generate the final system output. By selecting a specific digital filter, the first stage quantization error in the final output is eliminated, thereby achieving the effect of reducing the system quantization error and improving the resolution.

Define STF _1a (z) and NTF _1a (z) as the signal transfer function and noise transfer function in the first-level loop, respectively. STF _2a (z) and NTF _2a (z) are the signal transfer function and noise transfer function in the second-level loop, respectively. The subscript “a” indicates the realization of the corresponding transfer function in the analog domain.

Furthermore, the digital outputs _Y1 and _Y2 of the two-stage loop can be expressed as:

Y ₁ =STF _1a (z)X+NTF _1a (z)E ₁ (1)

Y ₂ =STF _2a (z)E ₁ +NTF _2a (z)E ₂ (2)

The digital signal _Y1 output by the first stage first passes through the upsampler and then is input into the first stage digital filter. The digital signal _Y2 output by the second stage is directly input into the second stage digital filter. The transfer functions of the first stage digital filter and the second stage digital filter are set to _H1 (z)= _STF2d (z), _H2 (z)= _NTF1d (z), respectively. The subscript "d" indicates the realization of the corresponding transfer function in the digital domain.

Furthermore, the output signal of the digital filter generates the final system output Y _MASH through the fourth adder 4:

Among them, the noise leakage term is:

Under the conditions NTF _1a (z ^N ) = NTF _1d (z), STF _2a (z) = STF _2d (z), the first-level quantization error E ₁ in the final output is eliminated, the noise leakage term becomes zero, and the final output is:

Y _MASH = STF _1a (z ^N ) STF _2d (z) X + NTF _2a (z) NTF _1d (z) E ₂ (5)

In this embodiment, the noise transfer function of the first-stage loop is _L1 represents the order of the first-stage loop. The signal transfer function of the second-stage loop is STF _2a (z) = 1. Then the first-stage digital filter transfer function is _H1 (z) = 1. The second-stage digital filter transfer function is Or the signal transfer function of the second-level loop _L2 represents the order of the second-stage loop, then the first-stage digital filter transfer function is The transfer function of the second-stage digital filter is still / > The first-stage quantization error E ₁ can be eliminated by setting the digital filter according to the above conditions.

In actual circuit implementation, the digital domain filter functions NTF _1d (z) and STF _2d (z) in equation (4) can be accurately implemented, while the analog domain transfer functions NTF _1a (z) and STF _2a (z) will be affected by PVT changes, which makes NTF _1a (z ^N ) ≠ NTF _1d (z), STF _2a (z) ≠ STF _2d (z), that is, E ₁ cannot be completely eliminated and noise leakage occurs. In addition, NTF _1d (z) in equation (4) has a noise shaping effect, which can shape and suppress the noise leakage generated by the inaccurate analog domain transfer function STF _2a (z), while STF _2d (z) is a signal transfer function, and its gain is approximately unity gain. The noise leakage generated by NTF _1a (z ^N ) with PVT changes will not be suppressed. Therefore, it is particularly important to ensure the accuracy of the noise transfer function NTF _1a (z) in the first-stage loop. The first stage of the structure of the present invention adopts a discrete time loop filter with low sensitivity to PVT, so a more accurate NTF _1a (z) can be obtained, which can greatly alleviate the noise leakage problem caused by the mismatch between the analog and digital filters in the MASH architecture ΔΣ modulator. Although the first stage of the traditional DT MASH also adopts a discrete time loop to alleviate the noise leakage problem, the performance of this structure under high-frequency clock is poor, so the OSR that can be achieved is limited. The present invention adopts a continuous time loop with high-speed performance in the second stage loop, so that the system has a higher equivalent OSR.

In summary, the low-noise-leakage MASHΔΣ modulator of the present invention can have a higher OSR while alleviating the noise leakage problem, thereby greatly increasing the system accuracy of this type of modulator.

The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (4)

1. A low noise leakage MASH delta sigma modulator comprising a two-stage cascaded first stage loop, second stage loop and digital filter, characterized by:

The first-stage loop comprises a first sampling holder, a first adder, a discrete time loop filter, a first quantizer, a first digital-to-analog converter and a third adder, wherein the output end of the first sampling holder is connected with the first input end of the first adder, the output end of the first adder is connected with the input end of the discrete time loop filter, the discrete time loop filter is provided with a first output end and a second output end, the first output end of the discrete time loop filter is connected with the input end of the first quantizer, the first quantizer is provided with two output ends, the first output end is respectively connected with the input end of the first digital-to-analog converter and the first input end of the third adder, the output end of the first digital-to-analog converter is connected with the second input end of the first adder, and the second output end of the discrete time loop filter is connected with the second input end of the third adder;

The second-stage loop comprises a second adder, a continuous time loop filter, a second sampling holder, a second quantizer and a second digital-to-analog converter, wherein the output end of the third adder is connected with the first input end of the second adder, the output end of the second adder is connected with the input end of the continuous time loop filter, the output end of the continuous time loop filter is connected with the input end of the second sampling holder, the output end of the second sampling holder is connected with the input end of the second quantizer, the second quantizer is provided with two output ends, the first output end of the second quantizer is connected with the input end of the second digital-to-analog converter, and the output end of the second digital-to-analog converter is connected with the second input end of the second adder;

The digital filter comprises an N-times up-sampler, a first-stage digital filter, a second-stage digital filter and a fourth adder, wherein the input end of the N-times up-sampler is connected with the second input end of the first quantizer, the output end of the N-times up-sampler is connected with the first input end of the fourth adder through the first-stage digital filter, the input end of the second-stage digital filter is connected with the second output end of the second quantizer, the output end of the second-stage digital filter is connected with the second input end of the fourth adder, and the output end of the fourth adder is the output end of the modulator;

the signal transfer function of the first-stage loop is STF _1a (z), and the noise transfer function is NTF _1a (z); the signal transfer function of the second-stage loop is STF _2a (z), and the noise transfer function is NTF _2a (z); wherein the quantization noise of the first stage loop is E ₁,

The quantization noise of the second-stage loop is E ₂, and the quantization noise E ₁ of the first-stage loop is used as an input signal of the second-stage loop;

The transfer function of the first stage digital filter of the digital filter is H ₁ (z), and the transfer function of the second stage digital filter is H ₂ (z); the output Y _MASH of the fourth adder is the output of the present MASH delta sigma modulator.

2. The low noise leakage MASH delta sigma modulator of claim 1, wherein said first stage loop operates at frequency F _S1 and said second stage loop operates at frequency F _S2＝N·F_S1, wherein N is a constant greater than 1.

3. The low noise leakage MASH delta sigma modulator of claim 1, wherein the transfer function of the first stage digital filter H ₁(z)＝STF_2a (z), the transfer function of the second stage digital filter H ₂(z)＝NTF_1a(z^N).

4. The low noise leakage MASH delta sigma modulator of claim 1, wherein the noise transfer function of the first stage loopL ₁ represents the order of the first-stage loop, the signal transfer function STF _2a (z) =1 of the second-stage loop, the transfer function H ₁ (z) =1 of the first-stage digital filter, and the second-stage digital filter transfer functionOr the signal transfer function/>, of the second-stage loopL ₂ represents the order of the second-stage loop, the first-stage digital filter transfer function/>The transfer function of the second digital filter is still