CN114900189A - MASH delta-sigma modulator with low noise leakage - Google Patents
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Abstract
A low-noise leakage MASH delta sigma modulator comprises a first-stage loop, a second-stage loop and a digital filter which are cascaded in two stages, wherein the first-stage loop adopts a discrete time structure, the second-stage loop adopts a continuous time structure which runs at a higher clock frequency, and the back-end digital filter is matched according to a signal transfer function and a noise transfer function in the two loops: noise transfer function of first stage loop
L 1 Representing the order of the first-stage loop, the signal transfer function STF of the second-stage loop 2a (z) 1, the first stage digital filter transfer function H 1 (z) 1, second stage digital filter transfer function
Or signal transfer function of second-stage loop
L 2 Representing the order of the second stage loop, the first stage digital filter transfer function
The second stage digital filter has a transfer function of
The first-stage quantization error E can be eliminated by setting the digital filter according to the above conditions 1 . Low sensitivity to noise leakage; meanwhile, the equivalent OSR of the system is effectively improved, so that the capability of the system for inhibiting quantization noise is enhanced.
Description
Technical Field
The present invention relates to mixed signal integrated circuits, and more particularly to a MASH delta sigma modulator with low noise leakage.
Background
With the continuous progress of digital audio technology, there are more and more products with analog-to-digital converter (ADC) chips, and at the same time, the requirements for ADCs are higher and higher. The ADC for audio codec, which is generally common, requires at least 13 bits of conversion accuracy, and is mostly an oversampling ADC. As an important component in an oversampling ADC, a Delta Sigma Modulator (DSM) can make a system achieve high conversion accuracy, and simultaneously avoid the requirement for high matching accuracy of circuit devices, and the requirement for an anti-aliasing filter is not high, so that the ADC is widely used in the field of audio processing.
Delta sigma modulators typically employ noise shaping techniques and oversampling techniques to reduce in-band noise of the audio signal and improve conversion accuracy. The effect of noise shaping is positively correlated to the order of the system, but considering that a high-order system is a nonlinear feedback system, the use of a system above the second order to achieve noise shaping causes serious instability problems. The delta sigma modulator with a multi-stage noise shaping (MASH) structure can ensure high-quality noise shaping and has good stability, and the phenomenon of stray string sounds can be greatly reduced. However, the performance of such a structure is greatly reduced due to noise leakage caused by mismatch between the analog circuit and the digital filter.
Document [1] (see m.sanchez-Renedo, s.paton and l.hernandez, "A2-2 Discrete Time captured Σ Δ Modulator with NTF Zero Using inter stage Feedback," 200613 th IEEE International reference on Electronics, Circuits and Systems, 2006, pp.954-957.) employs a Discrete Time (DT) MASH architecture, whose first order quantization error is easier to extract, and whose Discrete Time integrator has low sensitivity to process-voltage-temperature (PVT) variations, and therefore has a low noise leakage impact. However, the sampling rate of this architecture is limited by the discrete time integrator, and thus the Over Sampling Rate (OSR) is limited. To further increase the oversampling rate, the document [2] (see L.Qi, S.sin, S.U, F.Maloberti and R.P.Martins, "A4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multi-rate operation Sharing," in IEEE Transactions on Circuits and Systems I: regulated Papers, vol.64, No.10, pp.2641-2654, Oct.2017.) employs a multi-rate DT MASH architecture. However, the multi-rate DT MASH architecture requires the addition of a capacitor array based up-sampler between the two stages, increasing power consumption and area requirements. Document [3] (see a. edward et al, "a 43-mW MASH 2-2 CT Σ Δ Modulator addressing 74.4/75.8/76.8dB of SNDR/SNR/DR and 50MHz of BW in 40-nm CMOS," in IEEE Journal of Solid-State Circuits, vol.52, No.2, pp.448-459, feb.2017.) a continuous-time (CT) MASH structure can achieve higher sampling rates, but the structure employs a continuous-time type integrator whose coefficients are very sensitive to PVT variations, and thus the noise leakage is severe, limiting the final effective accuracy. In addition, in the CT MASH architecture, it is difficult to accurately extract the quantization error of the first stage due to the propagation delay of the quantizer module.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: in order to overcome the problems of high sensitivity of a traditional CT MASH structure to noise leakage and limited speed of a traditional DTMMASH, a MASH delta sigma modulator with low noise leakage is provided.
The technical solution of the invention is as follows:
a low-noise leakage MASH delta sigma modulator comprises a first-stage loop, a second-stage loop and a digital filter which are cascaded in two stages, and is characterized in that:
the first-stage loop comprises a first sample holder, a first adder, a discrete-time loop filter, a first quantizer, a first digital-to-analog converter and a third adder, wherein an output end of the first sample holder is connected with a first input end of the first adder, an output end of the first adder is connected with an input end of the discrete-time loop filter, the discrete-time loop filter is provided with a first output end and a second output end, a first output end of the discrete-time loop filter is connected with an input end of the first quantizer, the first quantizer is provided with two output ends, the first output ends are respectively connected with an input end of the first digital-to-analog converter and a first input end of the third adder, an output end of the first digital-to-analog converter is connected with a second input end of the first adder, and a second output end of the discrete-time loop filter is connected with a second input end of the third adder Connecting;
said second stage loop comprises a second adder, a continuous time loop filter, a second sample and hold device, a second quantizer and a second digital to analog converter, the output of said third adder being connected to the first input of said second adder, the output of said second adder being connected to the input of said continuous time loop filter, the output of said continuous time loop filter being connected to the input of said second sample and hold device, the output of said second sample and hold device being connected to the input of said second quantizer, the second quantizer having two outputs, the first output being connected to the input of said second digital to analog converter, the output of said second digital to analog converter being connected to the second input of said second adder;
the digital filter comprises an N times up-sampler, a first stage digital filter, a second stage digital filter and a fourth adder, wherein the input end of the N times up-sampler is connected with the second input end of the first quantizer, the output end of the N times up-sampler is connected with the first input end of the fourth adder through the first stage digital filter, the input end of the second stage digital filter is connected with the second output end of the second quantizer, the output end of the second stage digital filter is connected with the second input end of the fourth adder, and the output end of the fourth adder is the output end of the modulator;
the first stage loop has a signal transfer function of STF 1a (z) noise transfer function NTF 1a (z); the signal transfer function of the second stage loop is STF 2a (z) noise transfer function NTF 2a (z); wherein the quantization noise of the first stage loop is E 1 The quantization noise of the second-stage loop is E2, and the quantization noise of the first-stage loop is E 1 As an input signal to the second stage loop;
the first stage of the digital filter has a transfer function of H 1 (z) the transfer function of the second stage digital filter is H 2 (z); output Y of the fourth adder MASH Which is the output of the MASH delta sigma modulator.
The first stage loop at frequency F s1 Operating with said second stage loop at a frequency F s2 ＝N·F s1 Work, where N is a constant greater than 1, can generally be taken as an integer, especially a power of 2, is easier to implement.
Transfer function H of the first stage digital filter 1 (z)＝STF 2a (z), transfer function H of the second stage digital filter 2 (z)＝NTF 1a (z N )。
Noise transfer function of the first stage loop
L 1 Representing the order of the first-stage loop, the signal transfer function STF of the second-stage loop 2a (z) 1, then the transfer function H of the first stage digital filter 1 (z) 1, second stage digital filter transfer function
Or signal transfer function of second-stage loop
L 2 Representing the order of the second stage loop, the first stage digital filter transfer function
The second stage digital filter has a transfer function of
Compared with the prior art, the invention has the beneficial effects that:
1) according to the MASH delta sigma modulator with low noise leakage, a first-stage loop adopts a discrete time structure, a second-stage loop adopts a continuous time structure running at a higher clock frequency, and a rear-end digital filter is matched according to a signal transfer function and a noise transfer function in the two loops so as to eliminate quantization noise of the first stage. The MASH delta sigma modulator with low noise leakage has low noise leakage sensitivity; meanwhile, the equivalent OSR of the system is effectively improved, so that the capability of the system for inhibiting quantization noise is enhanced.
2) Compared with the traditional multi-rate DT MASH structure, the structure does not need an additional up-sampler before the second stage, thereby reducing the complexity of the circuit, and reducing the hardware expense and the system power consumption.
3) Compared with the traditional single-rate CT MASH structure, the invention greatly reduces the sensitivity to the change of the integrator coefficient.
Drawings
Fig. 1 is a schematic diagram of the structure of a conventional MASH Δ Σ modulator.
Fig. 2 is a schematic diagram of the structure of a multi-rate DT MASH delta sigma modulator.
Fig. 3 is a schematic diagram of the structure of the MASH delta sigma modulator with low noise leakage according to the present invention.
FIG. 4 is a power noise density spectrum of an embodiment of the present invention applied to a 2-2MASH structure.
FIG. 5 is a graph of signal-to-quantization noise ratio (SQNR) as a function of continuous-time integrator coefficients for a 2-2MASH structure and a conventional single-rate 2-2 CT MASH structure, according to embodiments of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are described in detail and completely with reference to the diagrams in the embodiments of the present invention, and the embodiments described below are only a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
In the structural schematic diagram of the conventional MASH Δ Σ modulator shown in fig. 1, two independent low-order loop Δ Σ modulators are connected to implement a high-order noise shaping function and avoid instability problems in the loop structure. At the digital back end, the two digital outputs are combined by cascading corresponding digital filters to produce the final output.
A schematic diagram of the multi-rate DT MASH delta sigma modulator structure is shown in fig. 2. In this structure, because the second stage is a discrete time loop, an up-sampler based on a capacitor array is needed at the sampling front end of the second stage, and the multi-rate operation can be realized only by sampling the quantization error of the first stage and then keeping the sampling state in the next several clock cycles.
Referring to fig. 3, fig. 3 is a schematic diagram of a MASH Δ Σ modulator according to the present invention, and it can be seen from the diagram that the MASH Δ Σ modulator with low noise leakage according to the present invention includes a first stage loop, a second stage loop and a digital filter, which are cascaded in two stages, and is characterized in that:
the first-stage loop comprises a first sample holder, a first adder, a discrete-time loop filter, a first quantizer, a first digital-to-analog converter and a third adder, wherein an output end of the first sample holder is connected with a first input end of the first adder, an output end of the first adder is connected with an input end of the discrete-time loop filter, the discrete-time loop filter is provided with a first output end and a second output end, a first output end of the discrete-time loop filter is connected with an input end of the first quantizer, the first quantizer is provided with two output ends, the first output ends are respectively connected with an input end of the first digital-to-analog converter and a first input end of the third adder, an output end of the first digital-to-analog converter is connected with a second input end of the first adder, and a second output end of the discrete-time loop filter is connected with a second input end of the third adder Connecting;
said second stage loop comprises a second adder, a continuous time loop filter, a second sample and hold device, a second quantizer and a second digital to analog converter, the output of said third adder being connected to the first input of said second adder, the output of said second adder being connected to the input of said continuous time loop filter, the output of said continuous time loop filter being connected to the input of said second sample and hold device, the output of said second sample and hold device being connected to the input of said second quantizer, the second quantizer having two outputs, the first output being connected to the input of said second digital to analog converter, the output of said second digital to analog converter being connected to the second input of said second adder;
the digital filter comprises an N times up-sampler, a first stage digital filter, a second stage digital filter and a fourth adder, wherein the input end of the N times up-sampler is connected with the second input end of the first quantizer, the output end of the N times up-sampler is connected with the first input end of the fourth adder through the first stage digital filter, the input end of the second stage digital filter is connected with the second output end of the second quantizer, the output end of the second stage digital filter is connected with the second input end of the fourth adder, and the output end of the fourth adder is the output end of the modulator;
the first stage loop has a signal transfer function of STF 1a (z) noise transfer function NTF 1a (z); the signal transfer function of the second stage loop is STF 2a (z) noise transfer function NTF 2a (z); wherein the quantization noise of the first stage loop is E 1 Quantization noise of the second stage loop is E 2 First stage loopQuantization noise E of 1 As an input signal to the second stage loop;
the transfer function of the first stage digital filter of the digital filter is H 1 (z) the transfer function of the second stage digital filter is H 2 (z); output Y of the fourth adder MASH Which is the output of the MASH delta sigma modulator.
Said first loop being at frequency F S1 Operating with said second stage loop at a frequency F S2 ＝N·F S1 Work, where N is a constant greater than 1, can generally be taken as an integer, especially a power of 2, is easier to implement.
The transfer function H of the first stage digital filter 1 (z)＝STF 2a (z), transfer function H of the second stage digital filter 2 (z)＝NTF 1a (z N )。
Noise transfer function of the first stage loop
L 1 Representing the order of the first stage loop, the signal transfer function STF of the second stage loop 2a (z) 1, then the transfer function H of the first stage digital filter 1 (z) 1, second stage digital filter transfer function
Or signal transfer function of second-stage loop
L 2 Representing the order of the second stage loop, the first stage digital filter transfer function
The second stage digital filter has a transfer function of
Examples
At a sampling frequency F S1 In the working process, the operation is carried out,while the second stage loop employs a continuous time delta sigma modulator at a clock frequency F S2 ＝N·F S1 (N > 1) operation.
The original analog signal is firstly input into the first stage loop, processed by the first stage discrete time loop filter after passing through the sample holder 1, and then transmitted to the first quantizer 1 for quantization to become a digital signal, and a first stage digital output Y is generated 1 . At the same time, output signal Y 1 Is converted into an analog signal by the first digital-to-analog converter 1 and is then fed back to the input by means of the adder 1. In addition, the signal after passing through the first DAC 1 and the signal at the front end of the first quantizer 1 are used by the adder 3 to generate the first-stage quantization error E 1 。
The first stage quantization error becomes directly the input signal to the second stage continuous-time loop. In the framework provided by the invention, as the second stage is a continuous time loop and the sampling action of the signal is realized by the following sample and hold module, an up-sampler is not needed between the first stage loop and the second stage loop, thus reducing the hardware area and power consumption of the system.
The signal input to the second stage from the first stage is processed by a continuous time loop filter and passed through a second sample and hold block 2, which is fed by F S2 ＝N·F S1 The operation can give full play to the advantage of high speed of the continuous time delta sigma modulator, and finally the signal passes through the second quantizer 2 to generate a second-stage digital output signal Y 2 . Similar to the first stage, the output signal Y 2 Becomes an analog signal through the second digital-to-analog converter 2 and is then fed back to the input by means of the adder 2.
And then, the digital signal output by the first stage and the digital signal output by the second stage are sent to a designated digital filter for processing. Digital signal Y output by the first stage 1 First goes through up-sampler and then is input to the first stage digital filter H 1 The digital signal Y2 output by the second stage is directly input to a digital filter H of the second stage 2 Finally, the two signals pass through a fourth adder 4 to generate a final system output, and a specific digital filter is selected to eliminate the quantization error of the first stage in the final outputAnd the effect of reducing the system quantization error and improving the resolution is realized.
Definition of STF 1a (z) and NTF 1a (z) Signal transfer function and noise transfer function in the first stage Loop, STF 2a (z) and NTF 2a (z) are the signal transfer function and the noise transfer function in the second stage loop, respectively, and the subscript "a" indicates the implementation of the respective transfer functions in the analog domain.
Further, the digital output Y of the two-stage loop 1 And Y 2 Can be respectively expressed as:
Y 1 ＝STF 1a (z)X+NTF 1a (z)E 1 (1)
Y 2 ＝STF 2a (z)E 1 +NTF 2a (z)E 2 (2)
digital signal Y output from the first stage 1 The digital signal Y is input to the first stage digital filter after passing through the up-sampler, and the digital signal Y is output from the second stage 2 Directly inputting the input signal to a second stage digital filter, and setting the transfer functions of the first stage digital filter and the second stage digital filter to be respectively H 1 (z)＝STF 2d (z)，H 2 (z)NTF 1d (z), the subscript "d" indicates the implementation of the corresponding transfer function in the digital domain.
Further, the output signal of the digital filter is passed through a fourth adder 4 to produce a final system output Y MASH ：
Wherein the noise leakage term is:
under the condition of NTF 1a (z N )＝NTF 1d (z)，STF 2a (z)＝STF 2d (z) first stage quantization error E in the final output 1 Eliminating, noise leakage term becoming zero, at mostThe final output is:
Y MASH ＝STF 1a (z N )STF 2d (z)X+NTF 2a (z)NTF 1d (z)E 2 (5)
in this embodiment, the noise transfer function of the first-stage loop
L 1 Representing the order of the first-stage loop, the signal transfer function STF of the second-stage loop 2a (z) 1, then the first stage digital filter transfer function H 1 (z) 1, second stage digital filter transfer function
Or signal transfer function of second-stage loop
L 2 Representing the order of the second stage loop, the first stage digital filter transfer function
The second stage digital filter has a transfer function of
The first-stage quantization error E can be eliminated by setting the digital filter according to the above conditions 1 。
In practical circuit implementation, the filter function NTF of digital domain in equation (4) 1d (z) and STF 2d (z) can be realized accurately, and transfer function NTF of analog domain 1a (z) and STF 2a (z) is affected by PVT variations, which makes NTF 1a (z N )≠NTF 1d (z)，STF 2a (z)≠STF 2d (z), i.e. E 1 Cannot be completely eliminated to generate noise leakage. Further, NTF in the formula (4) 1d (z) has noise shaping effect, and can be used for inaccurate simulation domain transfer function STF 2a (z) the resulting noise leakage is shaped and suppressed, and STF 2d (z) is a signalTransfer function with gain approximated as unity gain, NTF 1a (z N ) Noise leakage with PVT variation is not suppressed, thus ensuring noise transfer function NTF in the first stage loop 1a The accuracy of (z) is particularly important. The first stage of the structure of the invention adopts a discrete time loop filter with low sensitivity to PVT, so that more accurate NTF can be obtained 1a (z), the noise leakage problem caused by mismatch of analog and digital filters in the MASH architecture delta sigma modulator can be greatly relieved. Although the first stage in the conventional DT MASH also employs a discrete time loop to alleviate the noise leakage problem, the structure has poor performance at high frequency clocks, and therefore the achievable OSR is limited. The invention adopts the continuous time loop with high-speed performance as the second-stage loop, so that the system has higher equivalent OSR.
In conclusion, the MASH delta sigma modulator with low noise leakage can have higher OSR while relieving the problem of noise leakage, and greatly improves the system precision of the modulator.
FIG. 4 depicts a fast Fourier transform spectrum for application of an embodiment of the present invention to a 2-2MASH structure. FIG. 5 reflects that the structure of the present invention applied to the 2-2MASH is much less sensitive to changes in the continuous-time integrator coefficient than a conventional single-rate 2-2 continuous-time MASH Δ ∑ modulator.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (4)
1. A MASH delta sigma modulator with low noise leakage comprises a first-stage loop, a second-stage loop and a digital filter which are cascaded in two stages, and is characterized in that:
the first-stage loop comprises a first sample holder, a first adder, a discrete-time loop filter, a first quantizer, a first digital-to-analog converter and a third adder, wherein an output end of the first sample holder is connected with a first input end of the first adder, an output end of the first adder is connected with an input end of the discrete-time loop filter, the discrete-time loop filter is provided with a first output end and a second output end, a first output end of the discrete-time loop filter is connected with an input end of the first quantizer, the first quantizer is provided with two output ends, the first output ends are respectively connected with an input end of the first digital-to-analog converter and a first input end of the third adder, an output end of the first digital-to-analog converter is connected with a second input end of the first adder, and a second output end of the discrete-time loop filter is connected with a second input end of the third adder Connecting;
said second stage loop comprises a second adder, a continuous-time loop filter, a second sample-and-hold device, a second quantizer and a second digital-to-analog converter, the output of said third adder being connected to the first input of said second adder, the output of said second adder being connected to the input of said continuous-time loop filter, the output of said continuous-time loop filter being connected to the input of said second sample-and-hold device, the output of said second sample-and-hold device being connected to the input of said second quantizer, the second quantizer having two outputs, the first output being connected to the input of said second digital-to-analog converter, the output of said second digital-to-analog converter being connected to the second input of said second adder;
the digital filter comprises an N times up-sampler, a first stage digital filter, a second stage digital filter and a fourth adder, wherein the input end of the N times up-sampler is connected with the second input end of the first quantizer, the output end of the N times up-sampler is connected with the first input end of the fourth adder through the first stage digital filter, the input end of the second stage digital filter is connected with the second output end of the second quantizer, the output end of the second stage digital filter is connected with the second input end of the fourth adder, and the output end of the fourth adder is the output end of the modulator;
the first stage loop has a signal transfer function of STF 1a (z) a noise transfer function of NIF 1a (z); the signal transfer function of the second stage loop is STF 2a (z) noise transfer function NTF 2a (z); wherein the quantization noise of the first stage loop is E 1 Quantization noise of the second stage loop is E 2 Quantization noise E of the first-stage loop 1 As an input signal to the second stage loop;
the first stage of the digital filter has a transfer function of H 1 (z) the transfer function of the second stage digital filter is H 2 (z); output Y of the fourth adder MASH Which is the output of the MASH delta sigma modulator.
2. The low noise leakage MASH Δ Σ modulator of claim 1, where the first stage loop is at frequency F S1 Operating with said second stage loop at a frequency F S2 ＝N·F S1 Work, where N is a constant greater than 1, can generally be taken as an integer, especially a power of 2, is easier to implement.
3. The low noise leakage MASH delta sigma modulator according to claim 1, characterized in that the transfer function H of the first stage digital filter 1 (z)＝STF 2a (z), transfer function H of the second stage digital filter 2 (z)＝NTF 1a (z N )。
4. The MASH Δ Σ modulator of claim 1, where the noise transfer function of the first stage loop is the noise transfer function of the first stage loop
L 1 Representing the order of the first-stage loop, the signal transfer function STF of the second-stage loop 2a (z) 1, then the transfer function H of the first stage digital filter 1 (z) 1, second order numberTransfer function of filter
Or signal transfer function of second-stage loop
L 2 Representing the order of the second stage loop, the first stage digital filter transfer function
The second stage digital filter transfer function is still
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