CN118100945A - Sigma-Delta modulator circuit with chopper - Google Patents
Sigma-Delta modulator circuit with chopper Download PDFInfo
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- CN118100945A CN118100945A CN202410076454.0A CN202410076454A CN118100945A CN 118100945 A CN118100945 A CN 118100945A CN 202410076454 A CN202410076454 A CN 202410076454A CN 118100945 A CN118100945 A CN 118100945A
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- integrator
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- chopper
- quantizer
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- 239000003990 capacitor Substances 0.000 claims description 14
- 238000005070 sampling Methods 0.000 claims description 10
- 101100462365 Aspergillus niger (strain CBS 513.88 / FGSC A1513) otaA gene Proteins 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
- H03M3/326—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors
- H03M3/338—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors by permutation in the time domain, e.g. dynamic element matching
- H03M3/34—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors by permutation in the time domain, e.g. dynamic element matching by chopping
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/32—Delta-sigma modulation with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The invention relates to a Sigma-Delta modulator circuit with chopper. The modulator circuit comprises three cascaded integrators, a chopper circuit, a quantizer and a feedback digital module. The integrator comprises a chopper circuit; the three integrators are sequentially connected with the quantizer in sequence; the system input has 4 paths connected to the inputs of the three integrators and the quantizer, respectively; the outputs of the integrator (11) and the integrator (12) are respectively provided with a feed-forward circuit connected to the quantizer; the output of the quantizer is the system output and is connected to an integrator (11) through a feedback DAC; the output of the integrator (13) has an additional feedback path connected to the input of the integrator (12). The invention has the advantages of simple structure, effective reduction of low-frequency noise by chopping technology, difficult overload of integrator output at each stage, high precision, lower power consumption and the like.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a Sigma-Delta modulator circuit with chopper.
Background
With the development of digital signal processing technology, more and more systems use digital signals as media of a control system, so that a module for converting analog signals into digital signals is required, and an analog-to-digital signal converter (ADC) becomes an important link in modern signal processing systems. The ADC is used as a conversion module for analog and digital signals, and its speed and accuracy determine and limit the speed and accuracy of the digital control system, and determine the final signal processing result.
Sigma-Delta ADC is widely applied to occasions with higher requirements on precision, such as precise medical instruments, sensors, high-quality audio, and the like. The method uses the over-sampling and noise shaping technology, so that the ADC is insensitive to circuit mismatch, and meanwhile, the precision is higher, and the high requirement of precision equipment on the precision can be met.
The Sigma-Delta modulator forms the core of the ADC. The modulator superimposes and integrates the input signal with the feedback signal through each stage integrator, the output of each stage being part of the input of the next stage. In the modulator, the quantization noise of the integrator is gradually reduced by the processing of the former integrator, so the first integrator is particularly sensitive to low frequency noise. Since a modulator employing low-pass filtering cannot filter out low-frequency noise, the shaping effect of the first-stage integrator on low-frequency noise depends largely on the over-sampling rate (OSR), increasing the OSR can significantly increase the power consumption of the system, while increasing the difficulty of circuit design. There is a need for a way to reduce the sensitivity of the first stage integrator to low frequency noise without significantly increasing the power consumption, thereby increasing the overall signal-to-noise ratio (SNR) of the modulator.
Disclosure of Invention
The embodiments described herein provide Sigma-delta modulator circuits. The invention has the advantages of simple structure, effective reduction of low-frequency noise by chopping technology, difficult overload of integrator output at each level, high precision, lower power consumption and the like.
The technical scheme is as follows:
A Sigma-Delta modulator circuit with chopping, comprising the following modules:
the integrator 11, the integrator 12 and the integrator 13 are three integrators, the integrator 11, the integrator 12 and the integrator 13 are sequentially connected step by step in sequence,
The system inputs are connected to the inputs of integrator 11, integrator 12, integrator 13 and quantizer 14 respectively,
The outputs of integrator 11 and integrator 12 each have a feed-forward path connected to quantizer 14, and the output of integrator 13 has an additional feedback path connected to the input of integrator 12;
A quantizer 14, whose input end is connected to the integrator 11, the integrator 12 feed-forward path, and the integrator 13, for quantizing the output results of the three and outputting a digital signal;
A feedback DAC 15, the input of which is connected to the system output of the quantizer 14, for feeding back a digital signal to the input of the integrator 11.
In the preferred embodiment, the integrator 11, the integrator 12 and the integrator 13 comprise operational amplifiers, and the high gain operational amplifiers form the core of the integrator.
In the preferred embodiment, the integrator 11 further includes a chopper circuit for reducing low frequency noise and improving the performance of the modulator.
In the preferred embodiment, the quantizer 14 is comprised of a comparator and a latch.
In the preferred embodiment, the feedback DAC 15 feeds back a digital output signal to the input of the integrator 11 for providing the feedback signal necessary for the modulator.
The circuit module for realizing the Sigma-Delta modulator adopts a full feedforward structure, and each level of integrator is not easy to overload, has a simple structure and lower power consumption, and can keep higher precision. The chopper circuit included in the integrator 11 effectively suppresses low-frequency noise by simple switching control, has a simple structure, can improve the overall performance of the modulator, and does not need to improve the OSR, and has low power consumption.
Drawings
FIG. 1 is a schematic block diagram of a Sigma-Delta modulator circuit 10 according to an embodiment of the present disclosure;
fig. 2 is an exemplary circuit diagram of the integrator 11 of fig. 1;
Fig. 3 is a power spectral density plot of the output signal of Sigma-Delta modulator circuit 10 in accordance with an embodiment of the present disclosure.
Elements in the figures are illustrated schematically and not drawn to scale.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the attached drawings, so that the objects, features and advantages of the present invention will be more clearly understood. It should be understood that the embodiments shown in the drawings are not intended to limit the scope of the invention, but rather are merely illustrative of the true spirit of the invention.
In the following description, for the purposes of explanation of various disclosed embodiments, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. One skilled in the relevant art will recognize, however, that an embodiment may be practiced without one or more of the specific details. In other instances, well-known devices, structures, and techniques associated with the present application may not be shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.
Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
In the following description, for the purposes of clarity of presentation of the structure and manner of operation of the present invention, the description will be made with the aid of directional terms, but such terms as "forward," "rearward," "left," "right," "outward," "inner," "outward," "inward," "upper," "lower," etc. are to be construed as convenience, and are not to be limiting.
Please refer to fig. 1. Fig. 1 is a schematic block diagram of a Sigma-Delta modulator 10 with chopper according to an embodiment of the present disclosure, mainly including an integrator 11, an integrator 12, an integrator 13, a quantizer 14, a feedback DAC module 15, an integrator feedforward coefficient module 16, an input coefficient module 17, a feedback DAC coefficient module 18, and an integrator feedback coefficient module 19. The integrator 11, the integrator 12 and the integrator 13 are sequentially cascaded; three outputs of the integrator 11, the integrator 12 and the integrator 13 pass through a feedforward coefficient module 16, a system input passes through an input coefficient module 17, and the four outputs are summed to be used as inputs of the quantizer 14; the output of the quantizer 14 is the system output and is also the input to the feedback DAC module 15; the output of the feedback DAC module 15 is summed via a feedback DAC coefficient module 18 with the system input via the input coefficient module 17 as an input to the integrator 11; the system input is added to the integrator 13 via the input coefficient module 17; the output of integrator 13 is also fed into integrator 12 via integrator feedback coefficient block 19, together with the system input via input coefficient block 17.
The integrator feedforward coefficient block 16, the input coefficient block 17, the feedback DAC coefficient block 18, and the integrator feedback coefficient block 19 of fig. 1 are all carefully designed to ensure that their corresponding circuits meet the performance requirements required by the modulator circuit 10.
Please refer to fig. 2. Fig. 2 is an exemplary circuit diagram of the integrator 11 in fig. 1 described above. The integrator 11 includes 2 first switches 1111, 1112, and 4 second switches 1121, 1122, 1123, 1124, and a first operational amplifier OTA1, and 2 sampling capacitors 1141, 1142, and 2 integrating capacitors 1151, 1152, and chopper circuits 1131, 1132, wherein:
The left sides of the 2 first switches 1111 and 1112 are connected with the system input, the right sides are respectively connected with 2 sampling capacitors 1141 and 1142, the right sides of the sampling capacitors 1141 are connected with second switches 1121 and 1123, the right sides of the sampling capacitors 1142 are connected with second switches 1122 and 1124, the other ends of the second switches 1123 and 1124 are grounded, the other sides of the second switches 1121 and 1122 are respectively connected with chopper switches 1131 and 1132 and integrating capacitors 1151 and 1152, the other sides of the integrating capacitors 1151 and 1152 are respectively connected with the output of the integrator 11 and the chopper circuit 1132, the right side of the chopper circuit 1131 is connected with the input of the operational amplifier OTA1, and the left side of the chopper circuit 1132 is connected with the output of the operational amplifier OTA 1. The first switches 1111, 1112 and the second switches 1121, 1122, 1123, 1124 are controlled by two-phase non-overlapping clocks; chopper circuits 1131, 1132 are controlled by another set of clocks different from the previous set.
In addition, the structures of the integrator 12, the integrator 13, the quantizer 14, and the feedback DAC module 15 in fig. 1 are well known, and will not be described here.
Please refer to fig. 3. The amplitude of the input signal is 0.6 v, and when the clock frequency is 256000Hz and the chopper clock frequency is half of the clock frequency, fig. 3 is a power spectrum density diagram of the output signal of the Sigma-Delta modulator.
In summary, the present disclosure has the following technical features:
(1) The high-precision Sigma-Delta modulator circuit with the chopper has the advantages that the structure is simple, the high performance is maintained, and meanwhile, the power consumption is low;
(2) The chopper circuit can effectively inhibit low-frequency noise, and has simple structure and low power consumption;
(3) The structure adopted by the method is a 3-order structure of cascade connection of 3 integrators, so that the 4 th integrator can be simply cascaded to realize the improvement of the performance at the cost of improving the power consumption; or simply increasing the clock frequency, the performance of the modulator can be improved at the cost of improving the power consumption, and the expansibility is good.
Furthermore, the particular embodiments described herein may vary from one embodiment to another, and the above description is merely illustrative of the structure of the present invention. Equivalent or simple changes of the structure, characteristics and principle of the present invention are included in the protection scope of the present invention. Various modifications or additions to the described embodiments or similar methods may be made by those skilled in the art without departing from the structure of the invention or exceeding the scope of the invention as defined in the accompanying claims.
Claims (7)
1. A Sigma-Delta modulator circuit with chopping, comprising the following modules:
the integrator 11, the integrator 12 and the integrator 13 are three integrators, the integrator 11, the integrator 12 and the integrator 13 are sequentially connected step by step in sequence,
The system inputs are connected to the inputs of integrator 11, integrator 12, integrator 13 and quantizer 14 respectively,
The outputs of integrator 11 and integrator 12 each have a feed-forward path connected to quantizer 14, and the output of integrator 13 has an additional feedback path connected to the input of integrator 12;
A quantizer 14, whose input end is connected to the integrator 11, the integrator 12 feed-forward path, and the integrator 13, for quantizing the output results of the three and outputting a digital signal;
A feedback DAC 15, the input of which is connected to the system output of the quantizer 14, for feeding back a digital signal to the input of the integrator 11.
2. A Sigma-Delta modulator circuit with chopper according to claim 1, characterized in that said integrator 11, integrator 12 and integrator 13 comprise operational amplifiers, which constitute the core of the integrator.
3. A Sigma-Delta modulator circuit with chopping according to claim 1 or 2, characterized in that the integrator 11 further comprises a chopper circuit for reducing low frequency noise and improving the performance of the modulator.
4. A Sigma-Delta modulator circuit with chopping according to claim 1, characterized in that said quantizer 14 consists of a comparator and a latch.
5. A Sigma-Delta modulator circuit with chopper according to claim 1, characterized in that the feedback DAC 15 feeds back a digital output signal to the input of the integrator 11 for providing the necessary feedback signal for the modulator.
6. The Sigma-Delta modulator circuit with chopper according to claim 1, further comprising, as an embodiment, an integrator feedforward coefficient module 16, an input coefficient module 17, a feedback DAC coefficient module 18, and an integrator feedback coefficient module 19:
three outputs of the integrator 11, the integrator 12 and the integrator 13 pass through a feedforward coefficient module 16, a system input passes through an input coefficient module 17, and the four outputs are summed to be used as inputs of the quantizer 14;
the output of the quantizer 14 is the system output and is also the input to the feedback DAC module 15;
the output of the feedback DAC module 15 is summed via a feedback DAC coefficient module 18 with the system input via the input coefficient module 17 as an input to the integrator 11;
the system input is added to the integrator 13 via the input coefficient module 17; the output of integrator 13 is also fed into integrator 12 via integrator feedback coefficient block 19, together with the system input via input coefficient block 17.
7. The Sigma-Delta modulator circuit with chopping of claim 1, wherein said integrator comprises 2 first switches 1111, 1112 and 4 second switches 1121, 1122, 1123, 1124 and first operational amplifier OTA1 and 2 sampling capacitors 1141, 1142 and 2 integrating capacitors 1151, 1152 and chopper circuits 1131, 1132, wherein:
The left sides of the 2 first switches 1111 and 1112 are connected with the system input, the right sides are respectively connected with 2 sampling capacitors 1141 and 1142, the right sides of the sampling capacitors 1141 are connected with second switches 1121 and 1123, the right sides of the sampling capacitors 1142 are connected with second switches 1122 and 1124, the other ends of the second switches 1123 and 1124 are grounded, the other sides of the second switches 1121 and 1122 are respectively connected with chopper switches 1131 and 1132 and integrating capacitors 1151 and 1152, the other sides of the integrating capacitors 1151 and 1152 are respectively connected with the output of the integrator 11 and the chopper circuit 1132, the right side of the chopper circuit 1131 is connected with the input of the operational amplifier OTA1, and the left side of the chopper circuit 1132 is connected with the output of the operational amplifier OTA 1; the first switches 1111, 1112 and the second switches 1121, 1122, 1123, 1124 are controlled by two-phase non-overlapping clocks; chopper circuits 1131, 1132 are controlled by another set of clocks different from the previous set.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410076454.0A CN118100945A (en) | 2024-01-18 | 2024-01-18 | Sigma-Delta modulator circuit with chopper |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410076454.0A CN118100945A (en) | 2024-01-18 | 2024-01-18 | Sigma-Delta modulator circuit with chopper |
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| CN118100945A true CN118100945A (en) | 2024-05-28 |
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| CN202410076454.0A Pending CN118100945A (en) | 2024-01-18 | 2024-01-18 | Sigma-Delta modulator circuit with chopper |
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- 2024-01-18 CN CN202410076454.0A patent/CN118100945A/en active Pending
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