CN118100945A - Sigma-Delta modulator circuit with chopper - Google Patents

Abstract

The present invention relates to a Sigma-Delta modulator circuit with chopping. The modulator circuit comprises three cascaded integrators, a chopping circuit, a quantizer, and a feedback digital module. The integrator comprises a chopping circuit; the three integrators and the quantizer are connected in sequence; the system input has four paths, which are respectively connected to the inputs of the three integrators and the quantizer; the outputs of the integrator (11) and the integrator (12) each have a feedforward path connected to the quantizer; the output of the quantizer is the system output, which is connected to the integrator (11) through a feedback DAC; the output of the integrator (13) has an additional feedback path connected to the input of the integrator (12). The present invention has a simple structure, and has the advantages of effectively reducing low-frequency noise with the chopping technology, not being easy to overload the outputs of the integrators at all levels, high precision, and low power consumption.

Description

A Sigma-Delta modulator circuit with chopping

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a Sigma-Delta modulator circuit with chopping.

Background technique

With the development of digital signal processing technology, more and more systems use digital signals as the medium of control system, so a module that converts analog signals into digital signals is needed, and analog-to-digital converter (ADC) has become a very important part of modern signal processing system. As a conversion module between analog signals and digital signals, the speed and accuracy of ADC determine and limit the speed and accuracy of digital control system, and determine the final signal processing results.

Sigma-Delta ADC is widely used in precision medical instruments, sensors, high-quality audio and other occasions with high accuracy requirements. It uses oversampling and noise shaping technology to make the ADC insensitive to circuit mismatch and has high accuracy, which can meet the high accuracy requirements of precision equipment.

The Sigma-Delta modulator forms the core of the ADC. The modulator superimposes the input signal and the feedback signal through each stage of the integrator and integrates them. The output of each stage is used as part of the input of the next stage. In the modulator, the quantization noise of the integrator will gradually decrease after being processed by the previous stage integrator, so the first stage integrator is particularly sensitive to low-frequency noise. Since the modulator using low-pass filtering cannot filter out low-frequency noise, and the shaping effect of the first stage integrator on low-frequency noise depends largely on the oversampling rate (OSR), increasing the OSR will significantly increase the power consumption of the system and increase the difficulty of circuit design. There needs to be a way to reduce the sensitivity of the first stage integrator to low-frequency noise without significantly increasing power consumption, thereby improving the overall signal-to-noise ratio (SNR) of the modulator.

Summary of the invention

The embodiments described herein provide a Sigma-delta modulator circuit. The product structure of the present invention is simple, and the chopping technology effectively reduces low-frequency noise, the output of each level of integrator is not easy to overload, the accuracy is high, and the power consumption is low.

Technical solutions:

A Sigma-Delta modulator circuit with chopping, characterized by comprising the following modules:

Integrator 11, integrator 12 and integrator 13 are three integrators, and integrator 11, integrator 12 and integrator 13 are connected in sequence step by step.

The system input is connected to the inputs of integrator 11, integrator 12, integrator 13 and quantizer 14 respectively.

The outputs of integrators 11 and 12 each have a feedforward path connected to quantizer 14, and the output of integrator 13 has an additional feedback path connected to the input of integrator 12;

A quantizer 14, whose input end is connected to the integrator 11, the feedforward path of the integrator 12, and the integrator 13, for quantizing the output results of the three and outputting a digital signal;

The feedback DAC 15 , whose input is connected to the system output of the quantizer 14 , is used to feed back the digital signal to the input of the integrator 11 .

In a preferred embodiment, the integrators 11, 12 and 13 include operational amplifiers, and high-gain operational amplifiers form the core of the integrators.

In a preferred embodiment, the integrator 11 further includes a chopper circuit for reducing low-frequency noise and improving the performance of the modulator.

In a preferred embodiment, the quantizer 14 is composed of a comparator and a latch.

In a preferred embodiment, the feedback DAC 15 feeds back the digital output signal to the input terminal of the integrator 11 to provide the feedback signal necessary for the modulator.

The circuit module for implementing the Sigma-Delta modulator provided by the present invention adopts a full feedforward structure, and each level of integrator is not easy to be overloaded, has a simple structure, low power consumption, and can maintain high precision. The chopper circuit included in the integrator 11 effectively suppresses low-frequency noise through simple switch control, has a simple structure, can improve the overall performance of the modulator, does not need to increase OSR, and has low power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic block diagram of a Sigma-Delta modulator circuit 10 according to an embodiment of the present disclosure;

FIG2 is an exemplary circuit diagram of the integrator 11 in FIG1 ;

FIG. 3 is a power spectral density diagram of an output signal of the Sigma-Delta modulator circuit 10 according to an embodiment of the present disclosure.

The elements in the drawings are schematic and not drawn to scale.

Detailed ways

The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings so that the purpose, features and advantages of the present invention can be more clearly understood. It should be understood that the embodiments shown in the accompanying drawings are not intended to limit the scope of the present invention, but are only intended to illustrate the essential spirit of the technical solution of the present invention.

In the following description, certain specific details are set forth for the purpose of illustrating various disclosed embodiments to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the relevant art will recognize that the embodiments may be practiced without one or more of these specific details. In other cases, well-known devices, structures, and techniques associated with the present application may not be shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

References throughout the specification to "one embodiment" or "an embodiment" indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any manner in one or more embodiments.

In the following description, in order to clearly show the structure and working mode of the present invention, many directional words will be used for description, but the words "front", "back", "left", "right", "outside", "inside", "outward", "inward", "up", "down", etc. should be understood as convenient terms and should not be understood as restrictive terms.

Please refer to Fig. 1. Fig. 1 is a schematic block diagram of a Sigma-Delta modulator 10 with chopping proposed in an embodiment of the present disclosure, which mainly includes an integrator 11, an integrator 12, an integrator 13, a quantizer 14, a feedback DAC module 15, an integrator feedforward coefficient module 16, an input coefficient module 17, a feedback DAC coefficient module 18, and an integrator feedback coefficient module 19. The integrator 11, the integrator 12 and the integrator 13 are cascaded in sequence; the three outputs of the integrator 11, the integrator 12 and the integrator 13 pass through the feedforward coefficient module 16, and the system input passes through the input coefficient module 17, and the four are summed as the input of the quantizer 14; the output of the quantizer 14 is the system output and is also the input of the feedback DAC module 15; the output of the feedback DAC module 15 is summed with the system input passing through the input coefficient module 17 via the feedback DAC coefficient module 18 as the input of the integrator 11; the system input is added to the integrator 13 via the input coefficient module 17; in addition, the output of the integrator 13 is added to the integrator 12 together with the system input passing through the input coefficient module 17 via the integrator feedback coefficient module 19.

In FIG. 1 , the integrator feedforward coefficient module 16 , the input coefficient module 17 , the feedback DAC coefficient module 18 , and the integrator feedback coefficient module 19 are all carefully designed to ensure that their corresponding circuits meet the performance requirements of the modulator circuit 10 .

Please refer to Figure 2. Figure 2 is an exemplary circuit diagram of the integrator 11 in Figure 1. The integrator 11 includes two first switches 1111 and 1112, four second switches 1121, 1122, 1123, and 1124, a first operational amplifier OTA1, two sampling capacitors 1141 and 1142, two integrating capacitors 1151 and 1152, and chopping circuits 1131 and 1132, wherein:

The left sides of the two first switches 1111 and 1112 are connected to the system input, and the right sides are connected to the two sampling capacitors 1141 and 1142 respectively. The right side of the sampling capacitor 1141 is connected to the second switches 1121 and 1123, and the right side of the sampling capacitor 1142 is connected to the second switches 1122 and 1124. The other ends of the second switches 1123 and 1124 are grounded. The other sides of the second switches 1121 and 1122 are connected to the chopping switches 1131 and 1132 and the integrating capacitors 1151 and 1152 respectively. The other sides of the integrating capacitors 1151 and 1152 are connected to the output of the integrator 11 and the chopping circuit 1132 respectively. The right side of the chopping circuit 1131 is connected to the input of the operational amplifier OTA1, and the left side of the chopping circuit 1132 is connected to the output of the operational amplifier OTA1. The first switches 1111 , 1112 and the second switches 1121 , 1122 , 1123 , 1124 are controlled by two-phase non-overlapping clocks; the chopper circuits 1131 , 1132 are controlled by another group of clocks different from the previous group.

In addition, the structures of the integrator 12, the integrator 13, the quantizer 14, and the feedback DAC module 15 in FIG. 1 are well known and will not be described in detail here.

See Figure 3. The amplitude of the input signal is 0.6 volts. When the clock frequency is 256000 Hz and the chopping clock frequency is half of the clock frequency, Figure 3 is a power spectrum density diagram of the output signal of the Sigma-Delta modulator.

In summary, the present disclosure has the following beneficial effects with respect to the technical features:

(1) A high-precision Sigma-Delta modulator circuit with chopping is proposed, which has a simple structure and low power consumption while maintaining high performance;

(2) The chopper circuit can effectively suppress low-frequency noise and has a simple structure and low power consumption;

(3) The structure adopted by the present invention is a third-order structure of three cascaded integrators. At the expense of increased power consumption, the performance can be improved by simply cascading a fourth integrator; or simply increasing the clock frequency can also improve the modulator performance at the expense of increased power consumption, and has good scalability.

In addition, it should be noted that the specific embodiments described in this specification may be named differently, and the above content described in this specification is only an example of the structure of the present invention. All equivalent changes or simple changes made based on the structure, features and principles of the present invention are included in the protection scope of the present invention. Those skilled in the art of the present invention may make various modifications or supplements to the specific examples described or adopt similar methods, as long as they do not deviate from the structure of the present invention or exceed the scope defined by the claims, they should all fall within the protection scope of the present invention.

Claims (7)

1. A Sigma-Delta modulator circuit with chopping, characterized in that it includes the following modules: Integrator 11, integrator 12 and integrator 13 are three integrators, and integrator 11, integrator 12 and integrator 13 are connected in sequence step by step. The system input is connected to the inputs of integrator 11, integrator 12, integrator 13 and quantizer 14 respectively. The outputs of integrators 11 and 12 each have a feedforward path connected to quantizer 14, and the output of integrator 13 has an additional feedback path connected to the input of integrator 12; A quantizer 14, whose input end is connected to the integrator 11, the feedforward path of the integrator 12, and the integrator 13, for quantizing the output results of the three and outputting a digital signal; The feedback DAC 15 , whose input is connected to the system output of the quantizer 14 , is used to feed back the digital signal to the input of the integrator 11 . 2. A Sigma-Delta modulator circuit with chopping according to claim 1, characterized in that the integrator 11, the integrator 12 and the integrator 13 include operational amplifiers, which constitute the core of the integrators. 3. A Sigma-Delta modulator circuit with chopping according to claim 1 or 2, characterized in that the integrator 11 also includes a chopping circuit for reducing low-frequency noise and improving the performance of the modulator. 4 . The Sigma-Delta modulator circuit with chopping according to claim 1 , wherein the quantizer 14 is composed of a comparator and a latch. 5. The Sigma-Delta modulator circuit with chopping according to claim 1, characterized in that the feedback DAC 15 feeds back the digital output signal to the input end of the integrator 11 to provide the feedback signal required by the modulator. 6. A Sigma-Delta modulator circuit with chopping according to claim 1, characterized in that, as an embodiment and technical solution, it also includes an integrator feedforward coefficient module 16, an input coefficient module 17, a feedback DAC coefficient module 18, and an integrator feedback coefficient module 19: The three outputs of the integrator 11, the integrator 12, and the integrator 13 pass through the feedforward coefficient module 16, and the system input passes through the input coefficient module 17, and the sum of the four is used as the input of the quantizer 14; The output of the quantizer 14 is the system output and is also the input of the feedback DAC module 15; The output of the feedback DAC module 15 is summed with the system input through the input coefficient module 17 via the feedback DAC coefficient module 18 as the input of the integrator 11; The system input is added to the integrator 13 via the input coefficient module 17 . In addition, the output of the integrator 13 is added to the integrator 12 together with the system input via the input coefficient module 17 via the integrator feedback coefficient module 19 . 7. A Sigma-Delta modulator circuit with chopping according to claim 1, characterized in that the integrator comprises two first switches 1111, 1112, four second switches 1121, 1122, 1123, 1124, a first operational amplifier OTA1, two sampling capacitors 1141, 1142, two integrating capacitors 1151, 1152, and chopping circuits 1131, 1132, wherein: The left sides of the two first switches 1111 and 1112 are connected to the system input, and the right sides are connected to the two sampling capacitors 1141 and 1142 respectively. The right side of the sampling capacitor 1141 is connected to the second switches 1121 and 1123. The right side of the sampling capacitor 1142 is connected to the second switches 1122 and 1124, the other ends of the second switches 1123 and 1124 are grounded, the other sides of the second switches 1121 and 1122 are respectively connected to the chopping switches 1131 and 1132 and the integrating capacitors 1151 and 1152, the other sides of the integrating capacitors 1151 and 1152 are respectively connected to the output of the integrator 11 and the chopping circuit 1132, the right side of the chopping circuit 1131 is connected to the input of the operational amplifier OTA1, and the left side of the chopping circuit 1132 is connected to the output of the operational amplifier OTA1; the first switches 1111 and 1112, the second switches 1121, 1122, 1123, and 1124 are controlled by two-phase non-overlapping clocks; the chopping circuits 1131 and 1132 are controlled by another group of clocks different from the previous group.