WO2009133653A9 - Integrator, resonator, and oversampling a/d converter - Google Patents

Integrator, resonator, and oversampling a/d converter Download PDF

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Publication number
WO2009133653A9
WO2009133653A9 PCT/JP2009/001162 JP2009001162W WO2009133653A9 WO 2009133653 A9 WO2009133653 A9 WO 2009133653A9 JP 2009001162 W JP2009001162 W JP 2009001162W WO 2009133653 A9 WO2009133653 A9 WO 2009133653A9
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Prior art keywords
integrator
filter
converter
operational amplifier
quantizer
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PCT/JP2009/001162
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French (fr)
Japanese (ja)
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WO2009133653A1 (en
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道正志郎
森江隆史
松川和生
三谷陽介
高山雅夫
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パナソニック株式会社
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Priority to EP09738590A priority Critical patent/EP2273682A4/en
Priority to JP2010510020A priority patent/JP4875767B2/en
Priority to CN200980113833.6A priority patent/CN102067457B/en
Publication of WO2009133653A1 publication Critical patent/WO2009133653A1/en
Priority to US12/888,126 priority patent/US8258990B2/en
Publication of WO2009133653A9 publication Critical patent/WO2009133653A9/en

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00Conversion of analogue values to or from differential modulation
    • H03M3/30Delta-sigma modulation
    • H03M3/39Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/438Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path
    • H03M3/454Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00Conversion of analogue values to or from differential modulation
    • H03M3/30Delta-sigma modulation
    • H03M3/39Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/402Arrangements specific to bandpass modulators
    • H03M3/404Arrangements specific to bandpass modulators characterised by the type of bandpass filters used
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00Conversion of analogue values to or from differential modulation
    • H03M3/30Delta-sigma modulation
    • H03M3/39Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/43Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a single bit one

Definitions

  • the present invention relates to an integrator, and more particularly to an integrator suitable for a continuous-time ⁇ modulator.
  • the oversampling A / D converter is widely used for the front end of communication equipment and audio signal conversion, and is an essential circuit technology for current communication, video and audio signal processing circuits.
  • One of the oversampling A / D converters is a continuous-time ⁇ A / D converter (CTDS-ADC) with a continuous-time filter (for example, non-patent literature). 1 and 2).
  • CTDS-ADC In a general CTDS-ADC, an input signal is quantized by a quantizer through n cascaded integrators (continuous time filters). The digital output of the quantizer is converted into an analog current signal by n D / A converters and then fed back to each of n integrators.
  • the analog circuit portion does not include a switch, the voltage can be reduced.
  • a pre-filter that is normally required when a sampling filter is used is not necessary in the CTDS-ADC. From these points, CTDS-ADC is suitable for application to communication systems, and in recent years, application development research has become active.
  • an object of the present invention is to provide an integrator that exhibits high-order integration characteristics with a single operational amplifier. It is another object of the present invention to provide a resonator using such an integrator and a time continuous oversampling A / D converter.
  • An integrator having an operational amplifier, a first filter connected to the inverting input terminal of the operational amplifier, and a second filter connected between the inverting input terminal and the output terminal of the operational amplifier;
  • the first filter has n resistance elements connected in series, and n ⁇ 1 capacitance elements having one end connected to each connection point of the resistance elements and the other end grounded.
  • the second filter includes n capacitive elements connected in series and n ⁇ 1 resistive elements having one end connected to each connection point of the capacitive elements and the other end grounded.
  • n is an integer of 2 or more.
  • the transfer function of the integrator is In the denominator and numerator, the terms from s (where s is a Laplace operator) to s n ⁇ 1 are canceled to become only 1 / s n terms. That is, an n-order integrator can be configured with one operational amplifier.
  • the integrator further includes a third filter having at least one of a resistance element and a capacitance element connected in parallel to the first filter.
  • the third filter acts as a feedforward path between the input of the integrator and the inverting input terminal of the operational amplifier.
  • An oversampling A / D converter includes the integrator, a quantizer that quantizes the output of the integrator, and a digital output of the quantizer that converts the digital output into a current signal.
  • N-1 D / A converters that feed back to each connection point of the resistive element in the filter and the digital output of the quantizer are converted into current signals and fed back to each connection point of the capacitive element in the second filter.
  • an oversampling A / D converter according to the present invention includes the integrator described above, a quantizer that quantizes the output of the integrator, and a digital output of the quantizer that is converted into a current signal.
  • an oversampling A / D converter includes an integrator including the third filter, a quantizer that quantizes the output of the integrator, and a digital output of the quantizer as a current signal. And a D / A converter that feeds back to the input side of the integrator.
  • n-order integrator and n-order resonator can be obtained. Furthermore, it is possible to reduce the size and power consumption of the oversampling A / D converter with high resolution and high S / N ratio.
  • FIG. 1 is a configuration diagram of an integrator according to the first embodiment.
  • FIG. 2 is a configuration diagram of an integrator according to the second embodiment.
  • FIG. 3 is a configuration diagram of an integrator according to the third embodiment.
  • FIG. 4 is a configuration diagram of an oversampling A / D converter according to the fourth embodiment.
  • FIG. 5 is a configuration diagram of an oversampling A / D converter according to the fifth embodiment.
  • FIG. 6 is a configuration diagram of an oversampling A / D converter according to the sixth embodiment.
  • FIG. 7 is a graph showing a simulation result of the transient response of the resonator according to the present invention shown in FIG.
  • FIG. 8 is a configuration diagram of an oversampling A / D converter according to the seventh embodiment.
  • FIG. 8 is a configuration diagram of an oversampling A / D converter according to the seventh embodiment.
  • FIG. 9 is a graph showing a simulation result of the transient response of the resonator according to the present invention shown in FIG.
  • FIG. 10 is a configuration diagram of an oversampling A / D converter according to the eighth embodiment.
  • FIG. 11 is a configuration diagram of an oversampling A / D converter according to the ninth embodiment.
  • FIG. 1 shows a configuration of an integrator according to the first embodiment.
  • the integrator 10 includes an operational amplifier 11, a filter 12 connected to the inverting input terminal of the operational amplifier 11, and a filter 13 connected between the inverting input terminal and the output terminal of the operational amplifier 11.
  • the filter 12 is a secondary low-pass filter including two resistance elements 121 connected in series, and a capacitance element 122 having one end connected to a connection point of these resistance elements and the other end grounded.
  • the filter 13 is a secondary high-pass filter including two capacitive elements 131 connected in series, and a resistive element 132 having one end connected to a connection point of these capacitive elements and the other end grounded.
  • the input voltage is V in
  • the output voltage is V out
  • the resistance value of the resistance element 121 is R 1
  • the capacitance value of the capacitance element 122 is C 1
  • the resistance value of the resistance element 132 is R 2
  • the resistance element 121 is a Laplace operator.
  • the transfer function of the integrator 10 is derived as follows.
  • a single-stage operational amplifier 11 can constitute a secondary integrator.
  • a fourth-order or higher order integrator can be configured by multiplexing the integrators 10 according to the present embodiment. For example, by multiplexing two integrators 10 according to this embodiment, a four-order integrator can be configured with two operational amplifiers 11.
  • FIG. 2 shows a configuration of an integrator according to the second embodiment.
  • the integrator 10 includes filters 12 and 13 having a configuration different from that of the integrator 10 of FIG. That is, the filter 12 includes three or more resistance elements 121 connected in series, one end connected to each connection point of these resistance elements, the other end grounded, and one capacitive element 122 less than the resistance element 121. An n-order low-pass filter provided.
  • the filter 13 includes three or more capacitive elements 131 connected in series, one end connected to each connection point of these capacitive elements, the other end grounded, and one less resistive element 132 than the capacitive element 131. It is an nth order high pass filter.
  • the transfer function of the integrator 10 is generally expressed by the following equation.
  • ⁇ , ⁇ , ⁇ , ⁇ , and ⁇ are constants determined by the element values of the resistance elements 121 and 132 and the capacitance elements 122 and 131.
  • an n-order integrator can be configured with one operational amplifier.
  • the two resistance elements 121 in the filter 12 may have different resistance values.
  • the two capacitive elements 131 in the filter 13 may also have different resistance values.
  • the second-order or higher-order integrator 10 can be configured by satisfying a predetermined relationship between the element values of the resistance elements 121 and 132 and the capacitance elements 122 and 131.
  • FIG. 3 shows a configuration of an integrator according to the third embodiment.
  • the integrator 10 is obtained by adding a filter 14 to the integrator 10 of FIG. 1 or FIG.
  • the filter 14 includes a resistance element 141 and a capacitance element 142 connected in parallel to the filter 12.
  • the filter 14 acts as a feedforward path between the input of the integrator 10 and the inverting input terminal of the operational amplifier 11.
  • zeroth-order, first-order and second-order integral components can be generated in the output of the integrator 10.
  • the integral component of each order can be adjusted by appropriately setting the element values of the resistor element 141 and the capacitor element 142.
  • either one of the resistor element 141 and the capacitor element 142 may be omitted.
  • a first-order integral component can be generated in the output of the integrator 10 in addition to the n-order integral component.
  • zero-order and first-order integral components can be generated at the output of the integrator 10.
  • FIG. 4 shows the configuration of a CSDS-ADC according to the fourth embodiment.
  • the CTDS-ADC according to the present embodiment includes an integrator 10 in FIG. 1, a quantizer 20 that quantizes the output of the integrator 10, a digital output of the quantizer 20 into a current signal, and a resistive element in the filter 12.
  • a D / A converter 30 that feeds back to a connection point 121 and a D / A converter 40 that converts the digital output of the quantizer 20 into a current signal and feeds back to the connection point of the capacitive element 131 in the filter 13 are provided.
  • the output current of the D / A converter 30 is I 1
  • the output current of the D / A converter 40 is I 2
  • the following nodal equation is derived.
  • an oversampling A / D converter having secondary filtering characteristics can be configured with one operational amplifier 11.
  • An oversampling A / D converter that exhibits fourth-order or higher filtering characteristics can be configured by multiplexing the integrator 10. For example, by multiplexing two integrators 10, an oversampling A / D converter that exhibits fourth-order filtering characteristics can be configured with two operational amplifiers 11.
  • FIG. 5 shows a configuration of a CSDS-ADC according to the fifth embodiment.
  • the CTDS-ADC according to the present embodiment includes an integrator 10 in FIG. 2, a quantizer 20 that quantizes the output of the integrator 10, a digital output of the quantizer 20 into a current signal, and a resistive element in the filter 12.
  • a plurality of D / A converters 30 that feed back to each connection point 121 and a plurality of D / A conversions that convert the digital output of the quantizer 20 into a current signal and feed back to each connection point of the capacitive element 131 in the filter 13.
  • a container 40 is provided.
  • the integrator 10 exhibits the n-th order integration characteristic by satisfying a predetermined relationship between the element values of the resistance elements 121 and 132 and the capacitance elements 122 and 131.
  • an oversampling A / D converter that exhibits n-th order filtering characteristics can be configured with one operational amplifier 11.
  • FIG. 6 shows a configuration of a CTDS-ADC according to the sixth embodiment.
  • the CTDS-ADC according to the present embodiment includes a general primary integrator 10 ′ and secondary resonators 10A and 10A ′, and exhibits a fifth-order filtering characteristic as a whole.
  • symbols shown beside each element represent each element value.
  • the resonators 10A and 10A ′ are obtained by adding a Gm element (transconductor element) 15 to the integrator 10 of FIG.
  • the Gm element 15 feeds back the output of the operational amplifier 11 to the connection point of the resistance element in the filter 12.
  • FIG. 7 shows a simulation result of the transient response of the resonator 10A when a 5 MHz sine wave near the resonance frequency is input to the resonator 10A shown in FIG.
  • the gain of the operational amplifier 11 is 70 dB
  • GBW is 200 MHz. From this simulation result, it can be seen that the resonator 10A does not oscillate.
  • FIG. 8 shows a configuration of a CTDS-ADC according to the seventh embodiment.
  • the CTDS-ADC according to this embodiment is obtained by replacing the Gm element 15 in the resonators 10A and 10A ′ with a resistance element 16 in the CTDS-ADC of FIG.
  • FIG. 9 shows a simulation result of the transient response of the resonator 10A when a 5 MHz sine wave near the resonance frequency is input to the resonator 10A shown in FIG.
  • the gain of the operational amplifier 11 is 70 dB
  • GBW is 200 MHz. From this simulation result, it can be seen that the resonator 10A does not oscillate.
  • the resonator 10A according to the present embodiment has better transient response characteristics than the resonator 10A according to the sixth embodiment.
  • FIG. 10 shows a configuration of a CTDS-ADC according to the eighth embodiment.
  • the CTDS-ADC according to the present embodiment includes a general first-order integrator 10 ′ and a third-order resonator 10A, and exhibits a fourth-order filtering characteristic as a whole.
  • the resonator 10A is obtained by adding three Gm elements 15 to the integrator 10 of FIG. Each Gm element 15 feeds back the output of the operational amplifier 11 to each connection point of the resistance element in the filter 12. Similarly to the CTDS-ADC in FIG. 5, the outputs of the three D / A converters 30 are fed back to the connection points of the resistive elements in the filter 12. On the other hand, unlike the CTDS-ADC of FIG. 5, the output of the D / A converter 40 is fed back to the inverting input terminal of the operational amplifier 11 instead of the connection points of the capacitive elements in the filter 13.
  • the total number of D / A converters can be relatively small, and the circuit scale and power consumption can be reduced.
  • the Gm element 15 may be replaced with a resistance element. Further, it is not necessary to connect the Gm element 15 or the resistance element to all connection points of the resistance element in the filter 12. That is, a resonator can be configured by feeding back the output of the operational amplifier 11 to at least one connection point of the resistive element in the filter 12 via the Gm element or the resistive element.
  • FIG. 11 shows the configuration of a CTDS-ADC according to the ninth embodiment.
  • the CTDS-ADC according to the present embodiment includes a general first-order integrator 10 ′ and a second-order resonator 10A, and exhibits a third-order filtering characteristic as a whole.
  • the resonator 10 ⁇ / b> A is obtained by adding a resistance element 16 that feeds back the output of the operational amplifier 11 to the connection point of the resistance element in the filter 12 to the integrator 10 of FIG. 3.
  • the filter 14 acts as a feedforward path between the input of the resonator 10A and the inverting input terminal of the operational amplifier 11. Therefore, the phase compensation of the CTDS-ADC can be performed without feeding back the output of the quantizer 20 to the connection point of the resistive element in the filter 12. Therefore, according to this embodiment, the number of D / A converters can be further reduced, and the circuit scale and power consumption can be further reduced.
  • the resistance element 16 may be replaced with a Gm element. Further, the resistance element 16 may be omitted. In this case, the CTDS-ADC exhibits a filtering characteristic having no zero point in the transmission characteristic of the quantization noise.
  • each resistance element may be configured with a switched capacitor circuit.
  • the integrator 10 and the resonators 10A and 10A ' can be made into discrete filters. Since the discrete filter can determine the transfer function of the circuit by the capacitance ratio, the filtering accuracy can be improved.
  • the integrator, the resonator, and the oversampling A / D converter according to the present invention exhibit high-order integration characteristics and filtering characteristics with a relatively small scale and low power consumption, and thus are useful for portable communication devices and the like.

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Abstract

An integrator (10) comprises an operational amplifier (11), a first filter (12) connected to the inverting input terminal of the operational amplifier, and a second filter (13) connected between the inverting input terminal and the output terminal of the operational amplifier. The first filter (12) includes n-pieces of resistive elements (121) connected in series and (n-1)-pieces of capacitive elements (122) each having one end connected to each connection node of the resistive elements and the other end connected to ground. The second filter (13) includes n-pieces of capacitive elements (131) connected in series and (n-1)-pieces of resistive elements (132) each having one end connected to each connection node of the capacitive elements and the other end connected to ground.

Description

積分器、共振器及びオーバーサンプリングA/D変換器Integrator, resonator and oversampling A / D converter
 本発明は、積分器に関し、特に、連続時間型ΔΣ変調器に好適な積分器に関する。 The present invention relates to an integrator, and more particularly to an integrator suitable for a continuous-time ΔΣ modulator.
 オーバーサンプリングA/D変換器は通信機器のフロントエンドや音声信号の変換などに広く用いられており、現在の通信、映像、音声信号処理回路に必須の回路技術である。オーバーサンプリングA/D変換器の一つに、連続時間型フィルタを備えた連続時間型ΔΣA/D変換器(CTDS-ADC:Continuous Time Delta-Sigma A/D comverter)がある(例えば、非特許文献1,2参照)。 The oversampling A / D converter is widely used for the front end of communication equipment and audio signal conversion, and is an essential circuit technology for current communication, video and audio signal processing circuits. One of the oversampling A / D converters is a continuous-time ΔΣ A / D converter (CTDS-ADC) with a continuous-time filter (for example, non-patent literature). 1 and 2).
 一般的なCTDS-ADCでは、入力信号は縦続接続されたn個の積分器(連続時間型フィルタ)を通って量子化器によって量子化される。量子化器のデジタル出力はn個のD/A変換器によってアナログ電流信号に変換されてからn個の積分器のそれぞれにフィードバックされる。CTDS-ADCでは、アナログ回路部分にスイッチが含まれないため低電圧化が可能となる。また、サンプリングフィルタを用いた場合に通常必要となる前置フィルタがCTDS-ADCでは不要である。これらの点から、CTDS-ADCは通信システムへの応用に適しており、近年、応用開発研究が盛んとなっている。
Richard Schreier and Bo Bang, "Delta-Sigma Modulators Employing Continuous-Time Circuitry", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 43, NO. 4, APRIL 1996 Xuefeng Chen et al., "A 18mW CT ΔΣ Modulator with 25MHz Bandwidth for Next Generation Wireless Applications", IEEE 2007 Custom Intergrated Circuits Conference, 2007
In a general CTDS-ADC, an input signal is quantized by a quantizer through n cascaded integrators (continuous time filters). The digital output of the quantizer is converted into an analog current signal by n D / A converters and then fed back to each of n integrators. In the CTDS-ADC, since the analog circuit portion does not include a switch, the voltage can be reduced. In addition, a pre-filter that is normally required when a sampling filter is used is not necessary in the CTDS-ADC. From these points, CTDS-ADC is suitable for application to communication systems, and in recent years, application development research has become active.
Richard Schreier and Bo Bang, "Delta-Sigma Modulators Employing Continuous-Time Circuitry", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 43, NO. 4, APRIL 1996 Xuefeng Chen et al., "A 18mW CT ΔΣ Modulator with 25MHz Bandwidth for Next Generation Wireless Applications", IEEE 2007 Custom Intergrated Circuits Conference, 2007
 CTDS-ADCにおいて分解能とSN性能を向上させるには量子化ノイズ除去のためのフィルタ次数を上げる必要があり、その次数分の演算増幅器が必要となる。すなわち、CTDS-ADCの性能を向上しようとすると多数の演算増幅器を使用しなければならなくなる。しかし、演算増幅器の個数増加は回路規模と消費電力の増加を招くこととなり、携帯通信機器などに応用されるシステムLSIの性能向上に係るボトルネックの一因となる。 In order to improve resolution and SN performance in CTDS-ADC, it is necessary to increase the filter order for removing quantization noise, and operational amplifiers for that order are required. That is, in order to improve the performance of the CTDS-ADC, a large number of operational amplifiers must be used. However, an increase in the number of operational amplifiers leads to an increase in circuit scale and power consumption, which contributes to a bottleneck for improving the performance of a system LSI applied to portable communication devices and the like.
 上記問題に鑑み、本発明は、1個の演算増幅器で高次の積分特性を発揮する積分器を提供することを課題とする。さらに、そのような積分器を用いた共振器及び時間連続型オーバーサンプリングA/D変換器を提供することを課題とする。 In view of the above problems, an object of the present invention is to provide an integrator that exhibits high-order integration characteristics with a single operational amplifier. It is another object of the present invention to provide a resonator using such an integrator and a time continuous oversampling A / D converter.
 上記課題を解決するために本発明は次のような手段を講じた。積分器として、演算増幅器と、演算増幅器の反転入力端に接続された第1のフィルタと、演算増幅器の反転入力端と出力端との間に接続された第2のフィルタとを備えたものとする。ここで、第1のフィルタは、直列接続されたn個の抵抗素子と、一端が前記抵抗素子の各接続点に接続され、他端が接地されたn-1個の容量素子とを有する。また、第2のフィルタは、直列接続されたn個の容量素子と、一端が容量素子の各接続点に接続され、他端が接地されたn-1個の抵抗素子とを有する。ただし、nは2以上の整数である。 In order to solve the above problems, the present invention has taken the following measures. An integrator having an operational amplifier, a first filter connected to the inverting input terminal of the operational amplifier, and a second filter connected between the inverting input terminal and the output terminal of the operational amplifier; To do. Here, the first filter has n resistance elements connected in series, and n−1 capacitance elements having one end connected to each connection point of the resistance elements and the other end grounded. The second filter includes n capacitive elements connected in series and n−1 resistive elements having one end connected to each connection point of the capacitive elements and the other end grounded. However, n is an integer of 2 or more.
 これによると、第1のフィルタにおける抵抗素子及び容量素子並びに第2のフィルタにおける抵抗素子及び容量素子の各素子値について所定の関係が成り立つようにすることで、当該積分器の伝達関数は、その分母及び分子においてs(sはラプラス演算子である)からsn-1までの項が打ち消されて1/sの項のみとなる。すなわち、1個の演算増幅器でn次積分器を構成することができる。 According to this, by making a predetermined relationship hold for each element value of the resistive element and the capacitive element in the first filter and the resistive element and the capacitive element in the second filter, the transfer function of the integrator is In the denominator and numerator, the terms from s (where s is a Laplace operator) to s n−1 are canceled to become only 1 / s n terms. That is, an n-order integrator can be configured with one operational amplifier.
 上記の積分器は、第1のフィルタに並列接続された抵抗素子及び容量素子の少なくとも一つを有する第3のフィルタをさらに備えていることが好ましい。これによると、第3のフィルタは当該積分器の入力と演算増幅器の反転入力端との間でフィードフォワードパスとして作用する。これにより、当該積分器の出力に0次、1次、及び2次積分成分を生じさせることができる。 It is preferable that the integrator further includes a third filter having at least one of a resistance element and a capacitance element connected in parallel to the first filter. According to this, the third filter acts as a feedforward path between the input of the integrator and the inverting input terminal of the operational amplifier. As a result, zero-order, first-order, and second-order integral components can be generated in the output of the integrator.
 上記の積分器に、第1のフィルタにおける抵抗素子の接続点の少なくとも一つと演算増幅器の出力端との間に接続された少なくとも一つのGm素子又は抵抗素子を追加すると、共振器を構成することができる。 If at least one Gm element or resistance element connected between at least one connection point of the resistance element in the first filter and the output terminal of the operational amplifier is added to the integrator, a resonator is formed. Can do.
 また、本発明に係るオーバーサンプリングA/D変換器は、上記の積分器と、積分器の出力を量子化する量子化器と、量子化器のデジタル出力を電流信号に変換して第1のフィルタにおける抵抗素子の各接続点にフィードバックするn-1個のD/A変換器と、量子化器のデジタル出力を電流信号に変換して第2のフィルタにおける容量素子の各接続点にフィードバックするn-1個のD/A変換器とを備えている。あるいは、本発明に係るオーバーサンプリングA/D変換器は、上記の積分器と、積分器の出力を量子化する量子化器と、量子化器のデジタル出力を電流信号に変換して第1のフィルタにおける抵抗素子の各接続点にフィードバックするn-1個のD/A変換器と、量子化器のデジタル出力を電流信号に変換して演算増幅器の反転入力端にフィードバックするD/A変換器とを備えている。あるいは、本発明に係るオーバーサンプリングA/D変換器は、上記の第3のフィルタを備えた積分器と、積分器の出力を量子化する量子化器と、量子化器のデジタル出力を電流信号に変換して積分器の入力側にフィードバックするD/A変換器とを備えている。これらオーバーサンプリングA/D変換器は、それが備えている演算増幅器の個数よりも高い次数のフィルタリング特性を発揮する。 An oversampling A / D converter according to the present invention includes the integrator, a quantizer that quantizes the output of the integrator, and a digital output of the quantizer that converts the digital output into a current signal. N-1 D / A converters that feed back to each connection point of the resistive element in the filter and the digital output of the quantizer are converted into current signals and fed back to each connection point of the capacitive element in the second filter. n-1 D / A converters. Alternatively, an oversampling A / D converter according to the present invention includes the integrator described above, a quantizer that quantizes the output of the integrator, and a digital output of the quantizer that is converted into a current signal. N-1 D / A converters that feed back to each connection point of the resistive elements in the filter, and a D / A converter that converts the digital output of the quantizer into a current signal and feeds it back to the inverting input terminal of the operational amplifier And. Alternatively, an oversampling A / D converter according to the present invention includes an integrator including the third filter, a quantizer that quantizes the output of the integrator, and a digital output of the quantizer as a current signal. And a D / A converter that feeds back to the input side of the integrator. These oversampling A / D converters exhibit higher-order filtering characteristics than the number of operational amplifiers included therein.
 なお、上記のオーバーサンプリングA/D変換器に、第1のフィルタにおける抵抗素子の接続点の少なくとも一つと演算増幅器の出力端との間に接続された少なくとも一つのGm素子又は抵抗素子を追加すると、量子化ノイズの伝達特性に零点を持つフィルタリング特性を発揮するようになる。 When at least one Gm element or resistance element connected between at least one of the connection points of the resistance element in the first filter and the output terminal of the operational amplifier is added to the oversampling A / D converter. The filtering characteristic having a zero point in the transmission characteristic of the quantization noise is exhibited.
 本発明によると、小型かつ低消費電力のn次積分器及びn次共振器を得ることができる。さらに、高分解能かつ高SN比のオーバーサンプリングA/D変換器の小型化及び低消費電力化が可能となる。 According to the present invention, a small and low power consumption n-order integrator and n-order resonator can be obtained. Furthermore, it is possible to reduce the size and power consumption of the oversampling A / D converter with high resolution and high S / N ratio.
図1は、第1の実施形態に係る積分器の構成図である。FIG. 1 is a configuration diagram of an integrator according to the first embodiment. 図2は、第2の実施形態に係る積分器の構成図である。FIG. 2 is a configuration diagram of an integrator according to the second embodiment. 図3は、第3の実施形態に係る積分器の構成図である。FIG. 3 is a configuration diagram of an integrator according to the third embodiment. 図4は、第4の実施形態に係るオーバーサンプリングA/D変換器の構成図である。FIG. 4 is a configuration diagram of an oversampling A / D converter according to the fourth embodiment. 図5は、第5の実施形態に係るオーバーサンプリングA/D変換器の構成図である。FIG. 5 is a configuration diagram of an oversampling A / D converter according to the fifth embodiment. 図6は、第6の実施形態に係るオーバーサンプリングA/D変換器の構成図である。FIG. 6 is a configuration diagram of an oversampling A / D converter according to the sixth embodiment. 図7は、図6に示した本発明に係る共振器の過渡応答のシミュレーション結果を示すグラフである。FIG. 7 is a graph showing a simulation result of the transient response of the resonator according to the present invention shown in FIG. 図8は、第7の実施形態に係るオーバーサンプリングA/D変換器の構成図である。FIG. 8 is a configuration diagram of an oversampling A / D converter according to the seventh embodiment. 図9は、図8に示した本発明に係る共振器の過渡応答のシミュレーション結果を示すグラフである。FIG. 9 is a graph showing a simulation result of the transient response of the resonator according to the present invention shown in FIG. 図10は、第8の実施形態に係るオーバーサンプリングA/D変換器の構成図である。FIG. 10 is a configuration diagram of an oversampling A / D converter according to the eighth embodiment. 図11は、第9の実施形態に係るオーバーサンプリングA/D変換器の構成図である。FIG. 11 is a configuration diagram of an oversampling A / D converter according to the ninth embodiment.
符号の説明Explanation of symbols
10  積分器
10A、10A’ 共振器
11  演算増幅器
12  フィルタ(第1のフィルタ)
121 抵抗素子
122 容量素子
13  フィルタ(第2のフィルタ)
131 容量素子
132 抵抗素子
14  フィルタ(第3のフィルタ)
141 抵抗素子
142 容量素子
15  Gm素子
16  抵抗素子
20  量子化器
30  D/A変換器
40  D/A変換器
10 integrator 10A, 10A 'resonator 11 operational amplifier 12 filter (first filter)
121 Resistance element 122 Capacitance element 13 Filter (second filter)
131 Capacitance element 132 Resistance element 14 Filter (third filter)
141 Resistance element 142 Capacitance element 15 Gm element 16 Resistance element 20 Quantizer 30 D / A converter 40 D / A converter
 以下、本発明を実施するための最良の形態について、図面を参照しながら説明する。 Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings.
 (第1の実施形態)
 図1は、第1の実施形態に係る積分器の構成を示す。当該積分器10は、演算増幅器11、演算増幅器11の反転入力端に接続されたフィルタ12、及び演算増幅器11の反転入力端と出力端との間に接続されたフィルタ13を備えている。フィルタ12は、直列接続された2個の抵抗素子121、及び一端がこれら抵抗素子の接続点に接続され、他端が接地された容量素子122を備えた2次ローパスフィルタである。フィルタ13は、直列接続された2個の容量素子131、及び一端がこれら容量素子の接続点に接続され、他端が接地された抵抗素子132を備えた2次ハイパスフィルタである。
(First embodiment)
FIG. 1 shows a configuration of an integrator according to the first embodiment. The integrator 10 includes an operational amplifier 11, a filter 12 connected to the inverting input terminal of the operational amplifier 11, and a filter 13 connected between the inverting input terminal and the output terminal of the operational amplifier 11. The filter 12 is a secondary low-pass filter including two resistance elements 121 connected in series, and a capacitance element 122 having one end connected to a connection point of these resistance elements and the other end grounded. The filter 13 is a secondary high-pass filter including two capacitive elements 131 connected in series, and a resistive element 132 having one end connected to a connection point of these capacitive elements and the other end grounded.
 積分器10において、入力電圧をVin、出力電圧をVout、抵抗素子121の抵抗値をR、容量素子122の容量値をC、抵抗素子132の抵抗値をR、抵抗素子121と容量素子122との接続点の電圧をV、及び容量素子131と抵抗素子132との接続点の電圧をVとすると、次の節点方程式が導出される。ただし、sはラプラス演算子である。 In the integrator 10, the input voltage is V in , the output voltage is V out , the resistance value of the resistance element 121 is R 1 , the capacitance value of the capacitance element 122 is C 1 , the resistance value of the resistance element 132 is R 2 , and the resistance element 121. When the voltage at the connection point between the capacitor element 122 and the capacitor element 122 is V 1 , and the voltage at the connection point between the capacitor element 131 and the resistor element 132 is V 2 , the following nodal equation is derived. Here, s is a Laplace operator.
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001
 この節点方程式を解くと積分器10の伝達関数が次式のように導出される。 When the nodal equation is solved, the transfer function of the integrator 10 is derived as follows.
Figure JPOXMLDOC01-appb-M000002
Figure JPOXMLDOC01-appb-M000002
 ここで、C=4Cが成り立つとき、次の伝達関数が導出される。 Here, when C 1 R 1 = 4C 2 R 2 holds, the following transfer function is derived.
Figure JPOXMLDOC01-appb-M000003
Figure JPOXMLDOC01-appb-M000003
 すなわち、抵抗素子121及び132並びに容量素子122及び131の各素子値を適宜設定することで1/sの項のみからなる伝達関数を得ることができる。このように、本実施形態によると、1個の演算増幅器11で2次積分器を構成することができる。なお、本実施形態に係る積分器10を多重化することで4次以上の積分器を構成することができる。例えば、本実施形態に係る積分器10を2個多重化することで、2個の演算増幅器11で4次積分器を構成することができる。 That is, by appropriately setting the element values of the resistance elements 121 and 132 and the capacitance elements 122 and 131, a transfer function consisting only of the 1 / s 2 term can be obtained. Thus, according to the present embodiment, a single-stage operational amplifier 11 can constitute a secondary integrator. Note that a fourth-order or higher order integrator can be configured by multiplexing the integrators 10 according to the present embodiment. For example, by multiplexing two integrators 10 according to this embodiment, a four-order integrator can be configured with two operational amplifiers 11.
 (第2の実施形態)
 図2は、第2の実施形態に係る積分器の構成を示す。当該積分器10は、図1の積分器10とは異なる構成のフィルタ12及び13を備えている。すなわち、フィルタ12は、直列接続された3個以上の抵抗素子121、及び一端がこれら抵抗素子の各接続点に接続され、他端が接地され、抵抗素子121よりも1個少ない容量素子122を備えたn次ローパスフィルタである。フィルタ13は、直列接続された3個以上の容量素子131、及び一端がこれら容量素子の各接続点に接続され、他端が接地され、容量素子131よりも1個少ない抵抗素子132を備えたn次ハイパスフィルタである。
(Second Embodiment)
FIG. 2 shows a configuration of an integrator according to the second embodiment. The integrator 10 includes filters 12 and 13 having a configuration different from that of the integrator 10 of FIG. That is, the filter 12 includes three or more resistance elements 121 connected in series, one end connected to each connection point of these resistance elements, the other end grounded, and one capacitive element 122 less than the resistance element 121. An n-order low-pass filter provided. The filter 13 includes three or more capacitive elements 131 connected in series, one end connected to each connection point of these capacitive elements, the other end grounded, and one less resistive element 132 than the capacitive element 131. It is an nth order high pass filter.
 抵抗素子121及び容量素子131の個数をnとすると当該積分器10の伝達関数は一般に次式で表される。ただし、α、β、γ、τ、κは抵抗素子121及び132並びに容量素子122及び131の各素子値によって決まる定数である。 When the number of resistance elements 121 and capacitive elements 131 is n, the transfer function of the integrator 10 is generally expressed by the following equation. However, α, β, γ, τ, and κ are constants determined by the element values of the resistance elements 121 and 132 and the capacitance elements 122 and 131.
Figure JPOXMLDOC01-appb-M000004
Figure JPOXMLDOC01-appb-M000004
 ここで、抵抗素子121及び132並びに容量素子122及び131の各素子値について所定の関係が成り立つようにすることで、上記の伝達関数の分母及び分子においてsからsn-1までの項が打ち消されて1/sの項のみからなる伝達関数が得られる。このように、本実施形態によると、1個の演算増幅器でn次積分器を構成することができる。 Here, by establishing a predetermined relationship between the element values of the resistance elements 121 and 132 and the capacitance elements 122 and 131, the terms from s to s n−1 are canceled in the denominator and numerator of the transfer function. Thus, a transfer function consisting only of 1 / s n terms is obtained. Thus, according to the present embodiment, an n-order integrator can be configured with one operational amplifier.
 なお、上記の各実施形態において、フィルタ12における二つの抵抗素子121は互いに異なる抵抗値であってもよい。また、フィルタ13における二つの容量素子131もまた互いに異なる抵抗値であってもよい。いずれの場合でも、抵抗素子121及び132並びに容量素子122及び131の各素子値について所定の関係が成り立つようにすることで2次以上の積分器10を構成することができる。 In each of the above embodiments, the two resistance elements 121 in the filter 12 may have different resistance values. The two capacitive elements 131 in the filter 13 may also have different resistance values. In any case, the second-order or higher-order integrator 10 can be configured by satisfying a predetermined relationship between the element values of the resistance elements 121 and 132 and the capacitance elements 122 and 131.
 (第3の実施形態)
 図3は、第3の実施形態に係る積分器の構成を示す。当該積分器10は、図1又は図2の積分器10にフィルタ14を追加したものである。フィルタ14は、フィルタ12に並列接続された抵抗素子141及び容量素子142を備えている。フィルタ14は積分器10の入力と演算増幅器11の反転入力端との間でフィードフォワードパスとして作用する。これにより、積分器10の出力に、n次積分成分に加えて0次、1次及び2次の積分成分を生じさせることができる。各次数の積分成分は、抵抗素子141及び容量素子142の素子値を適宜設定することで調整可能である。
(Third embodiment)
FIG. 3 shows a configuration of an integrator according to the third embodiment. The integrator 10 is obtained by adding a filter 14 to the integrator 10 of FIG. 1 or FIG. The filter 14 includes a resistance element 141 and a capacitance element 142 connected in parallel to the filter 12. The filter 14 acts as a feedforward path between the input of the integrator 10 and the inverting input terminal of the operational amplifier 11. As a result, in addition to the nth-order integral component, zeroth-order, first-order and second-order integral components can be generated in the output of the integrator 10. The integral component of each order can be adjusted by appropriately setting the element values of the resistor element 141 and the capacitor element 142.
 なお、抵抗素子141及び容量素子142のいずれか一方を省略してもよい。例えば、フィルタ14を抵抗素子141のみで構成した場合、積分器10の出力に、n次積分成分に加えて1次の積分成分を生じさせることができる。フィルタ14を容量素子142のみで構成した場合、積分器10の出力に0次及び1次の積分成分を生じさせることができる。 Note that either one of the resistor element 141 and the capacitor element 142 may be omitted. For example, when the filter 14 is composed of only the resistance element 141, a first-order integral component can be generated in the output of the integrator 10 in addition to the n-order integral component. When the filter 14 is composed of only the capacitive element 142, zero-order and first-order integral components can be generated at the output of the integrator 10.
 (第4の実施形態)
 図4は、第4の実施形態に係るCSDS-ADCの構成を示す。本実施形態に係るCTDS-ADCは、図1の積分器10、積分器10の出力を量子化する量子化器20、量子化器20のデジタル出力を電流信号に変換してフィルタ12における抵抗素子121の接続点にフィードバックするD/A変換器30、量子化器20のデジタル出力を電流信号に変換してフィルタ13における容量素子131の接続点にフィードバックするD/A変換器40を備えている。ここで、D/A変換器30の出力電流をI、D/A変換器40の出力電流をIとすると、次の節点方程式が導出される。
(Fourth embodiment)
FIG. 4 shows the configuration of a CSDS-ADC according to the fourth embodiment. The CTDS-ADC according to the present embodiment includes an integrator 10 in FIG. 1, a quantizer 20 that quantizes the output of the integrator 10, a digital output of the quantizer 20 into a current signal, and a resistive element in the filter 12. A D / A converter 30 that feeds back to a connection point 121 and a D / A converter 40 that converts the digital output of the quantizer 20 into a current signal and feeds back to the connection point of the capacitive element 131 in the filter 13 are provided. . Here, when the output current of the D / A converter 30 is I 1 and the output current of the D / A converter 40 is I 2 , the following nodal equation is derived.
Figure JPOXMLDOC01-appb-M000005
Figure JPOXMLDOC01-appb-M000005
 この節点方程式を解くと積分器10の出力電圧Voutと電流Iとの関係が次式のように導出される。 This relationship of solving the nodal equation and the output voltage V out and the current I 1 of the integrator 10 is derived as follows.
Figure JPOXMLDOC01-appb-M000006
Figure JPOXMLDOC01-appb-M000006
 ここで、C=4Cが成り立つとき、次の関係式が導出される。 Here, when C 1 R 1 = 4C 2 R 2 holds, the following relational expression is derived.
Figure JPOXMLDOC01-appb-M000007
Figure JPOXMLDOC01-appb-M000007
 また、詳細な計算過程は省略するが、積分器10の出力電圧Voutと電流Iとの関係が次式のように導出される。 Also, detailed calculation process is omitted, the relationship between the output voltage V out and the current I 2 of the integrator 10 is derived as follows.
Figure JPOXMLDOC01-appb-M000008
Figure JPOXMLDOC01-appb-M000008
 すなわち、抵抗素子121及び132並びに容量素子122及び131の各素子値を適宜設定することで、D/A変換器30の出力をフィルタ12における抵抗素子121の接続点にフィードバックして2次積分操作を行うことができる。また、D/A変換器40の出力をフィルタ13における容量素子131の接続点にフィードバックして1次積分操作を行うことができる。このように、本実施形態によると、1個の演算増幅器11で2次フィルタリング特性(量子化ノイズ除去特性)を有するオーバーサンプリングA/D変換器を構成することができる。なお、積分器10を多重化することで4次以上のフィルタリング特性を発揮するオーバーサンプリングA/D変換器を構成することができる。例えば、積分器10を2個多重化することで、2個の演算増幅器11で4次フィルタリング特性を発揮するオーバーサンプリングA/D変換器を構成することができる。 That is, by appropriately setting the element values of the resistance elements 121 and 132 and the capacitance elements 122 and 131, the output of the D / A converter 30 is fed back to the connection point of the resistance element 121 in the filter 12 to perform the second-order integration operation. It can be performed. Further, the output of the D / A converter 40 can be fed back to the connection point of the capacitive element 131 in the filter 13 to perform the first order integration operation. Thus, according to the present embodiment, an oversampling A / D converter having secondary filtering characteristics (quantization noise elimination characteristics) can be configured with one operational amplifier 11. An oversampling A / D converter that exhibits fourth-order or higher filtering characteristics can be configured by multiplexing the integrator 10. For example, by multiplexing two integrators 10, an oversampling A / D converter that exhibits fourth-order filtering characteristics can be configured with two operational amplifiers 11.
 (第5の実施形態)
 図5は、第5の実施形態に係るCSDS-ADCの構成を示す。本実施形態に係るCTDS-ADCは、図2の積分器10、積分器10の出力を量子化する量子化器20、量子化器20のデジタル出力を電流信号に変換してフィルタ12における抵抗素子121の各接続点にフィードバックする複数のD/A変換器30、量子化器20のデジタル出力を電流信号に変換してフィルタ13における容量素子131の各接続点にフィードバックする複数のD/A変換器40を備えている。上述したように、抵抗素子121及び132並びに容量素子122及び131の各素子値について所定の関係が成り立つようにすることで、積分器10はn次積分特性を発揮するようになる。このように、本実施形態によると、1個の演算増幅器11でn次フィルタリング特性を発揮するオーバーサンプリングA/D変換器を構成することができる。
(Fifth embodiment)
FIG. 5 shows a configuration of a CSDS-ADC according to the fifth embodiment. The CTDS-ADC according to the present embodiment includes an integrator 10 in FIG. 2, a quantizer 20 that quantizes the output of the integrator 10, a digital output of the quantizer 20 into a current signal, and a resistive element in the filter 12. A plurality of D / A converters 30 that feed back to each connection point 121 and a plurality of D / A conversions that convert the digital output of the quantizer 20 into a current signal and feed back to each connection point of the capacitive element 131 in the filter 13. A container 40 is provided. As described above, the integrator 10 exhibits the n-th order integration characteristic by satisfying a predetermined relationship between the element values of the resistance elements 121 and 132 and the capacitance elements 122 and 131. Thus, according to the present embodiment, an oversampling A / D converter that exhibits n-th order filtering characteristics can be configured with one operational amplifier 11.
 (第6の実施形態)
 図6は、第6の実施形態に係るCTDS-ADCの構成を示す。本実施形態に係るCTDS-ADCは、一般的な1次積分器10’及び2次共振器10A及び10A’を備えており、全体として5次フィルタリング特性を発揮する。なお、図6において、各素子の傍らに示した記号は各素子値を表している。共振器10A及び10A’は、図1の積分器10にGm素子(トランスコンダクタ素子)15を追加したものである。Gm素子15は、演算増幅器11の出力を、フィルタ12における抵抗素子の接続点にフィードバックする。
(Sixth embodiment)
FIG. 6 shows a configuration of a CTDS-ADC according to the sixth embodiment. The CTDS-ADC according to the present embodiment includes a general primary integrator 10 ′ and secondary resonators 10A and 10A ′, and exhibits a fifth-order filtering characteristic as a whole. In FIG. 6, symbols shown beside each element represent each element value. The resonators 10A and 10A ′ are obtained by adding a Gm element (transconductor element) 15 to the integrator 10 of FIG. The Gm element 15 feeds back the output of the operational amplifier 11 to the connection point of the resistance element in the filter 12.
 図7は、図6に示した共振器10Aに共振周波数近傍の5MHzの正弦波を入力したときの共振器10Aの過渡応答のシミュレーション結果を示す。ただし、演算増幅器11のゲインは70dB、GBWは200MHzである。このシミュレーション結果から、共振器10Aは発振しないことがわかる。 FIG. 7 shows a simulation result of the transient response of the resonator 10A when a 5 MHz sine wave near the resonance frequency is input to the resonator 10A shown in FIG. However, the gain of the operational amplifier 11 is 70 dB, and GBW is 200 MHz. From this simulation result, it can be seen that the resonator 10A does not oscillate.
 (第7の実施形態)
 図8は、第7の実施形態に係るCTDS-ADCの構成を示す。本実施形態に係るCTDS-ADCは、図6のCTDS-ADCにおいて、共振器10A及び10A’におけるGm素子15を抵抗素子16に置き換えたものである。
(Seventh embodiment)
FIG. 8 shows a configuration of a CTDS-ADC according to the seventh embodiment. The CTDS-ADC according to this embodiment is obtained by replacing the Gm element 15 in the resonators 10A and 10A ′ with a resistance element 16 in the CTDS-ADC of FIG.
 図9は、図8に示した共振器10Aに共振周波数近傍の5MHzの正弦波を入力したときの共振器10Aの過渡応答のシミュレーション結果を示す。ただし、演算増幅器11のゲインは70dB、GBWは200MHzである。このシミュレーション結果から、共振器10Aは発振しないことがわかる。さらに、図7のグラフと比較すると、第6の実施形態に係る共振器10Aよりも本実施形態に係る共振器10Aの方が過渡応答特性がよいことがわかる。 FIG. 9 shows a simulation result of the transient response of the resonator 10A when a 5 MHz sine wave near the resonance frequency is input to the resonator 10A shown in FIG. However, the gain of the operational amplifier 11 is 70 dB, and GBW is 200 MHz. From this simulation result, it can be seen that the resonator 10A does not oscillate. Furthermore, when compared with the graph of FIG. 7, it can be seen that the resonator 10A according to the present embodiment has better transient response characteristics than the resonator 10A according to the sixth embodiment.
 (第8の実施形態)
 図10は、第8の実施形態に係るCTDS-ADCの構成を示す。本実施形態に係るCTDS-ADCは、一般的な1次積分器10’及び3次共振器10Aを備えており、全体として4次フィルタリング特性を発揮する。
(Eighth embodiment)
FIG. 10 shows a configuration of a CTDS-ADC according to the eighth embodiment. The CTDS-ADC according to the present embodiment includes a general first-order integrator 10 ′ and a third-order resonator 10A, and exhibits a fourth-order filtering characteristic as a whole.
 共振器10Aは、図2の積分器10に3個のGm素子15を追加したものである。各Gm素子15は、演算増幅器11の出力を、フィルタ12における抵抗素子の各接続点にフィードバックする。図5のCTDS-ADCと同様に、フィルタ12における抵抗素子の各接続点には3個のD/A変換器30のそれぞれの出力がフィードバックされる。一方、図5のCTDS-ADCとは異なり、D/A変換器40の出力はフィルタ13における容量素子の各接続点ではなく演算増幅器11の反転入力端にフィードバックされる。このように、本実施形態によると、D/A変換器の総数が比較的少なくて済み、回路規模及び消費電力を低減することができる。 The resonator 10A is obtained by adding three Gm elements 15 to the integrator 10 of FIG. Each Gm element 15 feeds back the output of the operational amplifier 11 to each connection point of the resistance element in the filter 12. Similarly to the CTDS-ADC in FIG. 5, the outputs of the three D / A converters 30 are fed back to the connection points of the resistive elements in the filter 12. On the other hand, unlike the CTDS-ADC of FIG. 5, the output of the D / A converter 40 is fed back to the inverting input terminal of the operational amplifier 11 instead of the connection points of the capacitive elements in the filter 13. Thus, according to this embodiment, the total number of D / A converters can be relatively small, and the circuit scale and power consumption can be reduced.
 なお、Gm素子15を抵抗素子に置換してもよい。また、フィルタ12における抵抗素子のすべての接続点にGm素子15又は抵抗素子を接続する必要はない。すなわち、フィルタ12における抵抗素子の少なくとも一つの接続点に演算増幅器11の出力をGm素子又は抵抗素子を介してフィードバックすることで共振器が構成可能である。 The Gm element 15 may be replaced with a resistance element. Further, it is not necessary to connect the Gm element 15 or the resistance element to all connection points of the resistance element in the filter 12. That is, a resonator can be configured by feeding back the output of the operational amplifier 11 to at least one connection point of the resistive element in the filter 12 via the Gm element or the resistive element.
 (第9の実施形態)
 図11は、第9の実施形態に係るCTDS-ADCの構成を示す。本実施形態に係るCTDS-ADCは、一般的な1次積分器10’及び2次共振器10Aを備えており、全体として3次フィルタリング特性を発揮する。共振器10Aは、図3の積分器10に、演算増幅器11の出力をフィルタ12における抵抗素子の接続点にフィードバックする抵抗素子16を追加したものである。
(Ninth embodiment)
FIG. 11 shows the configuration of a CTDS-ADC according to the ninth embodiment. The CTDS-ADC according to the present embodiment includes a general first-order integrator 10 ′ and a second-order resonator 10A, and exhibits a third-order filtering characteristic as a whole. The resonator 10 </ b> A is obtained by adding a resistance element 16 that feeds back the output of the operational amplifier 11 to the connection point of the resistance element in the filter 12 to the integrator 10 of FIG. 3.
 共振器10Aにおいてフィルタ14は共振器10Aの入力と演算増幅器11の反転入力端との間でフィードフォワードパスとして作用する。このため、フィルタ12における抵抗素子の接続点に量子化器20の出力をフィードバックしなくとも当該CTDS-ADCの位相補償が可能となる。したがって、本実施形態によると、D/A変換器をより一層削減することができ、回路規模及び消費電力のさらなる低減が可能となる。 In the resonator 10A, the filter 14 acts as a feedforward path between the input of the resonator 10A and the inverting input terminal of the operational amplifier 11. Therefore, the phase compensation of the CTDS-ADC can be performed without feeding back the output of the quantizer 20 to the connection point of the resistive element in the filter 12. Therefore, according to this embodiment, the number of D / A converters can be further reduced, and the circuit scale and power consumption can be further reduced.
 なお、抵抗素子16をGm素子に置換してもよい。また、抵抗素子16を省略してもよい。その場合のCTDS-ADCは、量子化ノイズの伝達特性に零点を持たないフィルタリング特性を発揮することとなる。 The resistance element 16 may be replaced with a Gm element. Further, the resistance element 16 may be omitted. In this case, the CTDS-ADC exhibits a filtering characteristic having no zero point in the transmission characteristic of the quantization noise.
 また、上記の各実施形態において、各抵抗素子をスイッチトキャパシタ回路で構成してもよい。これにより、積分器10及び共振器10A、10A’を離散型フィルタにすることができる。離散型フィルタは容量比で回路の伝達関数を決定することができるため、フィルタリング精度を向上させることができる。 In each of the above embodiments, each resistance element may be configured with a switched capacitor circuit. Thereby, the integrator 10 and the resonators 10A and 10A 'can be made into discrete filters. Since the discrete filter can determine the transfer function of the circuit by the capacitance ratio, the filtering accuracy can be improved.
 本発明に係る積分器、共振器及びオーバーサンプリングA/D変換器は、比較的小規模かつ低消費電力で高次の積分特性及びフィルタリング特性を発揮するため、携帯通信機器などに有用である。 The integrator, the resonator, and the oversampling A / D converter according to the present invention exhibit high-order integration characteristics and filtering characteristics with a relatively small scale and low power consumption, and thus are useful for portable communication devices and the like.

Claims (8)

  1.  演算増幅器と、
     前記演算増幅器の反転入力端に接続された第1のフィルタと、
     前記演算増幅器の反転入力端と出力端との間に接続された第2のフィルタとを備え、
     前記第1のフィルタは、nを2以上の整数として、
      直列接続されたn個の抵抗素子と、
      一端が前記抵抗素子の各接続点に接続され、他端が接地されたn-1個の容量素子とを有するものであり、
     前記第2のフィルタは、
      直列接続されたn個の容量素子と、
      一端が前記容量素子の各接続点に接続され、他端が接地されたn-1個の抵抗素子とを有するものである
    ことを特徴とする積分器。
    An operational amplifier;
    A first filter connected to the inverting input of the operational amplifier;
    A second filter connected between an inverting input terminal and an output terminal of the operational amplifier;
    In the first filter, n is an integer of 2 or more,
    N resistance elements connected in series;
    N-1 capacitance elements having one end connected to each connection point of the resistance element and the other end grounded,
    The second filter is:
    N capacitive elements connected in series;
    An integrator having n-1 resistance elements, one end of which is connected to each connection point of the capacitor and the other end of which is grounded.
  2. 請求項1の積分器において、
     前記第1のフィルタに並列接続された抵抗素子及び容量素子の少なくとも一つを有する第3のフィルタを備えている
    ことを特徴とする積分器。
    The integrator of claim 1, wherein
    An integrator comprising a third filter having at least one of a resistance element and a capacitance element connected in parallel to the first filter.
  3. 請求項1及び2のいずれかの積分器において、
     前記抵抗素子は、いずれも、スイッチトキャパシタ回路である
    ことを特徴とする積分器。
    The integrator of any of claims 1 and 2,
    The integrator is characterized in that each of the resistance elements is a switched capacitor circuit.
  4.  請求項1から3のいずれか一つの積分器と、
     前記第1のフィルタにおける前記抵抗素子の接続点の少なくとも一つと前記演算増幅器の出力端との間に接続された少なくとも一つのGm素子又は抵抗素子とを備えている
    ことを特徴とする共振器。
    An integrator according to any one of claims 1 to 3;
    A resonator comprising: at least one Gm element or a resistance element connected between at least one of connection points of the resistance element in the first filter and an output terminal of the operational amplifier.
  5.  請求項1の積分器と、
     前記積分器の出力を量子化する量子化器と、
     前記量子化器のデジタル出力を電流信号に変換して前記第1のフィルタにおける前記抵抗素子の各接続点にフィードバックするn-1個のD/A変換器と、
     前記量子化器のデジタル出力を電流信号に変換して前記第2のフィルタにおける前記容量素子の各接続点にフィードバックするn-1個のD/A変換器とを備えている
    ことを特徴とするオーバーサンプリングA/D変換器。
    An integrator according to claim 1;
    A quantizer for quantizing the output of the integrator;
    N-1 D / A converters that convert a digital output of the quantizer into a current signal and feed back to each connection point of the resistance element in the first filter;
    And n-1 D / A converters for converting the digital output of the quantizer into a current signal and feeding back to each connection point of the capacitive element in the second filter. Oversampling A / D converter.
  6.  請求項1の積分器と、
     前記積分器の出力を量子化する量子化器と、
     前記量子化器のデジタル出力を電流信号に変換して前記第1のフィルタにおける前記抵抗素子の各接続点にフィードバックするn-1個のD/A変換器と、
     前記量子化器のデジタル出力を電流信号に変換して前記演算増幅器の反転入力端にフィードバックするD/A変換器とを備えている
    ことを特徴とするオーバーサンプリングA/D変換器。
    An integrator according to claim 1;
    A quantizer for quantizing the output of the integrator;
    N-1 D / A converters that convert a digital output of the quantizer into a current signal and feed back to each connection point of the resistance element in the first filter;
    An oversampling A / D converter comprising: a D / A converter that converts a digital output of the quantizer into a current signal and feeds it back to an inverting input terminal of the operational amplifier.
  7.  請求項2の積分器と、
     前記積分器の出力を量子化する量子化器と、
     前記量子化器のデジタル出力を電流信号に変換して前記積分器の入力側にフィードバックするD/A変換器とを備えている
    ことを特徴とするオーバーサンプリングA/D変換器。
    An integrator according to claim 2;
    A quantizer for quantizing the output of the integrator;
    An oversampling A / D converter comprising: a D / A converter that converts a digital output of the quantizer into a current signal and feeds it back to an input side of the integrator.
  8. 請求項5から7のいずれか一つのオーバーサンプリングA/D変換器において、
     前記第1のフィルタにおける前記抵抗素子の接続点の少なくとも一つと前記演算増幅器の出力端との間に接続された少なくとも一つのGm素子又は抵抗素子を備えている
    ことを特徴とするオーバーサンプリングA/D変換器。
    The oversampling A / D converter according to any one of claims 5 to 7,
    The oversampling A /, comprising: at least one Gm element or a resistance element connected between at least one of the connection points of the resistance element in the first filter and an output terminal of the operational amplifier. D converter.
PCT/JP2009/001162 2008-04-28 2009-03-16 Integrator, resonator, and oversampling a/d converter WO2009133653A1 (en)

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