KR100933280B1 - Time Interleaved Sigma-Delta Modulator Using a Single Amplifier Architecture - Google Patents

Abstract

The present invention relates to a time interleaved sigma-delta modulator that maintains an existing transfer function with one amplifier per stage using a single amplifier architecture. The present invention provides a sigma-delta modulator comprising: a summation unit configured to sum-amplify a signal obtained by adding an externally input signal, a quantized signal fed back, and a signal fed back without quantization; At least one integrator which delays the signal output by the adder by a predetermined clock, multiplies by a predetermined coefficient, adds the input value, and provides the added signal as a signal fed back to the adder without quantization; A quantizer for quantizing the signal output by the adder; And a clock delay unit for delaying a signal outputted by the quantization unit and providing the signal as a signal which is quantized and fed back to the time interleaved sigma-delta modulator. According to the present invention, a high dynamic range modulator can be realized by increasing the effective sampling frequency, while the volume is greatly reduced, and a low power design can be realized.

Sigma-delta modulator, time-interleaved, A / D converter, low-pass, band-pass, single amplifier architecture

Description

Time-interleaved sigma-delta modulator using single amplifier architecture

The present invention relates to a time interleaved sigma-delta modulator implemented with a time interleaved structure. More specifically, it relates to a time interleaved sigma-delta modulator that uses a single amplifier architecture to maintain an existing transfer function with one amplifier per stage.

Most digital-analog composite devices have an analog-to-digital modulator (A / D modulator) or / and a digital-analog modulator (D / A modulator) for mutual conversion of digital and analog signals. Among them, an analog-digital modulator is a device for converting an analog signal into a digital signal, and has a structure of sampling an analog signal at high speed and integrating the sampled value again. Analog-to-digital modulators also use differential amplifier circuits to minimize the effects of external noise.

Recently, as the demand for digital communication networks and high-quality digital audio systems has exploded, the field of application of analog-digital modulators is gradually expanding. Accordingly, there is a need for analog-digital modulators to deal with many solutions, such as miniaturization, low power, frequency widening, and high precision. The use of sigma-delta modulators can solve this problem by adopting sigma-delta modulators, and the use of sigma-delta modulators is increasing day by day.

However, among the sigma-delta modulators, in particular, the time interleaved sigma-delta modulator is constituted by a plurality of blocks having different phases of clock frequencies. As a result, the clock frequency is smaller than that of a general sigma-delta modulator configured by a single block, and thus, it can be utilized even in a high IF (Intermediate Frequency) frequency band. Hereinafter, a time interleaved sigma-delta modulator will be described with reference to FIG. 1.

Referring to (a) and (b) of FIG. 1, the time interleaved sigma-delta modulator constitutes a plurality of blocks having different phases of clock frequencies during driving, that is, STAGE 1 to STAGE 5 in the case of (a) of FIG. 1. . The time interleaved sigma-delta modulator reduces the clock frequency and settling time with this configuration and obtains an effective sampling frequency that is not feasible with conventional switched capacitor circuits. In addition, the time interleaved sigma-delta modulator produces the effect of reducing the power consumed by each amplifier provided by lowering the slew rate.

However, the time interleaved sigma-delta modulator has an excessive number of mounted amplifiers due to the requirement that the amplifier is multiplied by the order and the number of stages, and thus the power consumed is very large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object thereof is to provide a time interleaved sigma-delta modulator to which a single amplifier architecture is applied.

The present invention has been made to achieve the above object, the sigma-delta modulator comprising: a summation unit for adding and amplifying a signal obtained by adding a signal input from the outside, a signal to be fed back after quantization and a signal to be fed back without quantization; At least one integrator for delaying the signal output by the adder by a predetermined clock, multiplying by a predetermined coefficient, adding the input value, and providing the input signal to the adder without being quantized; A quantizer for quantizing the signal output by the adder; And a clock delay unit delaying the signal outputted by the quantization unit and providing the delayed signal as the quantized and fed back signal.

(여기에서, N은 상기 타임 인터리브 시그마-델타 변조기의 차수)만큼 지연시킨다.Preferably, the number of integrators is formed equal to the order of the time interleaved sigma-delta modulator, and the integrators are configured in parallel. Preferably, the constant coefficient used by the integral part when multiplying is (-1) ^{k + 1} _n C _k (where n is the order of the time interleaved sigma-delta modulator and k is the corresponding order of the integral part). Derived from Preferably, the clock delay unit outputs a signal output from the quantization unit.

Where N is the order of the time interleaved sigma-delta modulator.

Preferably, a 1-delay (Z ⁻¹ ) is provided in a path from the summing unit to the quantization unit or a path from the quantization unit to the clock delay unit. More preferably, when a 1-delay is provided in the path from the summing unit to the quantization unit, the signal delayed by the integral unit by a predetermined clock is input at another stage, and the value is input in the N-k + 1 stage. UZ ^-k , where U is the output of the summation, N is the order of the time interleaved sigma-delta modulator, k is the corresponding order of the integrator. Alternatively, when a 1-delay is provided on the path from the quantization unit to the clock delay unit, the signal delayed by the integral unit by a predetermined clock is input at another stage, and the value is UZ ^-k in the Nk stage (where , U is the output of the summation, N is the order of the time interleaved sigma-delta modulator, k is the corresponding order of the integrator. Even more preferably, when a 1-delay is provided on the path from the quantization unit to the clock delay unit, the integrator which finally receives the signal output by the adder includes an N-delay (Z- ^N ).

Preferably, the time interleaved sigma-delta modulator is formed in a low pass form or a band pass form. More preferably, the time interleaved sigma-delta modulator is implemented in an odd pass when in the form of a bandpass.

Typical time interleaved sigma-delta modulators are bulky due to the use of many amplifiers and consume too much power. The time interleaved sigma-delta modulator according to the present invention is constructed using a single amplifier architecture, which enables a high dynamic range modulator by increasing the effective sampling frequency, while significantly reducing the volume occupied and enabling low power design.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are used as much as possible even if displayed on different drawings. In addition, in describing the present invention, when it is determined that the detailed description of the related known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted. In addition, the following will describe a preferred embodiment of the present invention, but the technical idea of the present invention is not limited thereto and may be variously modified and modified by those skilled in the art.

2 is a conceptual block diagram illustrating an internal configuration of a time interleaved sigma-delta modulator applying a single amplifier architecture according to a first preferred embodiment of the present invention. 3 is a conceptual block diagram illustrating an internal configuration of a time interleaved sigma-delta modulator applying a single amplifier architecture according to a second exemplary embodiment of the present invention. 2 and 3, the time interleaved sigma-delta modulator 200 according to the preferred embodiment of the present invention includes an adder 210, an integrator 215, and a quantizer 220. ) And a clock delay unit 225.

The time interleaved sigma-delta modulator 200 has one or more integrators 215 configured in parallel in embodiments of the present invention. Accordingly, even if only one amplifier (not shown) is designed in the adder 210 in the time interleaved sigma-delta modulator 200, it is possible to maintain a transfer function value in the case of the conventional time interleaved sigma-delta modulator. The position in which the amplifier is designed in the adder 210 may be variously implemented according to a purpose or a characteristic, and the present invention will not be described with reference to an embodiment.

Meanwhile, in the embodiment of the present invention, the number of the integrators 215 depends on the order. For example, when the time interleaved sigma-delta modulator 200 is Nth order, the number of integrators 215 is set to n.

In the embodiment of the present invention, the adder 210 receives three types of input signals and adds and amplifies them. Here, the three types of input signals received by the adder 210 refer to signals input through the input terminal 230, unquantized signals, and quantized signals.

Integrator 215 multiplies the delay signal input from the stage using the clock with a different phase by a predetermined coefficient in the embodiment of the present invention, and serves to add it. Integrator 215 includes a counter 217 and an adder 218 to perform this role. In the present invention, the integrator 215 is provided in the time interleaved sigma-delta modulator 200 by the order, and configured in parallel, and all of the values derived by the integrator 215 are summed as a signal that is not quantized. It is input to the adder 210.

The delay value of the delay signal varies depending on the acting stage, which can be expressed by the relation "Z ^-k (at stage Nk)".

In this case, however, the first integrator located at the top receives a delay signal from a stage using a different clock. On the other hand, as shown in FIG. 3, it is also possible that the first integrator does not receive a delay signal from a stage using a clock having a different phase. In this case, the first integrator receives a delay signal from the 1-delay Z- ¹ , and the 1-delay is installed on the path from the adder 210 to the quantizer 220. On the other hand, other integrator 215 except for the first integrator receives a delay signal from a stage using a clock having a different phase, and the delay value at this time is "Z ^-k (at stage N-k + 1)". It can be represented as

On the other hand, when the first integrator receives a delay signal from a stage using a clock having a different phase, the lowest integral part receiving the signal output from the adder 210 receives a delay signal having a delay value corresponding to the order. This will delay the signal. For example, as shown in FIG. 2, in the case of an N-th time interleaved sigma-delta modulator, the integrator is provided with an N-delay (Z ^−N ).

On the other hand, the counters 217 provided in the integrating unit 215 all have different coefficients, and this coefficient value is (-1) ^{k + 1} _n C _k (where n is the total order and k is the corresponding sequence number). Can be obtained from Therefore, it can be seen that the count values of the counting unit 217 shown in FIGS. 2 and 3 are all calculated through this equation.

The quantizer 220 serves to quantize the signal output by the adder 210 in the embodiment of the present invention. In this case, the signal input to the quantization unit 220 may be a signal passing through the 1-delay unit Z ^-1 or a signal that is not. When the signal input to the quantization unit 220 does not pass through the 1-delay unit, the 1-delay unit is provided on one side of the path to the clock delay unit 225.

The clock delay unit 225 delays the signal passing through the quantization unit 220 in the embodiment of the present invention, and serves to output it to the adder 210. The clock delay unit 225 has a constant delay value so that the transfer function value does not change from that of the conventional time interleaved sigma-delta modulator, which can be obtained as follows.

In general, the Nth order sigma-delta modulator has a transfer function as shown in Equation 1 below when the input signal is X, the output signal is Y, and the quantization noise is E.

Therefore, as long as there is no change in the value of the transfer function, this equation is applied to the present invention as it is. Accordingly, the input from the integrating unit 215 configured in parallel in the N-th time interleaved sigma-delta modulator 200 according to the present invention to the summation unit 210 has a transfer function as shown in Equation 2 below. . However, it is noted that the transfer function in the path provided with the clock delay unit 225 includes the noise value generated by the quantization unit 220.

In addition, according to the transfer function relational expression, the delay value of the clock delay unit 225 is set as in Equation 3 below.

Here, DV means a delay value.

As described above, the time interleaved sigma-delta modulator 200 according to the present invention constructed based on the above is operated as follows. See also FIG. 2 and FIG. 3. In a first step, the adder 210 receives V _in through the input terminal 230. Of course, the adder 210 may further receive the other two types of input signals. The input signal received by the adder 210 has already been described, and thus a detailed description thereof will be omitted herein. In a second step, the adder 210 adds and amplifies the input signals and outputs the sum signals. Then, U is output as the output signal.

In the third step, a part of the output signal U is input to the integrating unit 215, and all the signals passing through each of the integrating units 215 are summed and input to the adding unit 210. At the same time, the remainder of the output signal U is sequentially passed through the quantization unit 220 and the clock delay unit 225 and input to the summing unit 210. However, the signal input to the clock delay unit 225 passes through the delay unit 216 before passing through the quantization unit 220 or after passing through the quantization unit 220.

In the fourth step, some of the output signals passing through the quantization unit 220 are output to the outside through the output terminal 235 as V _out without going to the clock delay unit 225.

Next, we will actually implement a time interleaved sigma-delta modulator to which a single amplifier architecture is applied according to the present invention. The general configuration of the time interleaved sigma-delta modulator has already been described with reference to FIG. 2 and 3 illustrate the concept of a time interleaved sigma-delta modulator to which a single amplifier architecture is applied. Reflecting the contents of FIG. 2, if a specific block constituting the time interleaved sigma-delta modulator in FIG. 1 is designed, in particular, a sub-system block 400 is illustrated in FIG. 4. Similarly, designing a specific block constituting the time interleaved sigma-delta modulator in FIG. 1, in particular, the subsystem block 500, reflecting the content of FIG. 3, as shown in FIG. 4 and 5 may be generally inferred from the contents of FIGS. 2 and 3, and thus detailed descriptions thereof will be omitted. Note that x, u, and y are the V _in signal input from the outside through the input terminal 230, the output signal from the adder 210, and the V _out signal output from the outside through the output terminal 235, respectively. do.

On the other hand, it is understood that the specific blocks of the time interleaved sigma-delta modulator to which the single amplifier architecture shown in FIGS. 4 and 5 are applied are distinguished according to whether or not the delay unit 216 of the highest integral part is provided before the quantizer 220. Can be. This distinction results in a difference in the structure of the adder in the particular block. A detailed description thereof is well shown in the parts described with reference to FIGS. 2 and 3 and will not be described herein.

Time interleaved sigma-delta modulators are classified into low-pass time interleaved sigma-delta modulators and band-pass time interleaved sigma-delta modulators. Low pass time interleaved sigma-delta modulators are mainly used for audio, the configuration of which is described with reference to, for example, what is shown in U.S. Patent Publication No. 2007-90979 (name: Low-pass filter based delta-sigma modulator). can do. On the other hand, the bandpass time interleaved sigma-delta modulator is mainly used for wireless communication, and the configuration thereof is, for example, US Patent Publication No. 2004-169437 (name of the invention: Band-pass sigma-delta modulator and uses of sigma delta modulator for You can configure it by referring to the information in converting, detecting and producing signals. A single amplifier architecture is described below for the lowpass time interleaved sigma-delta modulator and the bandpass time interleaved sigma-delta modulator. First, a low pass time interleaved sigma-delta modulator is described.

6 is a conceptual example implemented by applying a single amplifier architecture to a specific block of the third-order low-pass time interleaved sigma-delta modulator. Designing it in the same multiple subsystem blocks and connecting them in a recursive manner is represented as shown in FIG. The time interleaved sigma-delta modulator in this case is of course implemented in three passes. In addition, a timing diagram as shown in FIG. 8 is required to drive these subsystem blocks. 9 is a time unfolded diagram for explaining the interaction (ie, connection and operation relationship) of each subsystem block.

Meanwhile, the bandpass time interleaved sigma-delta modulator may be implemented in 2N order with respect to the Nth order low pass time interleaved sigma-delta modulator. The reason for this is as follows. In general, in the case of a time interleaved sigma-delta modulator, delays included in a sub-system block are unnecessary because other sub-system blocks operating at different clocks may receive signals. Accordingly, the subsystem blocks implemented in the 2N order bandpass time interleaved sigma-delta modulator have the same form as the subsystem blocks implemented in the Nth order low pass time interleaved sigma-delta modulator. Thus, when a single amplifier architecture is applied to each block constituting the bandpass time interleaved sigma-delta modulator according to the present invention, the 2-delay part may be reflected in the 1-delay part of the highest integral. For example, applying a single amplifier architecture to a particular block of the fourth-order bandpass time interleaved sigma-delta modulator, this would be as shown in FIG.

11 through 13 illustrate internal design and recursive connection of subsystem blocks constituting a fourth order bandpass time interleaved sigma-delta modulator, timing diagrams for driving the subsystem blocks, and interaction of each subsystem block. Is a time evolution diagram for explaining the same as in the case of Figs.

On the other hand, if the bandpass time interleaved sigma-delta modulator is implemented as an even pass (e.g., 2 pass or 4 pass), the signal to noise and distortion ratio (SNDR) performance of the modulator is poor because the image of the input signal is exposed to the signal band. Done. Therefore, the bandpass time interleaved sigma-delta modulator is preferably implemented in an odd pass (e.g., three or five pass) when applying a single amplifier architecture in accordance with the present invention.

The above description is merely illustrative of the technical idea of the present invention, and various modifications, changes, and substitutions may be made by those skilled in the art without departing from the essential characteristics of the present invention. It will be possible. Accordingly, the embodiments disclosed in the present invention and the accompanying drawings are not intended to limit the technical spirit of the present invention but to describe the present invention, and the scope of the technical idea of the present invention is not limited by the embodiments and the accompanying drawings. . The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

In today's modern world, data communication (especially digital communication) is becoming an indispensable element. However, in order to perform data communication, a transmitting end providing data and a receiving end receiving data should be configured. In particular, in the case of the receiver, an A / D converter having a high resolution is required due to the expansion of the digital domain. Sigma-delta modulators, in particular time interleaved sigma-delta modulators, are increasingly used as A / D converter types with high resolution. If the volume is reduced according to the present invention and designed with low power consumption, the marketability will be very high in the future.

1 (a) is a block diagram showing the internal configuration of a conventional time interleaved sigma-delta modulator,

1 (b) is a timing diagram of a conventional time interleaved sigma-delta modulator,

2 is a conceptual diagram of the internal configuration of a time interleaved sigma-delta modulator applying a single amplifier architecture according to a first preferred embodiment of the present invention;

3 is a conceptual block diagram illustrating an internal configuration of a time interleaved sigma-delta modulator applying a single amplifier architecture according to a second preferred embodiment of the present invention;

4 is a block diagram of a specific block in a time interleaved sigma-delta modulator applying a single amplifier architecture according to a first preferred embodiment of the present invention.

5 is a block diagram of a specific block in a time interleaved sigma-delta modulator applying a single amplifier architecture according to a second embodiment of the present invention;

6 to 9 are diagrams for explaining a low pass time interleaved sigma-delta modulator applying a single amplifier architecture according to a preferred embodiment of the present invention;

10 to 13 illustrate a bandpass time interleaved sigma-delta modulator employing a single amplifier architecture according to a preferred embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

200: time interleaved sigma-delta modulator according to the present invention

210: summing unit 215: integrating unit

216: delay unit 217: counter

218: Adder 220: Quantization

225: clock delay unit 230: input terminal

235 output terminal

Claims (10)

And an adder for multiplying a delay signal input from a stage using a clock having a different phase by a predetermined coefficient and an adder for adding the multiplied value and a value derived by another counter configured in parallel with the counter. An integrator for outputting a signal containing a value as a first signal; A clock delay unit delaying a received signal and outputting the delayed signal as a second signal; A summation unit configured to sum-amplify the first signal, the second signal, and a third signal input from the outside; A quantizer for quantizing the sum amplified signal; And An output unit configured to output the quantized signal to the outside, and to feed back some of the quantized signals to the clock delay unit as the received signal Including; The total number of the integral parts provided in the sigma-delta modulator is the same as the order of the sigma-delta modulator, characterized in that at least two time interleaved sigma-delta modulator. delete The method of claim 1, The constant coefficient used by the integral when multiplying is derived from (-1) ^{k + 1} _n C _k (where n is the order of the time interleaved sigma-delta modulator and k is the corresponding order of the integral part). A time interleaved sigma-delta modulator. The method of claim 1, The clock delay unit outputs a signal output from the quantization unit.

Wherein N is the order of the time interleaved sigma-delta modulator. The method of claim 1, And a 1-delay (Z ^-1 ) in the path from the summing section to the quantization section or the path from the quantization section to the clock delay section. The method of claim 5, wherein When the 1-delay is provided on the path from the adder to the quantizer, the delay signal input from the 1-delay unit is multiplied by a predetermined coefficient and the signal containing the multiplied value is added to the first signal. The time interleaved sigma-delta modulator, characterized in that it further comprises. The method of claim 5, wherein When the 1-delay is provided on a path from the quantizer to the clock delay unit, the signal delayed by the adder is delayed by a predetermined value, multiplied by a predetermined coefficient, and the signal containing the multiplied value is added to the first delay unit. A time interleaved sigma-delta modulator further comprising a least integral part for outputting to be added to one signal. The method of claim 7, wherein And said lowest integral part uses the order of said sigma-delta modulator as said predetermined value for delaying a signal input from said summing part. The method of claim 1, The time interleaved sigma-delta modulator, characterized in that formed in the form of low pass or band pass. The method of claim 9, The time interleaved sigma-delta modulator, characterized in that implemented in the odd pass when the band pass-type modulator sigma-delta modulator.

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