CN116318162A - Double sampling Sigma-Delta modulator with chopper - Google Patents
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Abstract
The embodiment of the application provides a double-sampling Sigma-Delta modulator with chopper, which adopts a two-stage cascade structure and is formed by cascading two-stage single-ring structures, wherein the first-stage single-ring structure comprises an integrator 1, an integrator 2, an Adder, a quantizer Q1 and a feedback DAC loop which are sequentially connected; the second-stage single-loop structure comprises an integrator 3, an integrator 4, a quantizer Q2 and a feedback DAC loop which are connected in sequence; the double sampling Sigma-Delta modulator system with chopper also comprises an interstage path, and the output of the quantizer Q1 is fed back to the input end of the integrator 1 through a first-stage feedback DAC unit; the output of the integrator 2 is directly used as the input signal of a second-stage loop filter, and the output Q2 of the second-stage quantizer is fed back to the input end of the integrator 3 through the DAC 2; the digital filter module comprises an error cancellation logic function H 1 (z)、H 2 (z) eliminating the first-stage quantization error eq1 so that only the second-stage quantization error eq2 is enteredAnd the word filter module is used for completing the functions of low-pass filtering and downsampling of the output signal of the modulator.
Description
Technical Field
The embodiment of the application relates to the field of signal processing, in particular to a double-sampling Sigma-Delta modulator with chopper.
Background
With the development of digital signal processing technology, the digital domain has become the first choice to replace the analog domain because of its higher accuracy, reliability and price advantages. The digital signal can suppress noise better than the analog signal because noise and distortion are accumulated in the storage and transmission of the analog signal. Digital signals can be stored and transmitted without loss, and thus in order to take advantage of these advantages, many applications require conversion of analog signals into digital form. As a bridge between analog and digital signals, the performance of analog-to-digital converters and digital-to-analog converters is very important, and they determine the final signal processing effect.
The ADC types are diverse, such as successive approximation, pipelined, flash, and integral, and their main performance indicators are sampling speed and conversion accuracy. In selecting an ADC, the sampling speed and conversion accuracy should be evaluated according to the requirements of the application. If a high-speed, high-precision ADC is required, an oversampling ADC may be considered. Different types of ADCs have their unique advantages in different application areas. For example, in the fields of high-quality audio, medical electronics, precision instruments, sensor interfaces, physiological signal measurement, and the like, a high-precision ADC is required.
Currently, the Sigma-Delta architecture is the preferred solution for high precision ADCs. The signal-to-noise ratio (SNR) of the Sigma-delta adc can be improved by increasing the over-sampling rate (OSR) with the modulator order unchanged. However, as the sampling frequency increases, so does the power consumption of the modulator, and the operational amplifier requirements. Therefore, this approach is not compatible with the current concepts of low power chip design.
The Sigma-Delta modulator is a high-precision ADC architecture and is mainly divided into a single loop structure and a cascade structure. The single-ring structure has the advantages of simplicity, compact structure, good anti-interference performance, low implementation difficulty and easy implementation of low-power consumption design. However, due to its limited frequency response capability, it is generally only possible to sample low frequency signals. The cascade structure has the advantages of higher frequency response capability, suitability for sampling of high-frequency signals and higher signal-to-noise ratio. However, the cascade structure is complex relative to the single-ring structure, and it is difficult to realize low-power design. Thus, in selecting the Sigma-Delta modulator, it should be determined whether a single loop or a cascade structure is used according to the requirements of a particular application to ensure an optimal balance of frequency response capability and signal-to-noise ratio of the system.
Disclosure of Invention
In order to solve the problem, the embodiment of the application provides a double-sampling Sigma-Delta modulator with chopper.
The double sampling Sigma-Delta modulator with the chopper is realized by adopting the following scheme:a cascade structure Sigma-Delta modulator architecture is formed by cascading two-stage single-ring structures, wherein a first-stage single-ring structure comprises an integrator 1, an integrator 2, an Adder, a quantizer Q1 and a feedback DAC loop which are sequentially connected, and the signal transfer function of the first-stage single-ring structure is STF 1 (z) noise transfer function is NTF 1 (z); the second-stage single-loop structure comprises an integrator 3, an integrator 4, a quantizer Q2 and a feedback DAC loop which are connected in sequence, and the signal transfer function of the second-stage single-loop structure is STF 2 (z) noise transfer function is NTF 2 (z); the double sampling Sigma-Delta modulator system with chopper also comprises an interstage path, and the output of the quantizer Q1 is fed back to the input end of the integrator 1 through a first-stage feedback DAC unit; the output of the integrator 2 is directly used as the input signal of a second-stage loop filter, and the output Q2 of the second-stage quantizer is fed back to the input end of the integrator 3 through the DAC 2; the digital filter module comprises an error cancellation logic function H 1 (z)、H 2 (z) eliminating the first stage quantization error eq1 so that only the second stage quantization error eq2 enters the digital filter module, completing the low pass filtering and downsampling functions of the modulator output signal.
The integrator 1 adopts a double sampling type sample hold circuit with a chopping function. By using the double sampling technology, the signal to noise ratio of the modulator is effectively improved under the condition of not changing the clock frequency. Chopping techniques are used to reduce the 1/f noise and dc offset voltage of integrator 1, thereby effectively reducing the effects of these factors.
The first-stage single-loop structure of the modulator system is a feedforward 1-bit quantization structure, and the feedforward coefficients a1, a2, a3 and a4 of the first-stage loop filter are adjusted to enable quantization noise eq1 of the first stage and noise introduced by an Adder to be output through an integrator 2 and input to the second stage, so that noise in a loop can be further reduced; the second-stage single-loop structure is a distributed feedback type 1-bit quantization structure, and a scaling coefficient c1 is introduced in front of the integrator 4, so that the performance of the loop filter is further improved.
The quantizer Q1 and the quantizer Q2 are 1-bit quantizers, and are realized by adopting a dynamic comparator and an SR latch, so that the area, the power consumption and the error caused by capacitance mismatch of the circuit can be further reduced.
The feedback loops DAC1 and DAC2 are provided, and the quantizer Q1 and the quantizer Q2 are 1-bit quantizers, and the double-sampling type sample hold circuit is easy to cause high-frequency noise, so that the feedback DAC1 and DAC2 are single-capacitance type DAC, and the high-frequency noise introduced by double sampling can be effectively reduced.
The integrator 1-the integrator 4 apply the chopping technology, the input signal is carried to the high frequency through one-time chopping modulation and then is overlapped with offset noise and flicker noise, the input signal is modulated through one-time chopping after operational amplification treatment, at the moment, the input signal is modulated twice and returns to the original frequency band, the offset noise and the flicker noise are modulated once and are left at the high frequency, and then the offset noise and the flicker noise are filtered by a digital filter.
Compared with the prior art, the embodiment of the application has the following beneficial effects:
1. according to the double-sampling Sigma-Delta modulator with chopper, a two-stage cascade structure is adopted, a first-stage single-ring structure adopts a feedforward type 1-bit quantization loop filter structure, adder noise is introduced into a next-stage loop filter, and the signal to noise ratio is improved; the second-stage single-loop structure adopts a distributed feedback type 1-bit quantization loop filter structure, so that the system stability of the whole structure is improved.
2. According to the embodiment of the application, the double-sampling type sampling and holding circuit with the chopping function is adopted in the integrator 1, so that the clock frequency is reduced to be half of the original frequency on the premise of keeping the original over-sampling ratio OSR, and in one clock period T, the integrator 1 completes twice sampling and twice integration, the setting time of the operational amplifier is prolonged to be twice of the original time, and the power consumption of the operational amplifier can be effectively reduced. Meanwhile, the introduction of the chopper switch can effectively reduce noise generated by mismatch of the sampling capacitor and 1/f noise of the operational amplifier of the integrator, and the overall signal-to-noise ratio of the modulator is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description will make a brief introduction to the drawings used in the description of the embodiments or the prior art.
Fig. 1 is a diagram illustrating a Sigma-Delta modulator system architecture based on the modified double sampling technique presented herein.
Fig. 2 is a circuit diagram of a conventional double sampling switched capacitor integrator.
Fig. 3 shows a timing diagram for a double sampling switched capacitor integrator with chopping.
Fig. 4 shows a circuit diagram of a double sampling switched capacitor integrator with chopping.
Fig. 5 shows a schematic diagram of a comparator circuit used in the quantizer.
Fig. 6 shows a schematic diagram of the Sigma-Delta modulator circuit presented herein.
Fig. 7 shows a graph of the output signal spectrum of the Sigma-Delta modulator proposed herein.
Detailed Description
The technical solutions of the embodiments of the present application are specifically described below with reference to the accompanying drawings.
The embodiment of the application provides a double-sampling Sigma-Delta modulator with chopper, which mainly comprises a system level and a circuit level; the system level part is relevant to the overall system structure of the Sigma-Delta modulator, and the circuit level part relates to the specific circuit implementation of key constituent modules (integrator, quantizer and the like) of the modulator.
In the embodiment of the present application, the modulator has a two-stage cascade structure, as shown in fig. 1, and the transfer functions of integrator 1, integrator 2, integrator 3 and integrator 4 in fig. 1 are all
The transfer function of the first-order monocyclic structure at this time is (2 z -1 -z -2 )*X 1 (z) introducing a portion of the signal to be processed of the first-stage monocyclic structure into the second-stage monocyclic structure; the transfer function of the second-order monocyclic structure is +.>
Because the first-stage single-ring structure is a feedforward structure, one more analog adder is added than the feedback structure, and the adder introducesIs introduced into the second stage for higher order filtering, improving the overall signal-to-noise ratio of the modulator system.
According to the system level block diagram of the Sigma-Delta modulator based on the modified double sampling technique shown in fig. 1, the system Z-domain transfer functions of the first and second stages of the modulator can be written as:
V 1 (z)＝STF 1 (z)*X 1 (z)+NTF 1 (z)*E 1 (z)
V 2 (z)＝STF 2 (z)*X 2 (z)+NTF 2 (z)*E 2 (z)
wherein V is 1 (z) and V 2 (z) the outputs of the quantizers Q1 and Q2, respectively, as output signals of the first and second stages of the modulator; STF (Standard template f) 1 (z) and NTF 1 (z) the signal transfer function and the noise transfer function of the first stage of the modulator, X 1 (z) and E 1 (z) a first stage input signal and quantization error, respectively; similarly, STF 2 (z) and NTF 2 (z) X as the signal transfer function and the noise transfer function of the second stage, respectively 2 (z) and E 2 (z) is the second stage input signal and quantization error.
The deduction can be carried out:
the values of the modulator coefficients are properly selected according to the expressions of STF1 (z) and NTF1 (z) so as to beSTF1 (z) =1 is satisfied,
wherein D (Z) is a polynomial comprising Z.
Ideally, after V1 (z) and V2 (z) pass through the error cancellation logic functions H1 (z) and H2 (z), respectively, the quantization noise e1 of the first stage is completely cancelled, and the final output signal V only includes the quantization noise e2 of the second stage, and has the effect of 4-stage noise shaping.
To completely eliminate quantization noise (E1) of the first stage, NTF1 (z) X E1 (z) +stf2 (z) X2 (z) X H2 (z) =0. The input signal (X2 (z)) of the second stage contains only the component of the quantization noise (e 1). In general, H2 (z) comprises (1-z -1 ) 2 Has a noise shaping function; while H1 (z) is typically composed of a signal delay block, which is a low-pass output. Thus, the H2 (z) can be used to suppress the non-linearity problem of the second stage feedback unit (DAC 2) due to the capacitance mismatch.
The integrators in a typical discrete Sigma-Delta modulator are all implemented by switched capacitor integrators. Figure 2 shows a single ended implementation of a double sampling integrator. In this circuit, the input signal is sampled by two different capacitances, the capacitance CS1 being sampled in the Φ1 phase and integrated in the Φ2 phase; the capacitor CS2 samples in Φ2 and integrates in Φ1, so that there is both sampling and integration in both phases of the clock, and the effective sampling frequency is doubled accordingly. For input signal sampling, the modulated signal does not occur in the signal band due to the low frequency of the input signal, and therefore the input signal is not affected. However, in the case of the feedback DAC of the modulator, since the output of the DAC contains high frequency quantization noise, the above-described signal modulation phenomenon due to mismatch may fold the quantization noise back into the band, thereby deteriorating the SNR of the modulator. This phenomenon is a major drawback of the double sampling Sigma-Delta modulator.
Fig. 3 is a timing diagram corresponding to the integrator 1 in the Sigma-Delta modulator with chopping double sampling according to the embodiment of the present application, which is formed by an internal clock generating circuit.
Fig. 4 shows a double sampling switched capacitor integrator used in the integrator 1, mainly comprising: the sampling capacitor Cs, the integrating capacitor Ch, the feedback capacitor Cfb, the double sampling switch group CH1A, CH2A, CH1B, CH B, the chopper switches CHA and CHB and an operational amplifier OTA; wherein CHA, CHB, S1, S2 are two-phase non-overlapping clocks, the double sampling switch group always keeps the conduction of the input loop, and integration and sampling are completed at the same time; CH1A, CH a is obtained from CHA, S1, S2, respectively. The Input signal of the integrator 1 comprises the Input signal Input of the modulator and the output signal from the feedback unit DAC1, for the Input signal Input branch a conventional double sampling switched capacitor integrator as shown in fig. 2 is used; since the output signal of DAC1 has its peak energy at frequency Fc, the integrator structure shown in fig. 2 is not preferred, and thus, the fully floating double sampling switched capacitor integrator shown in fig. 4 is adopted to solve this problem.
For the operational amplifier input end of the integrator 1, when CHA is at a high level and CHB is at a low level, the uppermost double sampling network in FIG. 4 samples vin+, integrates Vin-, and the lowermost double sampling network integrates vin+, and samples Vin-; the sampling integration mode is similar when CHA is high and CHB is low. From the principle of conservation of charge, the transfer function of the improved double sampling integrator shown in fig. 4 can be deduced as:
fig. 5 shows a circuit structure adopted by a quantizer in the embodiment of the present application, where the quantizers Q1 and Q2 are 1-bit quantizers, and one-bit quantizer can be implemented in a circuit through one comparator, so that parameters such as precision and offset of the quantizer in the modulator do not seriously affect the overall performance of the modulator. In order to save the power consumption of the system, a dynamic comparator is used, because it does not generate static power consumption, only generates power consumption when comparing, and the comparison speed is faster.
The dynamic comparator of fig. 4 includes a clocked differential input pair MN1, MN2, two cross-coupled pairs MN3, MN4 and MP5, MP6 and four precharge switches MP1, MP2, MP3, MP4. The circuit provides rail-to-rail outputs at X and Y depending on the input polarity. LATCH signals are low, MN1 and MN2 are off, node P, Q, X, Y is precharged to VDD, LATCH signals go high, MP1-MP6 are off, MN1 and MN2 are on, and a differential current proportional to Vin1-Vin2 is formed. This current flows from P and Q just after MN3-MP6 turns off, which may provide some voltage gain. When VP and VQ drop to VDD-VTHN, the cross-coupled NMOS opens up to the pair of transistors MN3, MN4, allowing some of the drain current of MN1 and MN2 to flow from the X-node and the Y-node, since the sum of the input capacitances of the X-point, the Y-point and the comparator later stages is typically greater than the P-point and the Q-point when the circuit is actually implemented, and thus the cross-coupled NMOS provides less acceleration at this stage. With the output voltages VX and VY decreasing until MP5 or MP6 is turned on, the comparator enters a fourth operating state, so that the circuit enters a positive feedback operating state, one output is finally returned to VDD, the other output drops to 0, and finally the output is latched by the SR latch and used for controlling the feedback DAC after its driving capability is enhanced by the inverter chain.
In the comparator circuit of fig. 4, in the voltage gain amplification mode, the difference between VP and VQ is:
wherein g m1，2 Is the transconductance of the input tubes MN1, MN2, C P,Q Is the equivalent capacitance of the P and Q points.
Fig. 6 is a schematic circuit diagram of a double sampling Sigma-Delta modulator with chopper according to an embodiment of the present application, where the control switch operates under two non-overlapping clock signals. The modulator is of a two-stage cascade structure, and a first-stage single-ring structure is composed of an integrator 1, an integrator 2, an Adder, a quantizer Q1 and a feedback DAC loop; the second-stage single-loop structure is composed of an integrator 3, an integrator 4, a quantizer Q2 and a feedback DAC loop; the double sampling Sigma-Delta modulator system with chopper also comprises an interstage path, and the output of the quantizer Q1 is fed back to the input end of the integrator 1 through a first-stage feedback DAC unit; the output of integrator 2Directly serving as an input signal of a second-stage loop filter, and feeding back a second-stage quantizer output Q2 to an input end of an integrator 3 through a DAC 2; the digital filter module comprises an error cancellation logic function H 1 (z)、H 2 (z) eliminating the first stage quantization error eq1 so that only the second stage quantization error eq2 enters the digital filter module, completing the low pass filtering and downsampling functions of the modulator output signal. The operational amplifiers in the integrator 1 are all folded cascode operational amplifiers with auxiliary operational amplifiers, and the integrator 2-integrator 4 is folded cascode operational amplifiers without auxiliary operational amplifiers.
In the embodiment of the present application, the sampling frequency of the modulator is 7.32MHz, and the oversampling rate OSR is set to 128; the frequency of the input signal meets the coherent sampling theorem, so that frequency spectrum leakage is prevented; simulation is carried out on the output of the modulator by using Cadence virtual and Matlab combined simulation, and the obtained simulation result is shown in figure 7; simulation results indicate that the modulator overall SNDR 130.3Db has an effective number of ENOB 21.36 bits. Therefore, compared with the traditional cascaded Sigma-Delta modulator, the embodiment of the application has relatively simple circuit implementation and can obtain better performance indexes.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (4)
1. A double sampling Sigma-Delta modulator with chopper, characterized by: the modulator architecture adopts a two-stage cascade structure, a first-stage single-ring structure comprises an integrator 1, an integrator 2, an Adder, a quantizer Q1 and a feedback DAC loop which are sequentially connected, and the signal transfer function of the first-stage single-ring structure is STF 1 (z) noise transfer function is NTF 1 (z); the second-stage single-loop structure comprises an integrator 3, an integrator 4, a quantizer Q2 and a feedback DAC loop which are connected in sequence, and the signal transfer function of the second-stage single-loop structure is STF 2 (z) noise transfer function is NTF 2 (z); the double sampling Sigma-Delta modulator system with chopper also comprises an interstage path, and the output of the quantizer Q1 is fed back to the input end of the integrator 1 through a first-stage feedback DAC unit; the output of the integrator 2 is directly used as the input signal of a second-stage loop filter, and the output Q2 of the second-stage quantizer is fed back to the input end of the integrator 3 through the DAC 2; the digital filter module comprises an error cancellation logic function H 1 (z)、H 2 (z) eliminating the first stage quantization error eq1 so that only the second stage quantization error eq2 enters the digital filter module, completing the low pass filtering and downsampling functions of the modulator output signal.
2. A double sampling Sigma-Delta modulator with chopping according to claim 1, wherein: the integrator 1 in the first-stage single-ring structure uses a double-sampling type sampling and holding circuit and has a chopping function, so that the clock frequency is reduced to be half of the original frequency on the premise of keeping the original over-sampling ratio OSR, and in one clock period T, the integrator 1 completes twice sampling and twice integration, the time for establishing the operational amplifier is prolonged to be twice of the original time, and the power consumption of the operational amplifier can be effectively reduced. Meanwhile, the introduction of the chopper switch can effectively reduce noise generated by mismatch of the sampling capacitor and 1/f noise of the operational amplifier of the integrator, and the overall signal-to-noise ratio of the modulator is improved.
3. A double sampling Sigma-Delta modulator with chopping according to claim 2, wherein: the first-stage single-loop structure of the modulator system is a feedforward 1-bit quantization structure, and the feedforward coefficients a1, a2, a3 and a4 of the first-stage loop filter are adjusted to enable quantization noise eq1 of the first stage and noise introduced by an Adder to be output through an integrator 2 and input to the second stage, so that noise in a loop can be further reduced; the second-stage single-loop structure is a distributed feedback type 1-bit quantization structure, and a scaling coefficient c1 is introduced in front of the integrator 4, so that the performance of the loop filter is further improved.
4. The Sigma-Delta modulator based on the modified double sampling technique of claim 1, wherein said quantizer Q1 and quantizer Q2 are 1-bit quantizers, which are comprised of dynamic comparators and SR latches, to further reduce the area of the circuit, the power consumption and the error due to capacitance mismatch.
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