CN110875742B - Discrete low-power-consumption integrator for delta-sigma modulator - Google Patents
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Abstract
The invention discloses a discrete low-power-consumption integrator for a delta-sigma modulator, which comprises a clock generation submodule, a first feedback integration submodule, a second feedback integration submodule and an integration amplifier, wherein the clock generation submodule comprises a first output end, a second output end, a third output end and a fourth output end, a clock generation submodule circuit is connected with the first feedback integration submodule, the second feedback integration submodule and the integration amplifier through the output ends of the clock generation submodule, and generates clock pulses with different phase frequencies to control the first feedback integration submodule, the second feedback integration submodule and the integration amplifier. The invention also provides a method for controlling the enabling end of the integrating amplifier by using the clock, which is used for reducing the power consumption of the integrator. The integrator can effectively reduce nonlinear distortion, and can greatly reduce the voltage overshoot problem caused by switching.
Description
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a discrete low-power-consumption integrator for a delta-sigma modulator.
Background
Analog-to-digital converters (ADCs) play an important role in signal processing to connect digital and analog world bridges. The method has wide application in the fields of digital audio, image coding, frequency synthesis and various sensors. At present, the delta-sigma ADC based on oversampling and noise shaping technology is mainly used in a high-precision, low-voltage and low-power consumption system. The Delta-sigma modulator structure mainly comprises three modules: 1) a loop filter determining a noise transfer function; 2) a quantizer, which usually uses a 1-bit quantizer, although the multi-bit quantizer can improve the noise shaping capability of the system, it will generate nonlinear effect, and it needs to add an additional dynamic device matching logic circuit for correcting and improving linearity; 3) feedback digital-to-analog converters (DACs), which typically have the same number of bits as the DAC, have non-linearity problems when the number of bits is greater than 1.
Based on the working mode of the filter in the loop filter, the structure of the delta-sigma modulator is mainly divided into two types: 1) continuous Time (CT) delta-sigma modulation has large bandwidth, low power consumption and a self-contained anti-aliasing filter circuit, reduces the complexity of the circuit, but has low precision and is very sensitive to clock jitter and feedback delay, and the resistance-capacitance mismatch caused by the process also has serious influence on the performance. 2) Switched Capacitor (SC) delta-sigma modulation has a smaller bandwidth (<1MHz) than continuous time delta-sigma modulators, but with high accuracy and well-established design methods and process technology.
For widely used switched capacitor delta-sigma modulators, the core part is the design of an integrator, and a large amount of nonlinear harmonic distortion is generated due to the fact that a switched capacitor integrator with a traditional structure uses too many switches. Meanwhile, the switch itself has non-linear on-resistance and non-ideal factors such as charge leakage and clock feed-through, which all have serious influence on the overall performance of the modulator.
Therefore, for the delta-sigma modulator, improving the linearity of the front-end input of the integrator, reducing the nonlinear distortion caused by the switch, and the like are the key points for improving the overall performance of the modulator, and the integrator determines the overall power consumption of the modulator at the same time, so that reducing the power consumption and area of a single integrator means greatly reducing the power consumption and area cost of the entire modulator.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a discrete low power consumption integrator for a delta-sigma modulator, and also provides a method for reducing the power consumption of the integrator through clock control and an area improvement of the integrator by reducing the number of switches.
The invention is realized by adopting the following technical scheme:
a discrete low-power-consumption integrator for a delta-sigma modulator comprises a clock generation submodule, a first feedback integration submodule, a second feedback integration submodule and an integration amplifier, wherein the clock generation submodule comprises a first output end, a second output end, a third output end and a fourth output end, the clock generation submodule is connected with the first feedback integration submodule, the second feedback integration submodule and the integration amplifier through the output ends of the clock generation submodule, and generates clock pulses with different phase frequencies to control the first feedback integration submodule, the second feedback integration submodule and the integration amplifier; the first output end and the second output end are clocks with phase difference, the first output end and the third output end are non-overlapped clocks, and the third output end and the fourth output end are clocks with phase difference; the first feedback integration submodule and the second feedback integration submodule are both connected with a feedback end of the delta-sigma modulator circuit and an integration amplifier, and the integration amplifier integrates voltage signals output by the first feedback integration submodule and the second feedback integration submodule according to a set proportional coefficient;
the integrating amplifier comprises a fully differential operational amplifier, a first integrating resistor, a first integrating capacitor, a first switch, a first coupling capacitor, a third switch, a second integrating resistor, a second integrating capacitor, a second switch, a second coupling capacitor, a twelfth switch and a thirteenth switch; one end of the first integrating capacitor and one end of the first switch are connected with the inverting end of the fully differential operational amplifier; one end of the first feedback integration submodule and one end of the first integration resistor are connected with the other end of the first switch; the other end of the first integrating capacitor is connected with the positive output end of the fully differential operational amplifier; the other end of the first integrating resistor is connected with a negative end input signal of the modulator; one end of the second integrating capacitor and one end of the second switch are connected with the positive phase end of the fully differential operational amplifier; one end of the second feedback integration submodule and one end of the second integration resistor are connected with the other end of the second switch; the other end of the second integrating capacitor is connected with the negative output end of the fully differential operational amplifier; the other end of the second integrating resistor is connected with a positive end input signal of the modulator, one end of a third switch is connected with a negative end input signal of the delta-sigma modulator, and the other end of the third switch is connected with one end of the first coupling capacitor; the other end of the first coupling capacitor is connected with the second integrating resistor and one end of the second switch; one end of the thirteenth switch is connected with a positive end input signal of the delta-sigma modulator, and the other end of the thirteenth switch is connected with one end of the second coupling capacitor; the other end of the second coupling capacitor is connected with the first integrating resistor and one end of the first switch; one end of the twelfth switch is connected with the enabling end of the fully differential operational amplifier, and the other end of the twelfth switch is connected with an external high level; the fully differential operational amplifier is in a working state when the level of the enabling end of the fully differential operational amplifier is high, and does not work when the level of the enabling end of the fully differential operational amplifier is low.
In the above technical solution, further, the first switch and the second switch are connected to a third output of the clock generation submodule, and the third switch, the twelfth switch and the thirteenth switch are connected to a fourth output of the clock generation submodule; the clock pulse output by the clock generation submodule controls the on or off of the first switch, the second switch, the third switch, the twelfth switch and the thirteenth switch, and the five switches are all closed when the clock pulse is at a high level.
Furthermore, the first feedback integration submodule comprises a fourth switch, a fifth switch, a sixth switch, a seventh switch and a first feedback capacitor, the fourth switch is connected with the positive feedback end of the delta-sigma modulator circuit, the fifth switch is connected with the negative feedback end of the delta-sigma modulator circuit, the other end of the fifth switch, one end of the first feedback capacitor and one end of the sixth switch are connected with the other end of the fourth switch, one end of the seventh switch and one end of the first switch are connected with the other end of the first feedback capacitor, and the other end of the sixth switch and the other end of the seventh switch are connected with an external common mode level;
the second feedback integration submodule comprises an eighth switch, a ninth switch, a tenth switch, an eleventh switch and a second feedback capacitor, the eighth switch is connected with the positive feedback end of the delta-sigma modulator circuit, the ninth switch is connected with the negative feedback end of the delta-sigma modulator circuit, the other end of the ninth switch, one end of the second feedback capacitor and one end of the tenth switch are connected with the other end of the eighth switch, one end of the eleventh switch and one end of the second switch are connected with the other end of the second feedback capacitor, and the other ends of the tenth switch and the eleventh switch are connected with an external common mode level.
Furthermore, the fourth switch is connected with the negative end of the delta-sigma modulator circuit one-bit quantizer, the fifth switch is connected with the positive end of the delta-sigma modulator circuit one-bit quantizer, the sixth switch is connected with the second output end of the clock generation submodule, and the seventh switch is connected with the first output end of the clock generation submodule; the eighth switch is connected with the positive end of the delta-sigma modulator circuit one-bit quantizer, the ninth switch is connected with the negative end of the delta-sigma modulator circuit one-bit quantizer, the tenth switch is connected with the second output end of the clock generation submodule, and the eleventh switch is connected with the first output end of the clock generation submodule.
The invention has the beneficial effects that:
compared with the prior art, the invention changes the input structure of the front end and changes the first-stage switch capacitance sampling mode into a resistance input and capacitance coupling mode. When only the resistor is input, the switch node can generate a larger overshoot phenomenon, so that the overshoot on the input node is reduced by the invention through a capacitive coupling mode between two inputs of the delta-sigma modulator, thereby reducing the nonlinear distortion, and simultaneously greatly reducing the harmonic distortion caused by the nonlinear on-resistance of the switch.
Compared with the traditional switched capacitor type integrator structure, the structure of the invention reduces the use of switches, thereby not only reducing the distortion caused by the charge leakage and clock feed-through of the switches, but also reducing the area of the integrator, and further greatly reducing the area of the whole modulator.
The invention also provides a mode of controlling the enabling end of the integrating amplifier by the clock, which changes the working mode of the traditional switched capacitor type integrator, and controls whether the enabling end of the fully differential operational amplifier is connected to a high level or not by the fourth output of the clock generation submodule, so that the fully differential operational amplifier is in a working state only when the fourth output of the clock generation submodule is at the high level, and the average power consumption of the fully differential operational amplifier is reduced by half; from the perspective of the modulator, since the power consumption of the fully differential operational amplifier accounts for 60% -70% of the power consumption of the modulator, the power consumption of the whole modulator can be greatly reduced by using the integrator of the invention.
Drawings
FIG. 1 is a circuit diagram of a clock generation submodule according to an embodiment of the present invention;
FIG. 2 is a diagram of an exemplary circuit configuration of a switched capacitor integrator provided by an embodiment of the present invention;
FIG. 3 is a waveform diagram of clock signals output by the first output terminal (clk1), the second output terminal (clk1d), the third output terminal (clk2) and the fourth output terminal (clk2d) of the clock generation submodule according to the embodiment of the present invention;
fig. 4 is a graph comparing the waveform of the input terminal of the operational amplifier of the conventional switched capacitor integrator, the waveform of the input terminal of the operational amplifier when the resistor is input, and the waveform of the input terminal of the operational amplifier of the exemplary structure of the present invention.
Detailed Description
In order to make the objects and technical advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and examples. The following examples are intended to illustrate the invention, but not to limit the scope thereof.
Fig. 2 is a schematic circuit diagram of an exemplary switched capacitor integrator, and as shown in fig. 2, the present invention provides a discrete low power consumption integrator suitable for a delta-sigma modulator, which includes a clock generation sub-module, a first feedback integration sub-module, a second feedback integration sub-module, and an integrating amplifier. The clock generation submodule is respectively connected with the first feedback integration submodule, the second feedback integration submodule and the integration amplifier and generates clock pulses with different phase frequencies to control the first feedback integration submodule, the second feedback integration submodule and the integration amplifier. As shown in fig. 1, the clock generation submodule has a first output clk1, a second output clk1d, a third output clk2 and a fourth output clk2 d. The output clock pulse frequencies of the first output clk1, the second output clk1d, the third output clk2 and the fourth output clk2 are all 50MHz in this example. As shown in fig. 3, the clock pulses output by the first output terminal clk1 and the second output terminal clk1d of the clock generation submodule have a certain delay Td1 of 500ps, the first output terminal clk1 and the third output terminal clk2 are non-overlapped clocks, the rising edges and the falling edges of the two clocks are separated by Tc of about 1ns, respectively, and the clock pulses output by the third output terminal clk2 and the fourth output terminal clk2d have a certain delay Td2 of 500 ps. The first feedback integration submodule and the second feedback integration submodule are respectively connected with a feedback end of the delta-sigma modulator circuit and an integration amplifier, and the integration amplifier integrates voltage signals output by the first feedback integration submodule and the second feedback integration submodule according to a set proportional coefficient.
The integrating amplifier comprises a fully differential operational amplifier OP, a first integrating resistor R1, a first integrating capacitor Ci1, a first switch S1, a first coupling capacitor Cp1, a third switch S3, a second integrating resistor R2, a second integrating capacitor Ci2, a second switch S2, a second coupling capacitor Cp2, a twelfth switch S12 and a thirteenth switch S13. One end of the first integrating capacitor Ci1 and one end of the first switch S1 are connected to the inverting terminal of the fully differential operational amplifier; one end of the first feedback integration submodule and one end of the first integration resistor R1 are connected with the other end of the first switch S1; the other end of the first integrating capacitor Ci1 is connected with the positive output terminal Voutp of the fully differential operational amplifier; the other end of the first integrating resistor R1 is connected with a negative end input signal inn of the delta-sigma modulator; one end of the second integrating capacitor Ci2 and one end of the second switch are connected with the positive phase end of the fully differential operational amplifier; one end of the second feedback integration submodule and one end of the second integration resistor R2 are connected with the other end of the second switch S2; the other end of the second integrating capacitor Ci2 is connected with a negative output terminal Voutn of the fully differential operational amplifier; the other end of the second integrating resistor R2 is connected with a positive terminal input signal inp of the delta-sigma modulator, one end of a third switch S3 is connected with a negative terminal input signal inn of the delta-sigma modulator, and the other end of the third switch S3 is connected with one end of a first coupling capacitor Cp 1; the other end of the first coupling capacitor Cp1 is connected with one end of a second integrating resistor R2 and a second switch S2; one end of the thirteen switch S13 is connected with a positive end input signal inp of the delta-sigma modulator, and the other end of the thirteen switch S13 is connected with one end of a second coupling capacitor Cp 2; the other end of the second coupling capacitor Cp2 is connected with the first integrating resistor R1 and one end of the first switch S1; one end of the twelfth switch S12 is connected with the enable end EN of the fully differential operational amplifier, and the other end is connected with the external high level VDD; the fully differential operational amplifier is in a working state when the level of the enabling end of the fully differential operational amplifier is high, and does not work when the level of the enabling end of the fully differential operational amplifier is low.
The first switch S1 and the second switch S2 are connected to the third output clk2 of the clock generation submodule, and the third switch S3, the twelfth switch S12 and the thirteenth switch S13 are connected to the fourth output clk2d of the clock generation submodule; the clock pulse output by the clock generation submodule controls the on or off of the first switch, the second switch, the third switch, the twelfth switch and the thirteenth switch, and the five switches are all closed when the clock pulse is at a high level.
The first feedback integration submodule comprises a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7 and a first feedback capacitor Cf1, the fourth switch S4 is connected with a positive feedback end Vrefp of the delta-sigma modulator circuit, the fifth switch S5 is connected with a negative feedback end Vrefn of the delta-sigma modulator circuit, the other end of the fourth switch S4 is connected with the other end of the fifth switch S5, the first feedback capacitor Cf1 and one end of the sixth switch S6, the other end of the first feedback capacitor Cf1 is connected with one end of the seventh switch S7 and one end of the first switch S1, and the other ends of the sixth switch and the seventh switch are connected with an external common mode level Vcm. The second feedback integration submodule comprises an eighth switch S8, a ninth switch S9, a tenth switch S10, an eleventh switch S11 and a second feedback capacitor Cf2, the eighth switch S8 is connected with a positive feedback end Vrefp of the delta-sigma modulator circuit, the ninth switch S9 is connected with a negative feedback end Vrefn of the delta-sigma modulator circuit, the other end of the eighth switch S8 is connected with the other end of the ninth switch S9, the second feedback capacitor Cf2 and one end of the tenth switch S10, the other end of the second feedback capacitor Cf2 is connected with one end of the eleventh switch S11 and one end of the second switch S2, and the other ends of the tenth switch and the eleventh switch are connected with an external common mode level Vcm. The fourth switch S4 is connected to the negative terminal QB of the delta-sigma modulator circuit one-bit quantizer, the fifth switch S5 is connected to the positive terminal Q of the delta-sigma modulator circuit one-bit quantizer, the sixth switch S6 is connected to the second output clk1d of the clock generation submodule, and the seventh switch S7 is connected to the first output clk1 of the clock generation submodule. The eighth switch S8 is connected to the positive terminal Q of the delta-sigma modulator circuit one-bit quantizer, the ninth switch S9 is connected to the negative terminal QB of the delta-sigma modulator circuit one-bit quantizer, the tenth switch S10 is connected to the second output clk1d of the clock generation submodule, and the eleventh switch S11 is connected to the first output clk1 of the clock generation submodule.
The operation of the integrating circuit of the present invention, as shown in fig. 2, for a delta-sigma modulator will be described. When the first output clk1 of the clock generation submodule is high, the second output clk1d goes high, and the third output clk2 and the fourth output clk2d go low, at which time the third switch S3, the twelfth switch S12 and the thirteenth switch S13 are turned off, and both ends of the two feedback capacitors Cf1 and Cf2 are connected to the external common mode level Vcm. Meanwhile, the enable end EN of the fully differential operational amplifier OP is invalid, so that the fully differential operational amplifier OP is in an inoperative state, and the whole integrator stops working. When the first output clk1 of the clock generation submodule is at a low level, the second output clk1d goes low, and the third output clk2 and the fourth output clk2d go high, at this time, the third switch S3, the twelfth switch S12, and the thirteenth switch S13 are turned on, and the enable end EN of the fully differential operational amplifier OP is asserted, so that the fully differential operational amplifier OP is in a working state. Meanwhile, the channel from the integrating resistor R1 to the integrating capacitor Ci1 is closed and conducted by the first switch S1, and the channel from the integrating resistor R2 to the integrating capacitor Ci2 is conducted by the second switch S2. The coupling capacitors Cp1 and Cp2 couple the two inputs inn and inp of the modulator, the two ends of the feedback capacitors Cf1 and Cf2 are disconnected from the external common mode level Vcm, and the whole integrator is in an integrating state.
By analysis, assuming that the input clock frequency is Fs, n is the number of integration cycles of the integrator, Ci1 and Cf1 are respectively the integrating capacitor and the feedback capacitor mentioned in fig. 2 in this example, Vrefp and Vrefn are respectively the positive and negative feedback terminal voltages of the delta-sigma modulator, Vcm is the external common mode level, Cp is the coupling capacitor of the input, Cs is the equivalent sampling capacitor in the conventional switched capacitor integrator, vinp (t), vinn (t) are respectively the positive and negative input voltages of the delta-sigma modulator, the output voltage voutp (voutn) of the integrator of the present invention can be expressed as:
compared with the prior art, the invention changes the input structure of the front end and changes the first-stage switch capacitance sampling mode into a resistance input and capacitance coupling mode. When only the resistor is input, the capacitor coupling structure is not provided, that is, when the third switch, the thirteenth switch, the first coupling capacitor and the second coupling capacitor are omitted in the structure of fig. 2, the first switch node can generate a larger overshoot phenomenon, so that the overshoot on the input node is reduced by the invention through a capacitive coupling mode between the two inputs of the delta-sigma modulator, thereby reducing the nonlinear distortion, and simultaneously greatly reducing the harmonic distortion caused by the nonlinear on-resistance of the switch. As shown in fig. 4, waveforms of the operational amplifier input end of the conventional switched capacitor integrator, waveforms of the operational amplifier input end only when the resistor input has no capacitive coupling structure, and waveforms of the operational amplifier input end of the structure of the present invention are sequentially shown from top to bottom, and it is obvious that the overshoot phenomenon of the node signal is effectively reduced compared with the former two.
The technology adopted by the invention reduces the area and the power consumption of the integrator, and meanwhile, the output of the integrator can be equivalent to that of the traditional switched capacitor type integrator. The integral linearity of the delta-sigma modulator designed by the integrator is better than that of the prior art, and the area and the power consumption are greatly reduced.
The present invention has been described in connection with the preferred embodiments, but the present invention is not limited to the above embodiments, and any modifications, equivalents and improvements made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (1)
1. A discrete low-power-consumption integrator for a delta-sigma modulator is characterized by comprising a clock generation submodule, a first feedback integration submodule, a second feedback integration submodule and an integration amplifier, wherein the clock generation submodule comprises a first output end, a second output end, a third output end and a fourth output end, the clock generation submodule is connected with the first feedback integration submodule, the second feedback integration submodule and the integration amplifier through the output ends of the clock generation submodule, and generates clock pulses with different phase frequencies to control the first feedback integration submodule, the second feedback integration submodule and the integration amplifier; the first output end and the second output end are clocks with phase difference, the first output end and the third output end are non-overlapped clocks, and the third output end and the fourth output end are clocks with phase difference; the first feedback integration submodule and the second feedback integration submodule are both connected with a feedback end of the delta-sigma modulator circuit and an integration amplifier, and the integration amplifier integrates voltage signals output by the first feedback integration submodule and the second feedback integration submodule according to a set proportional coefficient;
the integrating amplifier comprises a fully differential operational amplifier, a first integrating resistor, a first integrating capacitor, a first switch, a first coupling capacitor, a third switch, a second integrating resistor, a second integrating capacitor, a second switch, a second coupling capacitor, a twelfth switch and a thirteenth switch; one end of the first integrating capacitor and one end of the first switch are connected with the inverting end of the fully differential operational amplifier; one end of the first feedback integration submodule and one end of the first integration resistor are connected with the other end of the first switch; the other end of the first integrating capacitor is connected with the positive output end of the fully differential operational amplifier; the other end of the first integrating resistor is connected with a negative end input signal of the modulator; one end of the second integrating capacitor and one end of the second switch are connected with the positive phase end of the fully differential operational amplifier; one end of the second feedback integration submodule and one end of the second integration resistor are connected with the other end of the second switch; the other end of the second integrating capacitor is connected with the negative output end of the fully differential operational amplifier; the other end of the second integrating resistor is connected with a positive end input signal of the modulator, one end of a third switch is connected with a negative end input signal of the delta-sigma modulator, and the other end of the third switch is connected with one end of the first coupling capacitor; the other end of the first coupling capacitor is connected with the second integrating resistor and one end of the second switch; one end of the thirteenth switch is connected with a positive end input signal of the delta-sigma modulator, and the other end of the thirteenth switch is connected with one end of the second coupling capacitor; the other end of the second coupling capacitor is connected with the first integrating resistor and one end of the first switch; one end of the twelfth switch is connected with the enabling end of the fully differential operational amplifier, and the other end of the twelfth switch is connected with an external high level; the fully differential operational amplifier is in a working state when the level of an enabling end of the fully differential operational amplifier is high, and does not work when the level of the enabling end of the fully differential operational amplifier is low;
the first switch and the second switch are connected with a third output of the clock generation submodule, and the third switch, the twelfth switch and the thirteenth switch are connected with a fourth output of the clock generation submodule; the clock pulse output by the clock generation submodule controls the first switch, the second switch, the third switch, the twelfth switch and the thirteenth switch to be switched on or switched off, and the five switches are all switched on when the clock pulse is at a high level;
the first feedback integration submodule comprises a fourth switch, a fifth switch, a sixth switch, a seventh switch and a first feedback capacitor, the fourth switch is connected with the positive feedback end of the delta-sigma modulator circuit, the fifth switch is connected with the negative feedback end of the delta-sigma modulator circuit, the other end of the fifth switch, one end of the first feedback capacitor and one end of the sixth switch are connected with the other end of the fourth switch, one end of the seventh switch and one end of the first switch are connected with the other end of the first feedback capacitor, and the other end of the sixth switch and the other end of the seventh switch are connected with an external common mode level;
the second feedback integration submodule comprises an eighth switch, a ninth switch, a tenth switch, an eleventh switch and a second feedback capacitor, the eighth switch is connected with the positive feedback end of the delta-sigma modulator circuit, the ninth switch is connected with the negative feedback end of the delta-sigma modulator circuit, the other end of the ninth switch, one end of the second feedback capacitor and one end of the tenth switch are connected with the other end of the eighth switch, one end of the eleventh switch and one end of the second switch are connected with the other end of the second feedback capacitor, and the other ends of the tenth switch and the eleventh switch are connected with an external common mode level;
the fourth switch is connected with the negative end of the delta-sigma modulator circuit one-bit quantizer, the fifth switch is connected with the positive end of the delta-sigma modulator circuit one-bit quantizer, the sixth switch is connected with the second output end of the clock generation submodule, and the seventh switch is connected with the first output end of the clock generation submodule; the eighth switch is connected with the positive end of the delta-sigma modulator circuit one-bit quantizer, the ninth switch is connected with the negative end of the delta-sigma modulator circuit one-bit quantizer, the tenth switch is connected with the second output end of the clock generation submodule, and the eleventh switch is connected with the first output end of the clock generation submodule.
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| CN111510082B (en) * | 2020-04-13 | 2023-11-03 | 芯浦(苏州)传感科技有限公司 | High-resolution gain-adjustable low-noise switched capacitor amplifier and design method thereof |
| CN111510150A (en) * | 2020-04-21 | 2020-08-07 | 北京新岸线移动多媒体技术有限公司 | Novel Sigma-Delta modulator |
| US11444635B2 (en) | 2020-10-02 | 2022-09-13 | Texas Instruments Incorporated | Delta sigma modulator |
| CN112187281B (en) * | 2020-10-03 | 2022-04-26 | 天津理工大学 | Switched capacitor oversampling delta-sigma modulator circuit |
| CN115882864A (en) * | 2021-09-29 | 2023-03-31 | 圣邦微电子（北京）股份有限公司 | Switch capacitor integrator circuit capable of preventing overshoot and undershoot |
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| "三阶Delta-Sigma调制器的设计";吴晓波等;《万方学位论文》;20090609;参见全文 * |
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| CN110875742A (en) | 2020-03-10 |
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