CN111510150A - Novel Sigma-Delta modulator - Google Patents
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Abstract
The invention discloses a novel Sigma-Delta modulator, which comprises an integrator, a quantizer, a selector and a feedback digital-to-analog converter, wherein the quantizer is used for performing quantization; the control end of the selector selects an analog-digital conversion working mode or a digital-analog conversion working mode through the switches included by the integrator, the Sigma-Delta modulator can be applied to a transmitter and a receiver, the analog-digital conversion working mode is selected at the receiver end, the digital-analog conversion working mode is selected at the transmitter end, and the chip area can be saved and the power consumption can be reduced through multiplexing of digital-analog converters in the Sigma-Delta modulator.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a novel Sigma-Delta modulator.
Background
In communication systems such as 2G/3G/4G/5G, or WiFi, a sigma-delta modulator is usually used in the receiver RX for analog-to-digital conversion, and a current steering digital-to-analog converter is used in the transmitter TX for digital-to-analog conversion, as shown in FIG. 1, the system includes an antenna ANT (antenna), a low Noise Amplifier L NA (L ow Noise Amplifier), a MIXER MIXER, a low Pass Filter L PF (L ow Pass Filter), and a programmable Gain Amplifier PGA (programmable Gain Amplifier).
Since the transmitter TX and the receiver RX belong to two relatively independent paths, in a general design, the digital-to-analog converter DAC in the transmitter TX and the analog-to-digital converter ADC in the receiver RX are generally designed separately. However, in a half-duplex communication system such as WiFi, the digital-to-analog converter DAC and the analog-to-digital converter ADC do not work simultaneously, and the analog-to-digital converter ADC mostly uses a sigma-delta modulator, fig. 2 is a structure diagram of a 1 st order single-loop N-bit sigma-delta modulator in the prior art, and fig. 2 shows that the digital-to-analog converter DAC is included in a conventional sigma-delta modulator.
Disclosure of Invention
In view of this, the present invention provides a novel Sigma-Delta modulator, which has an analog-to-digital conversion operating mode and a digital-to-analog conversion operating mode, and can be applied to a transmitter TX and a receiver RX, wherein the analog-to-digital conversion operating mode is selected at the receiver RX end, the digital-to-analog conversion operating mode is selected at the transmitter TX end, and the chip area and the power consumption can be reduced by multiplexing the digital-to-analog converters in the Sigma-Delta modulator.
The novel Sigma-Delta modulator comprises: an integrator, a quantizer, a selector and a feedback digital-to-analog converter;
the input end of the integrator is connected with the port of the first input signal line, and the output end of the integrator is connected with the input end of the quantizer; the first input end of the selector is connected with the output end of the quantizer, the second input end of the selector is connected with the port of the second input signal line, and the output end of the selector is connected with the input end of the feedback digital-to-analog converter; the output end of the feedback digital-to-analog converter is connected with the input end of an operational amplifier of the integrator;
the integrator comprises a first switch S1 connected with a first resistor R1 and the positive input end of the operational amplifier, a second switch S2 connected with a second resistor R2 and the negative input end of the operational amplifier, a third switch S3, a fourth switch S4, a first feedback resistor R3 and a second feedback resistor R4; the third switch S3 is connected in series with the first feedback resistor R3 and then connected in parallel with the first feedback capacitor C1, and the fourth switch S4 is connected in series with the second feedback resistor R4 and then connected in parallel with the second feedback capacitor C2;
the first switch S1 and the second switch S2 are used for controlling the on-off between the integrator and the first input signal;
the first switch S1 and the second switch S2 are closed, the third switch S3 and the fourth switch S4 are opened, the control end of the selector selects the first input end, and the Sigma-Delta modulator works in an analog-to-digital conversion working mode;
the first switch S1 and the second switch S2 are opened, the third switch S3 and the fourth switch S4 are closed, the control end of the selector selects the second input end, and the Sigma-Delta modulator works in a digital-to-analog conversion working mode.
The first input signal is an analog differential input signal in an analog-to-digital conversion working mode;
the second input signal is an input digital signal in a digital-to-analog conversion working mode.
Further, in the above-mentioned case,
the positive input of the operational amplifier of the integrator is connected to the port of the first input signal line through a first resistor R1 connected in series with a first switch S1, and the negative input is connected to the port of the first input signal line through a second resistor R2 connected in series with a second switch S2;
the input end of the operational amplifier is connected with the output end of the feedback digital-to-analog converter;
the output end of the operational amplifier is connected with the input end of the quantizer, and the analog differential voltage signal output by the integrator is configured to the quantizer.
The quantizer is configured to quantize the analog differential voltage signal output by the integrator, output an N-bit digital signal, and configure the N-bit digital signal to the selector;
the selector is configured to selectively input the N-bit digital signal output by the quantizer or the second input signal to the input end of the feedback digital-to-analog converter;
and the feedback digital-to-analog converter is configured to perform digital-to-analog conversion on the N-bit digital signal input by the selector or the second input signal and feed back the output analog signal to the integrator.
The integrator configured to:
in the analog-to-digital conversion working mode, a first input signal is input to the operational amplifier through the first switch S1, the second switch S2, the first resistor R1 and the second resistor R2, and the operational amplifier, the first feedback capacitor C1 and the second feedback capacitor C2 integrate the first input signal according to a feedback analog signal output by the feedback digital-to-analog converter;
when in a digital-to-analog conversion working mode, the first feedback resistor R3 and the second feedback resistor R4 are connected to the input end and the output end of the operational amplifier; the first feedback resistor R3, the second feedback resistor R4, the first feedback capacitor C1, the second feedback capacitor C2 and the operational amplifier constitute an integrator for integrating the output signal of the feedback digital-to-analog converter.
And when the quantizer works in the digital-to-analog conversion mode, the sampling switch of the quantizer is switched off, and the quantizer does not work.
In the analog-to-digital conversion working mode: the integrator integrates the first input signal, and the quantizer quantizes the output signal of the integrator and outputs an N-bit digital signal; the selector selects and inputs the N-bit digital signal output by the quantizer to the input end of the feedback digital-to-analog converter, the feedback digital-to-analog converter performs digital-to-analog conversion on the N-bit digital signal input by the selector, and the output analog signal is fed back to the integrator; the output signal of the Sigma-Delta modulator is an N-bit digital signal output by the quantizer;
in the digital-to-analog conversion working mode: the sampling switch of the quantizer is switched off, and the quantizer does not work; the selector selects a second input end through the control end, a second input signal is input to the input end of the feedback digital-to-analog converter, the feedback digital-to-analog converter performs digital-to-analog conversion on the second input signal input by the selector, and the output analog signal is input to the integrator; the integrator integrates the analog signal output by the feedback digital-to-analog converter and outputs an analog differential voltage signal, wherein the analog differential voltage signal is the output signal of the Sigma-Delta modulator.
The beneficial effects obtained by the invention are as follows:
1. the novel Sigma-Delta modulator is easy to realize, and can be realized by only adding four switches and one selector on the basis of the traditional Sigma-Delta modulator;
2. the novel Sigma-Delta modulator provided by the invention realizes the multiplexing of a digital-to-analog conversion module DAC contained in the traditional Sigma-Delta modulator, can save the chip area and reduce the power consumption;
3. the novel Sigma-Delta modulator provided by the invention can be simultaneously applied to a transmitting end and a receiving end, and can realize digital-to-analog conversion in a transmitter and analog-to-digital conversion in a receiver in a communication system by switching different working modes;
4. the quantizer in the invention adopts asynchronous SAR ADC, which can greatly save power consumption and area, and is easy to realize the migration between different processes.
For the purposes of the foregoing and related ends, the one or more embodiments include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects and are indicative of but a few of the various ways in which the principles of the various embodiments may be employed. Other benefits and novel features will become apparent from the following detailed description when considered in conjunction with the drawings and the disclosed embodiments are intended to include all such aspects and their equivalents.
Drawings
FIG. 1 is a schematic diagram of a prior art transmitter and receiver configuration;
FIG. 2 is a block diagram of a conventional 1-order single-loop N-bit Sigma-Delta modulator in the prior art;
FIG. 3 is a block diagram of a novel Sigma-Delta modulator according to the present invention;
fig. 4 is an internal structure diagram of a 10-bit asynchronous SAR ADC according to the present invention;
FIG. 5 is a schematic structural diagram of a continuous-time analog-to-digital conversion operation mode provided by the present invention;
FIG. 6 is a schematic structural diagram of a digital-to-analog conversion operation mode provided by the present invention;
FIG. 7 is a diagram of an array of adjustable capacitors C1, C2 according to the present invention.
Detailed Description
The following description and the drawings sufficiently illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. The scope of embodiments of the invention encompasses the full ambit of the claims, as well as all available equivalents of the claims. Embodiments of the invention may be referred to herein, individually or collectively, by the term "invention" merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed.
The present invention provides a novel Sigma-Delta modulator, which has an analog-to-digital conversion operating mode and a digital-to-analog conversion operating mode, and can realize digital-to-analog conversion in a transmitter and analog-to-digital conversion in a receiver in a communication system by switching different operating modes, as shown in fig. 3, including:
the analog-digital conversion working mode in the invention is a continuous time type analog-digital conversion working mode;
an integrator U1, a quantizer U2, a selector U3, and a feedback digital-to-analog converter U4;
the input end of the integrator U1 is connected with a first input signal line port, and the output end of the integrator U1 is connected with the input end of the quantizer U2; the output end of the quantizer U2 is connected with the input end of the selector U3; the first input end of the selector U3 is connected with the output end of the quantizer, the second input end is connected with the port of the second input signal line, and the output end is connected with the input end of the feedback digital-to-analog converter U4; the output end of the feedback digital-to-analog converter U4 is connected with the input end of an operational amplifier of the integrator U1;
specifically, the integrator U1 includes: a first switch S1, a second switch S2, a first resistor R1, a second resistor R2, a third switch S3, a fourth switch S4, a first feedback resistor R3, a second feedback resistor R4 and an operational amplifier AMP;
the first switch S1 is connected to the first resistor R1 and the positive input terminal of the operational amplifier, and the second switch is connected to the second resistor R2 and the negative input terminal of the operational amplifier;
the third switch S3 is connected in series with the first feedback resistor R3 and then connected in parallel with the first feedback capacitor C1, and the fourth switch S4 is connected in series with the second feedback resistor R4 and then connected in parallel with the second feedback capacitor C2;
the first adjustable capacitor C1 and the second adjustable capacitor C2 are used for adjusting the signal bandwidth of the integrator;
the positive input of the operational amplifier is connected to the first input signal line port through a first resistor R1 in series with a first switch S1, and the negative input through a second resistor R2 in series with a second switch S2.
The positive output end of the integrator U1 is connected with the positive input end of the quantizer U2, and the negative output end of the integrator U1 is connected with the negative input end of the quantizer U2; the positive output end of the feedback digital-to-analog converter U4 is connected with the negative input end of the operational amplifier; the negative output end of the feedback digital-to-analog converter U4 is connected with the positive input end of the operational amplifier;
the first input signal is an analog differential input signal in a continuous time analog-to-digital conversion working mode;
the second input signal is an input digital signal in a digital-to-analog conversion working mode.
The quantizer U2 is configured to quantize the output signal of the integrator, output an N-bit digital signal, and configure the N-bit digital signal to the selector;
and when the quantizer works in the digital-to-analog conversion mode, the sampling switch of the quantizer is switched off, and the quantizer does not work.
The selector U3 is configured to selectively input the N-bit digital signal output by the quantizer or the second input signal to the input end of the feedback digital-to-analog converter;
specifically, when the continuous time type analog-digital conversion work mode is adopted, the first input end is selected through the control end, and the N-bit digital signal output by the quantizer is input to the input end of the feedback digital-analog converter; and when the digital-to-analog conversion work mode is adopted, the second input end is selected by the control end to access the second input signal, and the second input signal is input to the input end of the feedback digital-to-analog converter.
The feedback digital-to-analog converter U4 is configured to perform digital-to-analog conversion on the N-bit digital signal input by the selector, or the second input signal, and input the output analog signal to the integrator:
specifically, the analog-to-digital conversion circuit is used for feeding back an integrator, performing digital-to-analog conversion on an N-bit digital signal input by a selector and feeding back an output analog signal to the integrator when in a continuous time type analog-to-digital conversion working mode; and when the digital-to-analog conversion work mode is adopted, the digital-to-analog conversion work mode is used for carrying out digital-to-analog conversion on the second input signal and inputting the output analog signal to the integrator.
The integrator configured to:
when the continuous time type analog-digital conversion work mode is adopted, the first switch S1 and the second switch S2 are closed, the third switch S3 and the fourth switch S4 are opened, and a first input signal is input to the operational amplifier through the first switch S1, the second switch S2, the first resistor R1 and the second resistor R2; the operational amplifier, the first feedback capacitor C1 and the second feedback capacitor C2 integrate the first input signal according to the feedback analog signal output by the feedback digital-to-analog converter;
when in a digital-to-analog conversion working mode, the first switch S1 and the second switch S2 are opened, the third switch S3 and the fourth switch S4 are closed, and the first feedback resistor R3 and the second feedback resistor R4 are connected to the input end and the output end of the operational amplifier; the first feedback resistor R3, the second feedback resistor R4, the first feedback capacitor C1, the second feedback capacitor C2, and the operational amplifier constitute an integrator, which integrates the output signal of the feedback digital-to-analog converter.
Specifically, the N-bit quantizer U2 is implemented by using an asynchronous SAR ADC, fig. 4 is a 10-bit asynchronous SAR ADC structure diagram, and the asynchronous SAR ADC is used to design a high-speed ADC in a low-node process, so that the area can be greatly saved, the power consumption can be reduced, and the migration between different processes can be easily implemented, thereby implementing the optimization of the power consumption and the area.
The output end of the integrator U1 is connected with an N-bit quantizer, and the N-bit quantizer is used for quantizing the analog differential voltage signal output by the integrator;
outputting an N-bit binary digital code DOUT _ ADC through a quantizer, wherein the N-bit digital code DOUT _ ADC and a digital input code DIN _ DAC of a digital-to-analog conversion working mode are input into a selector together;
the selector is an alternative switch U3, the selector U3 selects the quantizer to output an N-bit binary digital code DOUT _ ADC or a digital input code DIN _ DAC of a digital-to-analog conversion working mode under different working modes, and outputs the digital input code DIN _ DAC to the feedback digital-to-analog converter;
the Sigma-Delta modulator in the invention has a continuous time type analog-digital conversion working mode and a digital-analog conversion working mode, and is called as a continuous time type ADC working mode and a DAC working mode for short:
the specific connection mode of the circuit is as follows:
the first input signal, namely an analog differential input signal VIP _ ADC is connected to a first resistor R1, VIN _ ADC is connected to a second resistor R2, the other end of R1 is connected to a first switch S1, the other end of R2 is connected to a second switch S2, the other end of S1 is connected to the positive input terminal of the operational amplifier AMP, and the other end of S2 is connected to the negative input terminal of the operational amplifier AMP;
the first feedback resistor R3 and the third switch S3 are connected in series and then connected with the first feedback capacitor C1 in parallel: r3 and S3 form a first series circuit having one end connected to the positive input terminal of the operational amplifier AMP and the other end connected to the negative output terminal of the AMP; one end of the first adjustable capacitor C1 is connected with the positive input end of the operational amplifier AMP, and the other end is connected with the negative output end of the AMP;
the second feedback resistor R4 and the fourth switch S4 are connected in series and then connected with the second feedback capacitor C2 in parallel: r4 and S4 form a second series circuit having one end connected to the negative input terminal of the operational amplifier AMP and the other end connected to the positive output terminal of the AMP; one end of the second adjustable capacitor C2 is connected with the negative input end of the operational amplifier AMP, and the other end is connected with the positive output end of the AMP;
the positive output end of the operational amplifier is connected with the positive input end of the quantizer U2, and the negative output end of the operational amplifier is connected with the negative input end of the quantizer;
the selector U3 includes: the control end, the first input end and the second input end; a first input end of the selector U3 is connected to the output end of the quantizer U2, and a second input end is connected to a second input signal line port, i.e., the input signal DIN _ DAC in the DAC operating mode;
the output end of the selector U3 is connected with the input end of the feedback digital-to-analog converter U4;
the positive output end of the feedback digital-to-analog converter is connected with the negative input end of the operational amplifier AMP, and the negative output end of the feedback digital-to-analog converter is connected with the positive input end of the operational amplifier AMP.
The specific working mechanism of the two working modes is as follows:
1) in the continuous time type ADC working mode: the novel Sigma-Delta modulator is applied to a receiver RX, and implements an analog-to-digital conversion function to convert an analog differential input signal into an N-bit binary digital code, as shown in fig. 5:
the first switch S1 and the second switch S2 are closed, the analog differential input signals VIP _ ADC and VIN _ ADC are connected to the operational amplifier through the resistors R1 and R2, the third switch S3 and the fourth switch S4 are opened, and the operation part in the integrator comprises: s1, S2, R1, R2, C1, C2 and an operational amplifier; the third switch S3, the fourth switch S4, the first feedback resistor R3 and the second feedback resistor R4 do not work;
the sampling switch of the quantizer is switched on or switched off according to a sampling clock C L K1, when the sampling clock C L K1 is 1 in the graph of FIG. 4, the sampling switch is switched off, the switches S1 and S2 are connected with Vip and Vin, and the quantizer U2 normally works;
the selector is an alternative switch U3, and selects a second input end through a control end in the selector, namely selects a quantizer output signal, namely selects a 1 path in fig. 5, and outputs the N-bit binary digital code DOUT _ ADC;
the N-bit binary digital code DOUT _ ADC is input to the feedback digital-to-analog converter, the feedback digital-to-analog converter performs digital-to-analog conversion on the N-bit binary digital code DOUT _ ADC, analog differential signals are output, the analog differential signals are respectively fed back and connected to an analog input differential end of the operational amplifier U1, and an integrator is fed back;
under the continuous time type ADC working mode, an input signal is an analog signal input by an input end of the integrator, an output signal is an N-bit digital signal DOUT _ ADC output by the quantizer, and the novel Sigma-Delta modulator realizes the function of a first-order N-bit continuous time Sigma-Delta modulator.
2) The novel Sigma-Delta modulator in DAC mode is applied to a transmitter TX, and implements a digital-to-analog conversion function to convert an input signal in DAC mode, i.e. a digital input code DIN _ DAC, into an analog differential voltage signal, as shown in fig. 6:
the first switch S1 and the second switch S2 are opened, the third switch S3 and the fourth switch S4 are closed, and the part of the integrator which works comprises the following steps: s3, S4, R3, R4, C1, C2 and an operational amplifier; the first switch S1, the second switch S2, the first resistor R1 and the second resistor R2 do not work;
a sampling switch of the quantizer U2 is turned on, namely, an input switch in FIG. 4 is connected to Vref, the quantizer U2 is in a power-off state, namely, the PD1 is set to 1, a power-off working mode is activated, and the quantizer U2 does not work;
the input of the selector is a digital input code DIN _ DAC of the DAC working mode, the control end in the selector selects the second input end to select the digital input code DIN _ DAC, namely a 0 path in FIG. 6 is selected, and the selector outputs an N-bit binary digital code DIN _ DAC;
inputting the N-bit binary digital code DIN _ DAC into a feedback digital-to-analog converter, performing digital-to-analog conversion on the N-bit binary digital code DIN _ DAC by the feedback digital-to-analog converter, outputting an analog differential signal, and inputting the analog differential signal into an analog input differential end of an operational amplifier U1;
an integrator in the form of a transconductance amplifier (OTA) is formed by the operational amplifier U1 and its feedback elements S3, S4, C1, C2, R3 and R4, converting the output analog differential signal of the feedback digital-to-analog converter into analog differential voltage signals VON _ DAC and VOP _ DAC;
under the DAC working mode, the input signal is a digital signal DIN _ DAC input by a second selection end of the selector, and the output signals are analog differential voltage signals VON _ DAC and VOP _ DAC output by the integrator;
it should be noted that the first adjustable capacitor C1 and the second adjustable capacitor C2 are used to adjust the signal bandwidth of the integrator, and are adjustable in both modes, and both C1 and C2 are adjusted by using binary capacitor arrays to cover the large change in capacitance under the process angle, which results in the excessive change in the signal bandwidth of the integrator, and the capacitor arrays are shown in fig. 7.
Those of skill in the art will understand that the various exemplary method steps and apparatus elements described in connection with the embodiments disclosed herein can be implemented as electronic hardware, software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative steps and elements have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method described in connection with the embodiments disclosed above may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a subscriber station. In the alternative, the processor and the storage medium may reside as discrete components in a subscriber station.
The disclosed embodiments are provided to enable those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the scope or spirit of the invention. The above-described embodiments are merely preferred embodiments of the present invention, which should not be construed as limiting the invention, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. A novel Sigma-Delta modulator is characterized by comprising an integrator, a quantizer, a selector and a feedback digital-to-analog converter;
the output end of the integrator is connected with the input end of the quantizer; the first input end of the selector is connected with the output end of the quantizer, the second input end of the selector is connected with the port of the second input signal line, and the output end of the selector is connected with the input end of the feedback digital-to-analog converter; the output end of the feedback digital-to-analog converter is connected with the input end of an operational amplifier of the integrator;
the integrator includes: a first switch (S1) connected to the first resistor (R1) and the positive input end of the operational amplifier, a second switch (S2) connected to the second resistor (R2) and the negative input end of the operational amplifier, a third switch (S3), a fourth switch (S4), a first feedback resistor (R3) and a second feedback resistor (R4); the third switch (S3) is connected in series with the first feedback resistor (R3) and then connected in parallel with the first feedback capacitor (C1), and the fourth switch (S4) is connected in series with the second feedback resistor (R4) and then connected in parallel with the second feedback capacitor (C2);
the first switch (S1) and the second switch (S2) are closed, the third switch (S3) and the fourth switch (S4) are opened, the control end of the selector selects the first input end, and the Sigma-Delta modulator works in an analog-to-digital conversion working mode;
the first switch (S1) and the second switch (S2) are opened, the third switch (S3) and the fourth switch (S4) are closed, the control end of the selector selects the second input end, and the Sigma-Delta modulator works in a digital-to-analog conversion working mode.
2. The novel Sigma-Delta modulator of claim 1 wherein,
the input end of the integrator is connected with a first input signal line port;
the first switch (S1) and the second switch (S2) are used for controlling the connection and disconnection between the integrator and the first input signal.
3. The novel Sigma-Delta modulator of claim 1 wherein,
the first input signal is an analog differential input signal in an analog-to-digital conversion working mode;
the second input signal is an input digital signal in a digital-to-analog conversion working mode.
4. The novel Sigma-Delta modulator of claim 1 wherein,
the quantizer is configured to quantize the analog differential voltage signal output by the integrator, output an N-bit digital signal, and configure the N-bit digital signal to the selector;
the selector is configured to selectively input the N-bit digital signal output by the quantizer or the second input signal to the input end of the feedback digital-to-analog converter;
and the feedback digital-to-analog converter is configured to perform digital-to-analog conversion on the N-bit digital signal input by the selector or the second input signal and feed back the output analog signal to the integrator.
5. The novel Sigma-Delta modulator of claim 4, wherein the integrator is configured to:
in the analog-to-digital conversion operation mode, a first input signal is input to the operational amplifier through the first switch (S1), the second switch (S2), the first resistor (R1) and the second resistor (R2); the operational amplifier, the first feedback capacitor (C1) and the second feedback capacitor (C2) integrate the first input signal according to the feedback analog signal output by the feedback digital-to-analog converter;
in the digital-to-analog conversion working mode, the first feedback resistor (R3) and the second feedback resistor (R4) are connected to the operational amplifier through the third switch (S3) and the fourth switch (S4), and form an integrator with the first feedback capacitor (C1), the second feedback capacitor (C2) and the operational amplifier to integrate the output signal of the feedback digital-to-analog converter.
6. The novel Sigma-Delta modulator of claim 4 wherein the selector,
when the analog-digital conversion is in a working mode, the control end selects the first input end, and the N-bit digital signal output by the quantizer is input to the input end of the feedback digital-analog converter;
and when the digital-to-analog conversion work mode is adopted, the second input end is selected by the control end to access the second input signal, and the second input signal is input to the input end of the feedback digital-to-analog converter.
7. The novel Sigma-Delta modulator of claim 4 wherein the feedback digital-to-analog converter,
when in the analog-to-digital conversion working mode, the digital-to-analog conversion device is used for feeding back the integrator, performing digital-to-analog conversion on the N-bit digital signal input by the selector, and feeding back the output analog signal to the integrator;
and when the digital-to-analog conversion work mode is adopted, the digital-to-analog conversion work mode is used for carrying out digital-to-analog conversion on the second input signal and inputting the output analog signal to the integrator.
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