CN112968703A - Control circuit of analog-to-digital converter and electronic equipment - Google Patents
Control circuit of analog-to-digital converter and electronic equipment Download PDFInfo
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- CN112968703A CN112968703A CN202110542254.6A CN202110542254A CN112968703A CN 112968703 A CN112968703 A CN 112968703A CN 202110542254 A CN202110542254 A CN 202110542254A CN 112968703 A CN112968703 A CN 112968703A
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- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
Abstract
The disclosure relates to a control circuit and an electronic device of an analog-to-digital converter, so as to improve the signal conversion efficiency of the analog-to-digital converter. The control circuit includes: the device comprises an analog-to-digital converter, a pulse comparison unit and a control unit, wherein analog signals to be converted are respectively used as input signals of the analog-to-digital converter and the pulse comparison unit; the pulse comparison unit is connected with the control unit and used for determining whether the amplitude of the analog signal to be converted is within the preset range of the analog-to-digital converter according to the analog signal to be converted and the reference signal, generating a judgment signal according to the determination result and sending the judgment signal to the control unit, wherein the reference signal is determined based on the preset range; the control unit is connected with the analog-to-digital converter and used for receiving the judgment signal and outputting a corresponding control instruction to the analog-to-digital converter according to the judgment signal so as to control the working state of a target integrator in the analog-to-digital converter, wherein the target integrator is any one or more integrators in the analog-to-digital converter.
Description
Technical Field
The present disclosure relates to the field of integrated circuit design, and in particular, to a control circuit of an analog-to-digital converter and an electronic device.
Background
Because the Sigma-Delta analog-to-digital converter has the advantages of easy driving, high precision and wide bandwidth, the analog-to-digital converter is usually adopted in a broadband power line carrier (HPLC) communication module to realize the acquisition, amplification and conversion of an analog communication signal into a digital signal for a digital system to perform signal processing. This type of analog-to-digital converter comprises a feedback loop which oscillates when an overload occurs when the amplitude of the analog signal to be converted is large. When the overload condition disappears, the feedback loop may or may not be able to recover automatically after waiting several clock cycles. When the feedback loop is not recovered, the output signal of the analog-to-digital converter is damaged, the signal-to-noise ratio is seriously reduced, the analog-to-digital converter cannot work effectively, and the signal conversion efficiency is poor.
Disclosure of Invention
The present disclosure provides a control circuit and an electronic device of an analog-to-digital converter to improve signal conversion efficiency of the analog-to-digital converter.
In order to achieve the above object, a first aspect of the present disclosure provides a control circuit of an analog-to-digital converter, including: the device comprises an analog-to-digital converter, a pulse comparison unit and a control unit, wherein analog signals to be converted are respectively used as input signals of the analog-to-digital converter and the pulse comparison unit;
the pulse comparison unit is connected with the control unit and used for determining whether the amplitude of the analog signal to be converted is within a preset range of the analog-to-digital converter according to the analog signal to be converted and a reference signal, generating a decision signal according to a determination result and sending the decision signal to the control unit, wherein the reference signal is determined based on the preset range;
the control unit is connected with the analog-to-digital converter and used for receiving the decision signal and outputting a corresponding control instruction to the analog-to-digital converter according to the decision signal so as to control the working state of a target integrator in the analog-to-digital converter, wherein the target integrator is any one or more integrators in the analog-to-digital converter.
Optionally, the pulse comparing unit is configured to generate an enable decision signal for characterizing that the target integrator is in an enable state when the determination result indicates that the amplitude of the analog signal to be converted is within the preset range, and generate a disable decision signal for characterizing that the target integrator is in a disable state when the determination result indicates that the amplitude of the analog signal to be converted exceeds the preset range;
the control unit is configured to output an enable instruction to the analog-to-digital converter to control the target integrator to be in an enable state when the decision signal is the enable decision signal, and output a disable instruction to the analog-to-digital converter to control the target integrator to be in a disable state when the decision signal is the disable decision signal.
Optionally, the pulse comparing unit includes a first pulse comparing unit and a second pulse comparing unit, where a signal input by a positive input end of the first pulse comparing unit is the same as a signal input by a negative input end of the second pulse comparing unit, and a signal input by the negative input end of the first pulse comparing unit is the same as a signal input by a positive input end of the second pulse comparing unit;
the first pulse comparison unit is connected with the control unit and used for generating a first decision signal according to the analog signal to be converted and the reference signal and sending the first decision signal to the control unit;
the second pulse comparison unit is connected with the control unit and used for generating a second decision signal according to the analog signal to be converted and the reference signal and sending the second decision signal to the control unit;
the control unit is configured to output a corresponding control instruction to the analog-to-digital converter according to the first decision signal and the second decision signal.
Optionally, the control unit includes an or gate circuit, an input end of the or gate circuit is connected to the first pulse comparing unit and the second pulse comparing unit, respectively, and an output end of the or gate circuit is connected to the analog-to-digital converter.
Optionally, the control unit is further configured to control the analog-to-digital converter to output a signal with an amplitude value equal to a first preset value when the first decision signal indicates that the target integrator is controlled to be in a disable enable state.
Optionally, the control unit includes a not-gate circuit and a nor-gate circuit, an output end of the second pulse comparing unit is connected to an input end of the not-gate circuit, an output end of the not-gate circuit and an output end of the first pulse comparing unit are connected to an input end of the nor-gate circuit, and an output end of the nor-gate circuit is connected to the analog-to-digital converter, and is configured to control the analog-to-digital converter to output a signal whose amplitude is a second preset value when the second decision signal indicates that the target integrator is controlled to be in the disable enable state.
Optionally, the analog-to-digital converter comprises MOS switches, wherein each target integrator is connected in parallel with at least one MOS switch;
the gate of the MOS switch is connected with the control unit and used for controlling the target integrator to be in an enabling state when the control unit outputs an enabling instruction, and controlling the target integrator to be in a disabling state when the control unit outputs a disabling instruction.
Optionally, the pulse comparison unit comprises a fully differential comparator and a pulse width adjuster;
the input end of the fully differential comparator is respectively input with the analog signal to be converted and the reference signal, and is used for determining whether the amplitude of the analog signal to be converted is within the preset range of the analog-to-digital converter, and generating a pulse signal according to the determination result;
and the input end of the pulse width regulator is connected with the output end of the fully differential comparator and is used for adjusting the pulse width of the pulse signal to a preset pulse width to obtain the judgment signal, wherein the preset pulse width is determined based on the capacitance of the target integrator.
Optionally, the analog-to-digital converter is a Sigma-Delta type analog-to-digital converter.
The second aspect of the present disclosure also provides an electronic device, including: the control circuit of the analog-to-digital converter provided by the first aspect of the disclosure.
According to the technical scheme, the pulse comparison unit determines whether the amplitude of the analog signal to be converted is within the preset range of the analog-to-digital converter or not, and generates a decision signal according to the determination result, so that the control unit controls the working state of a target integrator in the analog-to-digital converter according to the decision signal. Therefore, the working state of the target integrator can be dynamically reset according to the amplitude of the analog signal to be converted, on one hand, the oscillation of the analog-to-digital converter can be effectively avoided when overload occurs, the stability of the analog-to-digital converter is improved, and the signal conversion efficiency of the analog-to-digital converter is improved. On the other hand, the normal operation of the analog-digital converter can be ensured when overload does not occur.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure.
Fig. 1 is a schematic diagram illustrating a control circuit of an analog-to-digital converter according to an exemplary embodiment.
Fig. 2 is a schematic diagram illustrating another control circuit of an analog-to-digital converter in accordance with an exemplary embodiment.
Detailed Description
In the related art, in order to avoid the output signal of the analog-to-digital converter from being damaged, the amplitude of the input signal of the analog-to-digital converter (i.e., the analog signal to be converted) is usually controlled to be much smaller than the range of the analog-to-digital converter, so as to ensure that the analog-to-digital converter is not overloaded under any condition. However, this method may cause the analog-to-digital converter to convert only the analog signal with a smaller amplitude, and not convert the analog signal with a larger amplitude, that is, the performance of the analog-to-digital converter is used to replace the stability of the output signal of the analog-to-digital converter, so that the application range of the analog-to-digital converter is greatly reduced, and the signal conversion efficiency is poor.
In view of this, the present disclosure provides a control circuit and an electronic device of an analog-to-digital converter to improve signal conversion efficiency of the analog-to-digital converter.
The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present disclosure, are given by way of illustration and explanation only, not limitation.
Fig. 1 is a schematic diagram illustrating a control circuit of an analog-to-digital converter according to an exemplary embodiment. As shown in fig. 1, the control circuit may include an analog-to-digital converter 100, a pulse comparison unit 200, and a control unit 300, wherein analog signals to be converted are input signals of the analog-to-digital converter 100 and the pulse comparison unit 200, respectively.
Specifically, the pulse comparing unit 200 is connected to the control unit 300, and configured to determine whether the amplitude of the analog signal to be converted is within the preset range of the analog-to-digital converter 100 according to the analog signal to be converted and the reference signal, generate a decision signal according to a determination result, and then send the decision signal to the control unit 300. The control unit 300 is connected to the analog-to-digital converter 100, and configured to receive the decision signal, and output a corresponding control instruction to the analog-to-digital converter according to the decision signal, so as to control a working state of a target integrator in the analog-to-digital converter. The operating state may include an enable state and a disable state, among others.
In the present disclosure, the reference signal is determined based on a preset range. For example, the analog-to-digital converter and the pulse comparison unit are all fully differential circuits, the analog signals to be converted may be denoted as differential signals VINP and VINN, and the reference signals may be denoted as a first reference signal VREFP and a second reference signal VREFN. Assuming that the predetermined range of the adc 100 is-1V, if the common mode voltage VCM =1.65V, the first reference signal VREFP =1.65+0.5V =2.15V, and the second reference signal VREFN =1.65-0.5V = 1.15V. It is worth noting that both the analog signal and the reference signal described in the present disclosure can be represented in the form of voltage.
In the present disclosure, at least one integrator is included in the analog-to-digital converter 100, and the target integrator is any one or more integrators. For example, the analog-to-digital converter 100 includes three integrators, which are respectively referred to as a first stage integrator, a second stage integrator, and a third stage integrator, and the target integrator may be any one or more of the three integrators, which is not specifically limited by the present disclosure.
By adopting the technical scheme, the pulse comparison unit determines whether the amplitude of the analog signal to be converted is within the preset range of the analog-to-digital converter or not, and generates a decision signal according to the determination result, so that the control unit controls the working state of a target integrator in the analog-to-digital converter according to the decision signal. Therefore, the working state of the target integrator can be dynamically reset according to the amplitude of the analog signal to be converted, on one hand, the oscillation of the analog-to-digital converter can be effectively avoided when overload occurs, the stability of the analog-to-digital converter is improved, and the signal conversion efficiency of the analog-to-digital converter is improved. On the other hand, the normal operation of the analog-digital converter can be ensured when overload does not occur.
Illustratively, the pulse comparison unit 200 generates an enable decision signal for characterizing that the control target integrator is in an enable state when the determination result indicates that the amplitude of the analog signal to be converted is within the preset range, and generates a disable decision signal for characterizing that the control target integrator is in a disable state when the determination result indicates that the amplitude of the analog signal to be converted is beyond the preset range. Accordingly, the control unit 300 outputs an enable instruction to the analog-to-digital converter 100 to control the target integrator to be in the enable state when the decision signal is the enable decision signal, and outputs a disable instruction to the analog-to-digital converter to control the target integrator to be in the disable state when the decision signal is the disable decision signal.
Illustratively, following the above example, if VINP-VINN >2.15-1.15V =1V, the amplitude of the analog signal to be converted is represented to be out of the preset range, and then the pulse comparison unit 200 generates the disable enable decision signal. If VINP-VINN <1V, the amplitude representing the analog signal to be converted is within the preset range, and the pulse comparison unit 200 generates an enable decision signal.
It should be noted that, when the number of integrators in the enabled state is smaller, the analog-to-digital converter 100 is less likely to oscillate when being overloaded, that is, the stability of the analog-to-digital converter is better, and therefore, when the amplitude of the analog signal to be converted exceeds the preset range, that is, the analog-to-digital converter is overloaded, the number of integrators in the enabled state is reduced, the oscillation of the analog-to-digital converter can be effectively avoided, the stability of the analog-to-digital converter is improved, and the signal conversion efficiency of the analog-to-digital converter is further improved.
By adopting the technical scheme, the target integrator is controlled to be in the enable-forbidden state when overload occurs so as to reduce the number of integrators in the enable state in the analog-to-digital converter, and the target integrator is controlled to be in the enable state when the overload does not occur so as to increase the number of integrators in the enable state in the analog-to-digital converter.
In order to make the control circuit of the analog-to-digital converter provided by the present disclosure better understood, the control circuit is described in detail in the following with a complete embodiment. In the present disclosure, the control circuit may be described in the form of a fully differential circuit, or may be described in the form of a single-ended circuit. The control circuit is illustrated in the present disclosure in the form of a fully differential circuit.
Considering that the amplitude of the analog signal to be converted exceeds the preset range, the two scenarios may be included, in one scenario, the amplitude of the analog signal to be converted is greater than the preset range, and in the other scenario, the amplitude of the analog signal to be converted is smaller than the preset range, which may cause overload of the analog-to-digital converter in any of the scenarios.
Accordingly, the pulse comparing unit 200 in fig. 1 may include a first pulse comparing unit and a second pulse comparing unit. The signal input by the positive input end of the first pulse comparison unit is the same as the signal input by the negative input end of the second pulse comparison unit, and the signal input by the negative input end of the first pulse comparison unit is the same as the signal input by the positive input end of the second pulse comparison unit. For example, the first pulse comparison unit may be used to determine whether the amplitude of the analog signal to be converted is greater than the preset range, and the second pulse comparison unit may be used to determine whether the amplitude of the analog signal to be converted is less than the preset range. For another example, the first pulse comparing unit may be configured to determine whether the amplitude of the analog signal to be converted is smaller than the preset range, and the second pulse comparing unit may be configured to determine whether the amplitude of the analog signal to be converted is larger than the preset range.
Fig. 2 is a schematic diagram illustrating another control circuit of an analog-to-digital converter in accordance with an exemplary embodiment. As shown in fig. 2, the pulse comparing unit 200 may include a first pulse comparing unit 201 and a second pulse comparing unit 202, wherein the first pulse comparing unit 201 may be configured to determine that the amplitude of the analog signal to be converted is greater than the preset range, and the second pulse comparing unit 202 may be configured to determine that the amplitude of the analog signal to be converted is less than the preset range. That is, the positive output terminal of the first pulse comparing unit 201 is used for inputting the differential signal VINP, and the negative input terminal is used for inputting the differential signal VINN. The positive output terminal of the second pulse comparing unit 202 is used for inputting the differential signal VINN, and the negative input terminal is used for inputting the differential signal VINP.
The first pulse comparing unit 201 determines the magnitude relationship between (VINP-VINN) and (VREFP-VREFN) and generates a first decision signal. For example, when (VINP-VINN) > (VREFP-VREFN), the first decision signal Flag _ P =1 is generated for characterizing that the control target integrator is in the disable enable state, and otherwise, the first decision signal Flag _ P =0 is generated for characterizing that the control target integrator is in the enable state.
For example, the first pulse comparing unit 201 may include a first fully differential comparator 2011 and a first pulse width adjuster 2012. As shown in fig. 2, the input terminal of the first fully-differential comparator 2011 is used for inputting the analog signals to be converted (i.e., the differential signals VINP and VINN), and the reference signals (i.e., the first reference signal VREFP, the second reference signal VREFN), determining whether the amplitude of the analog signal to be converted is within a preset range of the analog-to-digital converter, and generating the pulse signal Flag _ PP according to the determination result. The input end of the first pulse width adjuster 2012 is connected to the output end of the first fully differential comparator 2011, and is configured to adjust the pulse width of the pulse signal to a preset pulse width, so as to obtain a first decision signal Flag _ P.
The second pulse comparing unit 202 determines a magnitude relationship between (VINN-VINP) and (VREFP-VREFN) and generates a first decision signal. For example, when (VINN-VINP) > (VREFP-VREFN) is generated, the second decision signal Flag _ N _ IN =1 is used to represent that the control target integrator is IN the disable enable state, and otherwise, the second decision signal Flag _ N _ IN =0 is generated to represent that the control target integrator is IN the enable state.
For example, the second pulse comparing unit 202 may include a second fully differential comparator 2021 and a second pulse width adjuster 2022. As shown in fig. 2, the input terminal of the second fully differential comparator 2021 is used for inputting the analog signals to be converted (i.e., the differential signals VINP and VINN), the reference signals (i.e., the first reference signal VREFP, the second reference signal VREFN), determining whether the amplitude of the analog signal to be converted is within the preset range of the analog-to-digital converter, and generating the pulse signal Flag _ NN according to the determination result. The input end of the second pulse width adjuster 2022 is connected to the output end of the second fully differential comparator 2021, and is configured to adjust the pulse width of the pulse signal to a preset pulse width, so as to obtain a second decision signal Flag _ N _ IN.
In the present disclosure, the preset pulse width is determined based on the capacitance of the target integrator. The first pulse width adjuster 2012 and the second pulse width adjuster 2022 adjust the pulse width of the pulse signal to a preset pulse width, so as to completely discharge the electric quantity of the capacitor of the target integrator within a time duration corresponding to the preset pulse width, thereby enabling the target integrator to be in an enable prohibition state.
The control unit 300 is connected to the first pulse comparing unit 201 and the second pulse comparing unit 202, respectively, and configured to output a corresponding control instruction to the analog-to-digital converter 100 according to the first decision signal and the second decision signal.
Illustratively, the control unit 300 comprises an or gate 301, the inputs of which are connected to the first pulse comparing unit 201 and the second pulse comparing unit 202, respectively, and the output of which is connected to the analog-to-digital converter 100. As shown in fig. 2, the input terminals of the or gate circuit are connected to a first pulse width adjuster 2012 and a second pulse width adjuster 2022, respectively. When the first decision signal output by the first pulse comparing unit 201 (i.e., the first pulse width adjuster 2012) or the second decision signal output by the second pulse comparing unit 202 (i.e., the second pulse width adjuster 2022) is the disable decision signal, the target integrator in the analog-to-digital converter 100 is in the disable enable state.
The analog-to-digital converter 100 may be a Sigma-Delta type analog-to-digital converter, and as shown in fig. 2, the analog-to-digital converter may include three integrators, each of which is a first stage integrator 1011Second stage integrator 1012And a third stage integrator 1013. Each stage of integrator comprises two resistors, two capacitors and an operational amplifier. In fig. 2, reference numerals of resistors, capacitors, and operational amplifiers are not shown. In addition, the three integrators in fig. 2 are all target integrators, and each target integrator is connected with two MOS switches in parallel. For example, first stage integrator 1011Connected in parallel with a first MOS switch 1021A second MOS switch 1031Second stage integrator 1012Connected in parallel with a third MOS switch 1042Fourth MOS switch 1052Third stage integrator 1013In parallel with a fifth MOS switch 1063Sixth MOS switch 1073And, the gate of each MOS switch is connected to the output terminal of the or gate circuit 301, that is, the signal input to the gate of each MOS switch is the signal Reset output from the output terminal of the or gate circuit 301. Thus, when one of the first decision signal Flag _ P and the second decision signal Flag _ N _ IN is at a high level, the signal Reset =1 output from the output terminal of the or gate circuit 301, that is, the capacitor IN the integrator connected IN parallel to the MOS switch is discharged until short-circuited, so that the integrator is IN the disable enable state.
That is, when the first pulse comparing unit or the second pulse comparing unit determines that the analog signal to be converted exceeds the preset range, the target integrator in the analog-to-digital converter is in the disable-enable state, so as to avoid oscillation of a feedback loop in the analog-to-digital converter and ensure the stability of the analog-to-digital converter.
It should be noted that at most one of the first decision signal Flag _ P generated by the first pulse comparing unit and the second decision signal Flag _ N _ IN generated by the second pulse comparing unit can only be 1 at the same time, and the situation that both Flag _ P and Flag _ N _ IN are 1 does not occur.
In addition, in order to further avoid the signal output by the analog-to-digital converter from being damaged when overload occurs, in the present disclosure, the analog-to-digital converter may be controlled to output a signal of a fixed amplitude when overload occurs. For example, the analog-to-digital converter may be controlled to output a signal having a maximum amplitude when the amplitude of the analog signal to be converted is greater than a preset range, and the analog-to-digital converter may be controlled to output a signal having a minimum amplitude when the amplitude of the analog signal to be converted is less than the preset range.
Specifically, the control unit 300 is further configured to control the digital-to-analog converter 100 to output a signal with an amplitude of a first preset value when the first decision signal indicates that the control target integrator is in the disable enable state. Illustratively, as shown in fig. 2, the output terminal of the first pulse width adjuster 2012 is connected to the quantizer 108 in the analog-to-digital converter 100, and when the first decision signal Flag _ P =1 is output from the output terminal of the first pulse width adjuster 2012, the output terminal of the quantizer 108 is controlled to output a signal having a first predetermined value, that is, the output signal Qout of the quantizer 108 is controlled to have a first predetermined value.
As shown in fig. 2, the control unit 300 may further include a not gate circuit 302 and a nor gate circuit 303. The output end of the second pulse comparing unit 202 is connected to the input end of the not-gate circuit 302, the output end of the not-gate circuit 302 and the output end of the first pulse comparing unit 201 are connected to the input end of the nor-gate circuit 303, and the output end of the nor-gate circuit 303 is connected to the analog-to-digital converter 100, and is configured to control the analog-to-digital converter to output a signal with an amplitude value of a second preset value when the second decision signal indicates that the control target integrator is in the disable enabling state. Specifically, the output end of the nor gate circuit 303 is connected to the quantizer 108 IN the analog-to-digital converter 100, and when the second decision signal indicates that the control target integrator is IN the disable enable state, the analog-to-digital converter is controlled to output a signal with a second preset magnitude, that is, when the second decision signal Flag _ N _ IN =1 output by the output end of the second pulse width adjuster 2022, the signal Flag _ N =1 output by the output end of the nor gate circuit 303, and at this time, the magnitude of the output signal Qout of the quantizer 108 is controlled to be the second preset magnitude. Wherein the first preset value is greater than the second preset value.
It should be noted that, in fig. 2, the output end of the quantizer 108 is respectively connected to the first digital-to-analog converter 109 and the second digital-to-analog converter 110 in the analog-to-digital converter 100, and the connection relationship and functions of the first digital-to-analog converter 109 and the second digital-to-analog converter 110 in the analog-to-digital converter 100 are in the prior art, and details of this disclosure are not repeated.
By adopting the technical scheme, when the amplitude of the analog signal to be converted is larger than the preset range, the analog-to-digital converter is controlled to output the signal with the amplitude of a first preset value, and when the amplitude of the analog signal to be converted is smaller than the preset range, the analog-to-digital converter is controlled to output the signal with the amplitude of a second preset value. In this way, the analog-to-digital converter can be ensured to output a complete signal when the input signal overload occurs.
Based on the same inventive concept, the present disclosure also provides an electronic device including the control circuit of the analog-to-digital converter provided by the present disclosure.
The preferred embodiments of the present disclosure are described in detail with reference to the accompanying drawings, however, the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solution of the present disclosure within the technical idea of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, various possible combinations will not be separately described in this disclosure.
In addition, any combination of various embodiments of the present disclosure may be made, and the same should be considered as the disclosure of the present disclosure, as long as it does not depart from the spirit of the present disclosure.
Claims (10)
1. A control circuit for an analog-to-digital converter, comprising: the device comprises an analog-to-digital converter, a pulse comparison unit and a control unit, wherein analog signals to be converted are respectively used as input signals of the analog-to-digital converter and the pulse comparison unit;
the pulse comparison unit is connected with the control unit and used for determining whether the amplitude of the analog signal to be converted is within a preset range of the analog-to-digital converter according to the analog signal to be converted and a reference signal, generating a decision signal according to a determination result and sending the decision signal to the control unit, wherein the reference signal is determined based on the preset range;
the control unit is connected with the analog-to-digital converter and used for receiving the decision signal and outputting a corresponding control instruction to the analog-to-digital converter according to the decision signal so as to control the working state of a target integrator in the analog-to-digital converter, wherein the target integrator is any one or more integrators in the analog-to-digital converter.
2. The control circuit of claim 1, wherein the pulse comparing unit is configured to generate an enable decision signal for controlling the target integrator to be in an enable state when the determination result indicates that the amplitude of the analog signal to be converted is within the preset range, and generate a disable decision signal for controlling the target integrator to be in a disable state when the determination result indicates that the amplitude of the analog signal to be converted is beyond the preset range;
the control unit is configured to output an enable instruction to the analog-to-digital converter to control the target integrator to be in an enable state when the decision signal is the enable decision signal, and output a disable instruction to the analog-to-digital converter to control the target integrator to be in a disable state when the decision signal is the disable decision signal.
3. The control circuit according to claim 1 or 2, wherein the pulse comparison unit comprises a first pulse comparison unit and a second pulse comparison unit, wherein a signal input to a positive input end of the first pulse comparison unit is the same as a signal input to a negative input end of the second pulse comparison unit, and a signal input to the negative input end of the first pulse comparison unit is the same as a signal input to a positive input end of the second pulse comparison unit;
the first pulse comparison unit is connected with the control unit and used for generating a first decision signal according to the analog signal to be converted and the reference signal and sending the first decision signal to the control unit;
the second pulse comparison unit is connected with the control unit and used for generating a second decision signal according to the analog signal to be converted and the reference signal and sending the second decision signal to the control unit;
the control unit is configured to output a corresponding control instruction to the analog-to-digital converter according to the first decision signal and the second decision signal.
4. The control circuit according to claim 3, wherein the control unit comprises an or gate circuit, input ends of the or gate circuit are respectively connected with the first pulse comparison unit and the second pulse comparison unit, and an output end of the or gate circuit is connected with the analog-to-digital converter.
5. The control circuit of claim 3, wherein the control unit is further configured to control the analog-to-digital converter to output a signal having a first predetermined magnitude when the first decision signal indicates that the target integrator is controlled to be in the disable-enable state.
6. The control circuit according to claim 3, wherein the control unit comprises a not-gate circuit and a nor-gate circuit, the output terminal of the second pulse comparing unit is connected to the input terminal of the not-gate circuit, the output terminal of the not-gate circuit and the output terminal of the first pulse comparing unit are connected to the input terminal of the nor-gate circuit, and the output terminal of the nor-gate circuit is connected to the analog-to-digital converter, so as to control the analog-to-digital converter to output a signal with a second predetermined magnitude when the second decision signal indicates that the target integrator is controlled to be in the disable enable state.
7. The control circuit of claim 2, wherein the analog-to-digital converter comprises MOS switches, wherein at least one MOS switch is connected in parallel to each target integrator;
the gate of the MOS switch is connected with the control unit and used for controlling the target integrator to be in an enabling state when the control unit outputs an enabling instruction, and controlling the target integrator to be in a disabling state when the control unit outputs a disabling instruction.
8. The control circuit of claim 1, wherein the pulse comparison unit comprises a fully differential comparator and a pulse width adjuster;
the input end of the fully differential comparator is respectively input with the analog signal to be converted and the reference signal, and is used for determining whether the amplitude of the analog signal to be converted is within the preset range of the analog-to-digital converter, and generating a pulse signal according to the determination result;
and the input end of the pulse width regulator is connected with the output end of the fully differential comparator and is used for adjusting the pulse width of the pulse signal to a preset pulse width to obtain the judgment signal, wherein the preset pulse width is determined based on the capacitance of the target integrator.
9. The control circuit of claim 1, wherein the analog-to-digital converter is a Sigma-Delta type analog-to-digital converter.
10. An electronic device, comprising: a control circuit for an analog to digital converter as claimed in any one of claims 1 to 9.
Priority Applications (1)
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