CN111900185B - Display panel and preparation method thereof - Google Patents
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- CN111900185B CN111900185B CN202010551710.9A CN202010551710A CN111900185B CN 111900185 B CN111900185 B CN 111900185B CN 202010551710 A CN202010551710 A CN 202010551710A CN 111900185 B CN111900185 B CN 111900185B
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/124—Insulating layers formed between TFT elements and OLED elements
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- H10K50/11—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
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- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
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- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
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- H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
- H10K59/65—OLEDs integrated with inorganic image sensors
Abstract
The application provides a display panel and a preparation method thereof, the display panel comprises an array substrate, a first anode layer, a pixel definition layer, a second anode layer, a light emitting layer and a cathode layer, the array substrate comprises an array area and a vacant area, the first anode layer is arranged on the array area, the pixel definition layer is arranged on the array area and the first anode layer of the array substrate, the pixel definition layer comprises a plurality of through holes, the pixel definition layer comprises a first area, the first area is positioned on the side of the vacant area, the second anode layer is arranged on the first area of the pixel definition layer, the second anode layer is positioned on the surface of the pixel definition layer in the through holes, the light emitting layer comprises a plurality of first light emitting parts, each first light emitting part is arranged in one through hole, the cathode layer is arranged on the pixel definition layer and the light emitting layer, and the cathode layer is electrically connected with the light emitting layer. The light transmittance of the vacant region of the display panel is improved, and normal display is ensured.
Description
Technical Field
The application relates to the technical field of display panels, in particular to a display panel and a preparation method thereof.
Background
At present, in the display device, usually with digging hole design in the display device for place camera under the screen, nevertheless, because of the regional needs of placing camera under the screen get rid of corresponding device rete, make camera region unable normal display under the screen.
Disclosure of Invention
The application provides a display panel and a preparation method thereof, which aim to solve the problem that a camera area under a screen cannot normally display and image in the prior art.
The application provides a display panel, including:
the array substrate comprises an array area and a vacant area;
the first anode layer is arranged on the array area and is electrically connected with the array substrate;
the pixel defining layer is arranged on the array area of the array substrate and the first anode layer and comprises a plurality of through holes, the through holes penetrate through the pixel defining layer to expose the first anode layer, and the pixel defining layer comprises a first area which is positioned on the side edge of the vacant area;
the second anode layer is arranged on the first area of the pixel defining layer, the second anode layer is positioned on the surface, facing the vacant area, of the pixel defining layer in the through hole, and the first anode layer and the second anode layer are insulated from each other;
the light-emitting layer comprises a plurality of first light-emitting parts, each first light-emitting part is arranged in one through hole, and the first light-emitting parts cover and are electrically connected with the first anode layer and the second anode layer; and
a cathode layer disposed on the pixel defining layer and the light emitting layer, the cathode layer being electrically connected to the light emitting layer.
In the display panel provided by the present application, the second anode layer includes a plurality of second anodes, each of the second anodes includes an extension portion, the extension portion is located on the upper surface of the pixel defining layer, and an insulating layer is disposed between the extension portion and the cathode layer.
In the display panel provided by the present application, the first region surrounds the vacant region.
In the display panel provided by the present application, the array substrate includes a plurality of first transistors and a plurality of second transistors, the first transistors are electrically connected to the first anode layer, and the second transistors are electrically connected to the second anode layer.
In the display panel provided by the present application, the pixel defining layer further includes a second area, the first area is located between the second area and the empty area, the light emitting layer further includes a plurality of second light emitting portions, each of the second light emitting portions is disposed in a through hole of the first area, and the second light emitting portions are electrically connected to the first anode layer and the cathode layer.
In the display panel provided by the present application, the first light-emitting portion covers the second anode layer, the light emitted by the first light-emitting portion exits from the vacant area, the second light-emitting portion covers the first anode layer, and the light emitted by the second light-emitting portion exits from the array area.
In the display panel provided by the present application, the display panel further includes an encapsulation layer, and the encapsulation layer is disposed on the cathode layer of the array region and on the vacant region.
The application also provides a preparation method of the display panel, which comprises the following steps:
providing an array substrate, wherein the array substrate comprises an array area and a vacant area;
forming a first anode layer on an array region of the array substrate, the first anode layer being electrically connected to the array substrate;
forming a pixel defining layer on the array region of the array substrate and the first anode layer, wherein the pixel defining layer comprises a plurality of through holes which penetrate through the pixel defining layer to expose the first anode layer, and the pixel defining layer comprises a first area which is positioned at the side of the vacant area;
forming a second anode layer on the first region of the pixel defining layer, the second anode layer being located on a surface of the pixel defining layer facing the vacant region in the through hole, the first anode layer and the second anode layer being insulated from each other;
forming a light-emitting layer in the through hole, wherein the light-emitting layer comprises a plurality of first light-emitting parts, each first light-emitting part is arranged in one through hole, and the first light-emitting parts cover and are electrically connected with the first anode layer and the second anode layer;
forming a cathode layer on the pixel defining layer and the light emitting layer, the cathode layer being electrically connected to the light emitting layer.
In the method for manufacturing a display panel provided by the present application, after the step of forming a cathode layer on the pixel defining layer and the light emitting layer, and electrically connecting the first cathode layer and the light emitting layer, the method further includes:
and forming an encapsulation layer on the cathode layer of the array region and the vacant regions.
In the method for manufacturing a display panel provided by the present application, the forming a second anode layer on the first region of the pixel defining layer, the second anode layer being located on a surface of the pixel defining layer facing the vacant region in the through hole, and after the step of insulating the first anode layer and the second anode layer from each other, the method further includes:
and forming an insulating layer on the second anode layer, wherein the second anode layer comprises a plurality of second anodes, each second anode comprises an extension part, the extension parts are positioned on the upper surface of the pixel definition layer, and the insulating layer covers the extension parts.
The application provides a display panel and a preparation method thereof, the display panel comprises an array substrate, a first anode layer, a pixel definition layer, a second anode layer, a light emitting layer and a cathode layer, the array substrate comprises an array area and a vacant area, the first anode layer is arranged on the array area, the first anode layer is electrically connected with the array substrate, the pixel definition layer is arranged on the array area of the array substrate and the first anode layer, the pixel definition layer comprises a plurality of through holes, the through holes penetrate through the pixel definition layer to expose the first anode layer, the pixel definition layer comprises a first area, the first area is positioned on the side of the vacant area, the second anode layer is arranged on the first area of the pixel definition layer, the second anode layer is positioned on the surface of the vacant area towards the pixel definition layer in the through holes, the first anode layer and the second anode layer are insulated from each other, the light-emitting layer comprises a plurality of first light-emitting parts, each first light-emitting part is arranged in one through hole, the first light-emitting parts cover and are electrically connected with the first anode layer and the second anode layer, the cathode layer is arranged on the pixel defining layer and the light-emitting layer, and the cathode layer is electrically connected with the light-emitting layer. In the application, the first light-emitting part is electrically connected with the second anode layer, so that light emitted by the first light-emitting part is oblique light and is emitted to the vacant area from the first light-emitting part, and the vacant area is normally imaged and normally displayed.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a first plan view of an anode film layer provided herein.
Fig. 2 is a first cross-sectional view of a display panel provided by the present application along line I-II.
Fig. 3 is a light path diagram of a display panel provided in the present application.
Fig. 4 is a second plan view of an anode film layer provided herein.
Fig. 5 is a pixel plan view of a display panel provided in the present application.
Fig. 6 is a cross-sectional view of a display panel provided by the present application along line III-IV.
Fig. 7 is a flowchart of a method for manufacturing a display panel according to the present application.
Fig. 8 to 16 are cross-sectional views illustrating a manufacturing method of a display panel provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1 and 2, fig. 1 is a first plan view of an anode film layer provided in the present application. Fig. 2 is a cross-sectional view of a display panel provided by the present application along line I-II. The present application provides a display panel 10. The display panel 10 includes an array substrate 100, a first anode layer 200, a pixel defining layer 300, a second anode layer 400, a light emitting layer 500, and a cathode layer 600.
The array substrate 100 includes a vacant region 110 and an array region 120. Specifically, the vacant areas are used for placing the cameras under the screen. The array substrate 100 includes a flexible substrate 130, a buffer layer 140, and a transistor layer 150 disposed in the array region 120. The buffer layer 140 is disposed on the flexible substrate 130. The buffer layer 140 is used to block water and oxygen corrosion. The transistor layer 150 is disposed on the buffer layer 140 of the array region 120. The transistor layer 150 includes a number of first transistors 151 and a number of second transistors 152. The first transistor 151 includes a first active layer 1511, a first gate insulating layer 1512, a first gate 1513, a first source 1514, and a first drain 1515. The first active layer 1511 includes an N-type doped portion 15111, a semiconductor portion 15112, and a P-type doped portion 15113. The N-type doped portion 15111 and the P-type doped portion 15113 are located at both sides of the semiconductor portion 15112. The first gate insulating layer 1512 is disposed on the first active layer 1511. The first gate 1513 is located on the first gate insulating layer 1512. The first source 1514 is positioned at one side of the first active layer 1511 and is electrically connected to the first active layer 1511. The first drain 1515 is positioned at the other side of the first active layer 1511 and is electrically connected to the first active layer 1511. The second transistor 152 includes a second active layer 1521, a second gate insulating layer 1522, a second gate 1523, a second source 1524, and a second drain 1525. The second active layer 1521 includes an N-type doped portion 15211, a semiconductor portion 15212 and a P-type doped portion 15213. The N-type doped portion 15211 and the P-type doped portion 15213 are located on two sides of the semiconductor portion 15212. The structure and the corresponding position of the second transistor 152 are the same as those of the first transistor 151, and are not described again here. The transistor layer 150 further includes a plurality of first grooves 153. The first recess 153 is located above the first drain 1515 and exposes the first drain 1515.
The first anode layer 200 is disposed on the array region 120. The first anode layer 200 is electrically connected to the array substrate 100. Specifically, the first anode layer 200 is disposed in the first groove 153 and on the transistor layer 150. The first anode layer 200 is electrically connected to the first drain electrode 1515.
The pixel defining layer 300 is disposed on the array region 120 of the array substrate 100 and the first anode layer 200. The pixel definition layer 300 includes a number of vias 310. The via hole 310 penetrates the pixel defining layer 300 to expose the first anode layer 200. The pixel defining layer 300 includes a first region 320 and a second region 330. The through hole 310 is located on the first region 320. The first region 320 is located at a side of the vacant region 110. The first region 320 is located between the second region 330 and the vacant region 110. In this embodiment, the first region 320 surrounds the vacant region 110.
In another embodiment, the pixel definition layer 300 further includes a number of vias 340. The via hole 340 is located on the first region, and penetrates through the pixel defining layer 300 and a portion of the transistor layer 150 to expose the second drain electrode 1525.
The second anode layer 400 is disposed on the first region 320 of the pixel defining layer 300. The second anode layer 400 is located on the surface of the pixel defining layer 300 facing the vacant region 110 in the via hole 310. The first anode layer 200 and the second anode layer 400 are insulated from each other. Specifically, the second anode layer 400 includes a plurality of second anodes 410. Each of the second anodes 410 includes an extension 411. The extension 411 is located on the upper surface of the pixel defining layer 300 and in the via hole 340. The second electrode 410 is electrically connected to the second drain 1525 through the extension 411.
In this application, the first anode layer and the second anode layer are mutually insulated, and the luminous parts driven by the first anode layer and the second anode layer are guaranteed not to be dry when emitting light, so that normal display of the display panel is guaranteed.
In another embodiment, the display panel 10 further includes an insulating layer 700. The insulating layer 700 is disposed on the extension portion 411 and covers the extension portion 411.
Referring to fig. 3, fig. 3 is a light path diagram of a display panel provided in the present application. The light emitting layer 500 includes a plurality of first light emitting parts 510 and a plurality of second light emitting parts 520. Each of the first light emitting parts 510 is disposed in one of the through holes 230. The first light emitting part 510 electrically connects the first anode layer 200 and the second anode layer 500. The first light emitting part 510 is positioned on the second anode layer 400. The light emitted from the first light emitting part 510 is emitted from the vacant region 110. The light emitted by the first light emitting part 510 is an oblique emergent light. Each of the second light emitting parts 520 is disposed in a through hole 230 of the first region 320, and the second light emitting part 520 covers and is electrically connected to the first anode layer 200. The light emitted from the second light emitting part 520 is emitted from the array region 120. The light emitted by the second light emitting part 520 is a vertical outgoing light. The first light emitting portion 510 is electrically connected to the second light emitting portion 520. The first and second light emitting parts 510 and 520 include a red light emitting part, a green light emitting part, and a blue light emitting part.
The cathode layer 600 is disposed on the pixel defining layer 300, the insulating layer 700, and the light emitting layer 500. The cathode layer 600 is electrically connected to the light emitting layer 500.
In this application, the second illuminating part with first anode layer reaches the cathode layer electricity is connected, first transistor drive the second illuminating part, the light that the second illuminating part sent is vertical emergent light for provide the normal demonstration of area around the vacant district, first illuminating part with the second anode layer reaches the cathode layer electricity is connected, the second transistor with second anode layer electricity is connected, the second transistor drive first illuminating part, the light that first illuminating part sent is oblique emergent light, provides the required light of camera formation of image under the screen that is located the vacant district, and make the normal demonstration of vacant district, simultaneously, because of vacant district function rete is got rid of, further guarantees that camera enough external light is used for normal formation of image under the screen.
In another embodiment, the display panel 10 further includes an encapsulation layer 800. The encapsulation layer 800 is disposed on the cathode layer 600 of the array region 120 and on the vacant region 110. The encapsulation layer 800 is disposed on the array substrate 100 and the cathode layer 600 in the array region 120. The encapsulation layer 800 includes a first inorganic layer 810, an organic layer 820, and a second inorganic layer 830. The organic layer 820 is disposed on the first inorganic layer 810. The second inorganic layer 830 is disposed on the organic layer 820. In this embodiment, the package layer 800 has a three-layer stacked structure.
Referring to fig. 4, fig. 4 is a second plan view of an anode film provided in the present application. The difference between the fig. 4 and the 1 is that the second anode layer 400 in the fig. 4 is a non-rectilinear design.
The application provides a display panel, display panel includes array substrate, first anode layer, pixel definition layer, second anode layer, luminescent layer and cathode layer, array substrate includes an array district and a vacant region, first anode layer set up in on the array district, first anode layer with the array substrate electricity is connected, pixel definition layer set up in the array district of array substrate with on the first anode layer, pixel definition layer includes a plurality of through-holes, the through-hole runs through pixel definition layer in order to expose the first anode layer, pixel definition layer includes first region, first region is located the side of vacant region, the second anode layer set up in the first region of pixel definition layer, the second anode layer is located the surface of pixel definition layer orientation in the through-hole, the first anode layer and the second anode layer are insulated from each other, the light-emitting layer comprises a plurality of first light-emitting parts, each first light-emitting part is arranged in one through hole, the first light-emitting parts cover and are electrically connected with the first anode layer and the second anode layer, the cathode layer is arranged on the pixel defining layer and the light-emitting layer, and the cathode layer is electrically connected with the light-emitting layer. In the application, the first light-emitting part is electrically connected with the second anode layer, so that light emitted by the first light-emitting part is oblique light and is emitted to the vacant area, and the vacant area can be normally imaged and normally displayed.
Referring to fig. 5 and 6, fig. 5 is a pixel plane view of a display panel provided in the present application. Fig. 6 is a cross-sectional view of a display panel provided by the present application along line III-IV.
Fig. 5 shows the pixel layer distribution in the vacant area and the periphery of the display panel of the present application, and for the sake of understanding, fig. 6 shows only the light path diagram of the first transistor driving the second light emitting portion, which does not mean that the first light emitting portion is driven without the second transistor.
Referring to fig. 7 and fig. 8-16, fig. 7 is a flowchart illustrating a method for manufacturing a display panel according to the present disclosure. Fig. 8 to 16 are cross-sectional views illustrating a manufacturing method of a display panel provided in the present application. The present application also provides a method for manufacturing a display panel 10, the method including:
20. an array substrate 100 is provided, and the array substrate 100 includes a vacant area 110 and an array area 120.
Referring to fig. 8 and 9, in particular, the vacant area is used for placing the off-screen camera. Specifically, the array substrate 100 includes a flexible substrate 130, a buffer layer 140, and a transistor layer 150. A buffer layer 140 is formed on the flexible substrate 130. The buffer layer 140 is used to block water and oxygen corrosion. A transistor layer 150 is formed on the buffer layer 140, and the transistor layer 150 on the vacant region 110 is removed by masking or etching. The transistor layer 150 includes a number of first transistors 151 and a number of second transistors 152. The first transistor 151 includes a first active layer 1511, a first gate insulating layer 1512, a first gate 1513, a first source 1514, and a first drain 1515. The first active layer 1511 includes an N-type doped portion 15111, a semiconductor portion 15112, and a P-type doped portion 15113. The N-type doped portion 15111 and the P-type doped portion 15113 are located at both sides of the semiconductor portion 15112. The first gate insulating layer 1512 is disposed on the first active layer 1511. The first gate 1513 is located on the first gate insulating layer 1512. The first source 1514 is positioned at one side of the first active layer 1511 and is electrically connected to the first active layer 1511. The first drain 1515 is positioned at the other side of the first active layer 1511 and is electrically connected to the first active layer 1511. The second transistor 152 includes a second active layer 1521, a second gate insulating layer 1522, a second gate 1523, a second source 1524, and a second drain 1525. The structure and the corresponding position of the second transistor 152 are the same as those of the first transistor 151, and are not described again here. The transistor layer 150 further includes a plurality of first grooves 153. The first recess 153 is located above the first drain 1515 and exposes the first drain 1515.
30. A first anode layer 200 is formed on the array region 120 of the array substrate 100, and the first anode layer 200 is electrically connected to the array substrate 100.
Referring to fig. 10, a first anode layer material is disposed in the first recess 153 and on the transistor layer 150, and a first anode layer 200 is formed by masking or etching. The first anode layer 200 is electrically connected to the first drain electrode 1515.
40. Forming a pixel defining layer 300 on the array region 120 of the array substrate 100 and the first anode layer 200, wherein the pixel defining layer 300 includes a plurality of through holes 310, the through holes 310 penetrate the pixel defining layer 300 to expose the first anode layer 200, the pixel defining layer 300 includes a first region 320, and the first region 320 is located at a side of the vacant region 110.
Referring to fig. 11, in detail, a pixel defining layer material is disposed on the transistor layer 150 and the first anode layer 200, and a pixel defining layer 300 is formed by masking or etching. The pixel defining layer 300 includes a number of through holes 310 and a number of via holes 340. The through hole 310 and the via hole 340 are located on the first region 320. The via hole 310 penetrates the pixel defining layer 300 to expose the first anode layer 200. The via 340 penetrates through the pixel defining layer 300 and a portion of the transistor layer 150 to expose the second drain 1525. The pixel defining layer 300 includes a first region 320 and a second region 330. The first region 320 is located at a side of the vacant region 110. The first region 320 is located between the second region 330 and the vacant region 110. In this embodiment, the first region 320 surrounds the vacant region 110.
50. Forming a second anode layer 400 on the first region 320 of the pixel defining layer 300, wherein the second anode layer 400 is located on the surface of the pixel defining layer 300 facing the vacant region 110 in the through hole 310, and the first anode layer 200 and the second anode layer 400 are insulated from each other.
Referring to fig. 12, in particular, a second anode layer material is disposed in the via hole 340 and on the first region 320 of the pixel defining layer 300, and a second anode layer 400 is formed by masking or etching. The second anode layer 400 includes a number of second anodes 410. Each of the second anodes 410 includes an extension 411. The extension 411 is located on the upper surface of the pixel defining layer 300 and in the via hole 340. The second electrode 410 is electrically connected to the second drain 1525 through the extension 411.
Referring to fig. 13, after the step of forming the second anode layer 400 on the first region 320 of the pixel defining layer 300, an insulating layer 700 covering the extension 411 is formed on the extension 411.
In this application, an insulating layer 700 is disposed on the second anode layer 400 to isolate the second anode layer 400 from the cathode layer 600, thereby preventing electrical short.
60. Forming a light emitting layer 500 in the through hole 310, wherein the light emitting layer 500 includes a plurality of first light emitting parts 510, each of the first light emitting parts 510 is disposed in one of the through holes, and the first light emitting part 510 covers and electrically connects the first anode layer 200 and the second anode layer 400.
Referring to fig. 14, in detail, a light emitting layer 500 is formed in the through hole 310 by using a mask. The light emitting layer 500 includes a plurality of first light emitting parts 510 and a plurality of second light emitting parts 520. The first light emitting portion 510 is electrically connected to the second light emitting portion 520. The first light emitting part 510 electrically connects the first anode layer 200 and the second anode layer 500. The first light emitting part 510 covers and is electrically connected to the second anode layer 400. The light emitted from the first light emitting part 510 is emitted from the vacant region 110. The light emitted by the first light emitting part 510 is an oblique emergent light. The second light emitting part 520 covers and is electrically connected to the first anode layer 200. The light emitted from the second light emitting part 520 is emitted from the array region 120. The light emitted by the second light emitting part 520 is a vertical outgoing light. The first and second light emitting parts 510 and 520 include a red light emitting part, a green light emitting part, and a blue light emitting part.
70. A cathode layer 600 is formed on the pixel defining layer 300 and the light emitting layer 500, and the cathode layer 600 is electrically connected to the light emitting layer 500.
Referring to fig. 15, specifically, a cathode layer 600 is formed on the pixel defining layer 300, the insulating layer 700 and the light emitting layer 500 by masking or etching.
In this application, the second illuminating part with first anode layer reaches the cathode layer electricity is connected, first transistor drive the second illuminating part, the light that the second illuminating part sent is vertical emergent light for provide the normal demonstration of area around the vacant district, first illuminating part with the second anode layer reaches the cathode layer electricity is connected, the second transistor with second anode layer electricity is connected, the second transistor drive first illuminating part, the light that first illuminating part sent is oblique emergent light, provides the required light of camera formation of image under the screen that is located the vacant district, and make the normal demonstration of vacant district, simultaneously, because of vacant district function rete is got rid of, further guarantees that camera enough external light is used for normal formation of image under the screen.
Referring to fig. 16, after the step of forming the cathode layer 600 on the pixel defining layer 300 and the light emitting layer 500, a first inorganic layer 810, an organic layer 820 and a second inorganic layer 830 are sequentially formed on the array substrate 100 and the cathode layer 600 on the array region 120. The first inorganic layer 810, the organic layer 820 and the second inorganic layer 830 constitute an encapsulation layer 800 of the display panel 10. In this embodiment, the package layer 800 has a three-layer stacked structure.
The application provides a display panel and a preparation method thereof, the display panel comprises an array substrate, a first anode layer, a pixel definition layer, a second anode layer, a light emitting layer and a cathode layer, the array substrate comprises an array area and a vacant area, the first anode layer is arranged on the array area, the first anode layer is electrically connected with the array substrate, the pixel definition layer is arranged on the array area of the array substrate and the first anode layer, the pixel definition layer comprises a plurality of through holes, the through holes penetrate through the pixel definition layer to expose the first anode layer, the pixel definition layer comprises a first area, the first area is positioned on the side of the vacant area, the second anode layer is arranged on the first area of the pixel definition layer, the second anode layer is positioned on the surface of the vacant area towards the pixel definition layer in the through holes, the first anode layer and the second anode layer are insulated from each other, the light-emitting layer comprises a plurality of first light-emitting parts, each first light-emitting part is arranged in one through hole, the first light-emitting parts cover and are electrically connected with the first anode layer and the second anode layer, the cathode layer is arranged on the pixel defining layer and the light-emitting layer, and the cathode layer is electrically connected with the light-emitting layer. In the application, the first light-emitting part is electrically connected with the second anode layer, so that light emitted by the first light-emitting part is oblique light and is emitted to the vacant area from the first light-emitting part, and the vacant area is normally imaged and normally displayed.
The above embodiments are merely examples, and not intended to limit the scope of the present disclosure, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present disclosure, or their direct or indirect application to other related arts, are included in the scope of the present disclosure.
Claims (10)
1. A display panel, comprising:
the array substrate comprises an array area and a vacant area;
the first anode layer is arranged on the array area and is electrically connected with the array substrate;
the pixel defining layer is arranged on the array area of the array substrate and the first anode layer and comprises a plurality of through holes, the through holes penetrate through the pixel defining layer to expose the first anode layer, and the pixel defining layer comprises a first area which is positioned on the side edge of the vacant area;
the second anode layer is arranged on the first area of the pixel defining layer, the second anode layer is positioned on the surface, facing the vacant area, of the pixel defining layer in the through hole, and the first anode layer and the second anode layer are insulated from each other;
the light-emitting layer comprises a plurality of first light-emitting parts, each first light-emitting part is arranged in one through hole, and the first light-emitting parts cover and are electrically connected with the first anode layer and the second anode layer; and
a cathode layer disposed on the pixel defining layer and the light emitting layer, the cathode layer being electrically connected to the light emitting layer.
2. The display panel of claim 1, wherein the second anode layer comprises a plurality of second anodes, each of the second anodes comprising an extension on an upper surface of the pixel definition layer with an insulating layer between the extension and the cathode layer.
3. The display panel according to claim 1, wherein the first region surrounds the vacant region.
4. The display panel of claim 1, wherein the array substrate includes a plurality of first transistors electrically connected to the first anode layer and a plurality of second transistors electrically connected to the second anode layer.
5. The display panel according to claim 1, wherein the pixel defining layer further includes a second region, the first region is located between the second region and the vacant region, the light emitting layer further includes a plurality of second light emitting portions, each of the second light emitting portions is disposed in a through hole of the first region, and the second light emitting portions are electrically connected between the first anode layer and the cathode layer.
6. The display panel according to claim 5, wherein the first light-emitting portion covers the second anode layer, light emitted from the first light-emitting portion exits from the vacant region, the second light-emitting portion covers the first anode layer, and light emitted from the second light-emitting portion exits from the array region.
7. The display panel of claim 1, further comprising an encapsulation layer disposed on the cathode layer of the array region and on the vacant regions.
8. A method for manufacturing a display panel, comprising:
providing an array substrate, wherein the array substrate comprises an array area and a vacant area;
forming a first anode layer on an array region of the array substrate, the first anode layer being electrically connected to the array substrate;
forming a pixel defining layer on the array region of the array substrate and the first anode layer, wherein the pixel defining layer comprises a plurality of through holes which penetrate through the pixel defining layer to expose the first anode layer, and the pixel defining layer comprises a first area which is positioned at the side of the vacant area;
forming a second anode layer on the first region of the pixel defining layer, the second anode layer being located on a surface of the pixel defining layer facing the vacant region in the through hole, the first anode layer and the second anode layer being insulated from each other;
forming a light-emitting layer in the through hole, wherein the light-emitting layer comprises a plurality of first light-emitting parts, each first light-emitting part is arranged in one through hole, and the first light-emitting parts cover and are electrically connected with the first anode layer and the second anode layer;
forming a cathode layer on the pixel defining layer and the light emitting layer, the cathode layer being electrically connected to the light emitting layer.
9. The method for manufacturing a display panel according to claim 8, wherein the step of forming a cathode layer over the pixel defining layer and the light emitting layer, the cathode layer being electrically connected to the light emitting layer, further comprises:
and forming an encapsulation layer on the cathode layer of the array region and the vacant regions.
10. The method for manufacturing a display panel according to claim 8, wherein the step of forming a second anode layer over the first region of the pixel defining layer, the second anode layer being located on a surface of the pixel defining layer facing the vacant region in the through hole, and the first anode layer and the second anode layer being insulated from each other further comprises:
and forming an insulating layer on the second anode layer, wherein the second anode layer comprises a plurality of second anodes, each second anode comprises an extension part, the extension parts are positioned on the upper surface of the pixel definition layer, and the insulating layer covers the extension parts.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010551710.9A CN111900185B (en) | 2020-06-17 | 2020-06-17 | Display panel and preparation method thereof |
| US16/973,574 US11508794B2 (en) | 2020-06-17 | 2020-06-30 | Display panel with light-emitting portions in pixel definition layer and manufacturing method thereof |
| PCT/CN2020/099433 WO2021253500A1 (en) | 2020-06-17 | 2020-06-30 | Display panel and preparation method therefor |
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| CN202010551710.9A CN111900185B (en) | 2020-06-17 | 2020-06-17 | Display panel and preparation method thereof |
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| CN111900185B true CN111900185B (en) | 2021-06-25 |
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| US (1) | US11508794B2 (en) |
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| KR20220034949A (en) * | 2020-09-11 | 2022-03-21 | 삼성디스플레이 주식회사 | Display device |
| CN113193140B (en) * | 2021-04-16 | 2022-07-12 | 武汉华星光电半导体显示技术有限公司 | Display panel and manufacturing method thereof |
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| KR102587708B1 (en) * | 2016-06-30 | 2023-10-11 | 엘지디스플레이 주식회사 | Organic light emitting display device, head mounted display including the same and method for manufacturing the same |
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| US20220190049A1 (en) | 2022-06-16 |
| WO2021253500A1 (en) | 2021-12-23 |
| US11508794B2 (en) | 2022-11-22 |
| CN111900185A (en) | 2020-11-06 |
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