CN111883485A - Method for manufacturing semiconductor structure - Google Patents

Method for manufacturing semiconductor structure Download PDF

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Publication number
CN111883485A
CN111883485A CN202010884225.3A CN202010884225A CN111883485A CN 111883485 A CN111883485 A CN 111883485A CN 202010884225 A CN202010884225 A CN 202010884225A CN 111883485 A CN111883485 A CN 111883485A
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China
Prior art keywords
layer
patterned
substrate
etching
insulating
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CN202010884225.3A
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Chinese (zh)
Inventor
秋沉沉
钱俊
孙昌
魏峥颖
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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Priority to CN202010884225.3A priority Critical patent/CN111883485A/en
Publication of CN111883485A publication Critical patent/CN111883485A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

The invention provides a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate, and preparing a polycrystalline silicon layer on the substrate; etching the polysilicon layer and the substrate to form an isolation trench; forming an insulating layer in the isolation groove, wherein the upper surface of the insulating layer is lower than the upper surface of the polycrystalline silicon layer; and etching the polysilicon layer to form a grid electrode. The preparation method of the semiconductor structure provided by the invention reduces the damage of the gate structure process to the isolation trench by improving the process flow of semiconductor manufacturing, thereby improving the electric leakage phenomenon. Meanwhile, the difference between devices mainly caused by photoetching and etching in the preparation process of the isolation groove and the gate structure is reduced, so that the mismatch phenomenon of the semiconductor device is improved, and the stability and the reliability of the semiconductor device are improved.

Description

Method for manufacturing semiconductor structure
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a preparation method of a semiconductor structure.
Background
Static Random Access Memory (SRAM) is an important memory, has the advantages of high speed, low power consumption, high reliability, and the like, and is widely used in the fields of personal communication, consumer electronics (smart cards, digital cameras, multimedia players), and the like.
In the design and production process of semiconductor devices, due to uncertainty, random errors, gradient errors and the like, exactly the same semiconductor devices are designed with errors after production, which is called mismatch process (mismatch process) of semiconductor devices. The mismatch process not only becomes a limitation in the general analog signal processing process, but also has a significant impact on the matching of devices in the digital circuit. For example, after the process size of the sram is reduced to 100nm, the influence of the MOS threshold voltage fluctuation caused by the random variation of the process parameters on the stability and reliability of the sram becomes more and more serious, and becomes one of the important factors limiting the yield improvement of the sram.
In the prior art, the preparation of the sram generally includes processes of forming an Active Area (AA), forming a Gate (Gate), depositing polysilicon (poly dep), and etching polysilicon (poly etch). However, the above process may cause damage to the sharp corner portion (STI corner) of the isolation trench and cause sram mismatch. At present, the method for improving the mismatching of the static random access memory mainly improves the stability of the processes such as photoetching, etching and the like, and has limited effect.
Disclosure of Invention
The invention aims to provide a preparation method of a semiconductor structure, which reduces the damage of a gate structure process to an isolation trench by improving the process flow of semiconductor manufacturing, and simultaneously reduces the difference between devices caused by the process flow, thereby improving the mismatch phenomenon of the semiconductor device, reducing electric leakage and improving the stability and reliability of the semiconductor device.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor structure, comprising:
providing a substrate, and preparing a first polycrystalline silicon layer on the substrate;
providing a substrate, and preparing a polycrystalline silicon layer on the substrate;
etching the polysilicon layer and the substrate to form an isolation trench;
forming an insulating layer in the isolation groove, wherein the upper surface of the insulating layer is lower than the upper surface of the polycrystalline silicon layer;
and etching the polysilicon layer to form a grid electrode.
Optionally, an oxide layer is further formed between the first polysilicon layer and the substrate.
Optionally, the upper surface of the insulating layer is higher than the upper surface of the oxide layer.
Optionally, the step of etching the polysilicon layer and the substrate to form the isolation trench includes:
forming a patterned first photoresist layer on the polysilicon layer;
etching the polycrystalline silicon layer and the substrate by taking the patterned first photoresist layer as a mask layer to form an isolation groove; and
and removing the patterned first photoresist layer.
Optionally, the process of forming the insulating layer in the isolation trench includes:
filling an insulating material layer in the isolation trench, wherein the insulating material layer extends to cover the polycrystalline silicon layers on two sides of the isolation trench;
carrying out planarization treatment on the insulating material layer to enable the upper surface of the insulating material layer to be flush with the upper surface of the polycrystalline silicon layer;
and etching the insulating material layer with a certain thickness to form an insulating layer, wherein the upper surface of the insulating layer is lower than the upper surface of the polycrystalline silicon layer.
Optionally, the process of etching the polysilicon layer to form the gate includes:
forming a second patterned photoresist layer on the polysilicon layer, wherein the second patterned photoresist layer covers the insulating layer;
etching the polycrystalline silicon layer by taking the patterned second photoresist layer as a mask layer until part of the oxide layer is exposed; and
and removing the patterned second photoresist layer.
Optionally, a plasma photoresist removing process is used to remove the patterned first photoresist layer and the patterned second photoresist layer.
Optionally, the polysilicon layer is etched by a dry method.
Optionally, the material of the oxide layer includes silicon oxide.
Optionally, the material of the insulating layer includes silicon oxide.
In summary, the present invention provides a method for manufacturing a semiconductor structure, including: providing a substrate, and preparing a polycrystalline silicon layer on the substrate; etching the polysilicon layer and the substrate to form an isolation trench; forming an insulating layer in the isolation groove, wherein the upper surface of the insulating layer is lower than the upper surface of the polycrystalline silicon layer; and etching the polysilicon layer to form a grid electrode. The preparation method of the semiconductor structure provided by the invention reduces the damage of the gate structure process to the isolation trench by improving the process flow of semiconductor manufacturing, thereby improving the electric leakage phenomenon. Meanwhile, the difference between devices mainly caused by photoetching and etching in the preparation process of the isolation groove and the gate structure is reduced, so that the mismatch phenomenon of the semiconductor device is improved, and the stability and the reliability of the semiconductor device are improved.
Drawings
Fig. 1-5 are schematic cross-sectional views corresponding to steps of a method for fabricating a semiconductor structure according to this embodiment;
fig. 6 is a flowchart of a method for fabricating a semiconductor structure according to the present embodiment;
fig. 7-14 are schematic cross-sectional views corresponding to steps of the method for fabricating the semiconductor structure according to the present embodiment;
wherein the reference numbers are as follows:
100' -a substrate; 110' -an oxide layer; 120' -mask layer; 130' -a patterned first photoresist layer;
200' -an isolation trench; 210' -an insulating layer;
300' -a polysilicon layer; 310' -a patterned second photoresist layer; 301 ', 302' -gate;
100-a substrate; 110-an oxide layer;
200-an isolation trench; 210-an insulating layer; 220-a layer of insulating material;
300-a polysilicon layer; 301. 302-a gate;
400-a patterned first photoresist layer; 500-a patterned second photoresist layer.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 1-5 are schematic cross-sectional views corresponding to steps in a method for fabricating a semiconductor structure. Referring to fig. 1, a substrate 1 ' is first provided, the substrate 1 ' having an oxide layer 110 ' formed thereon.
Next, referring to fig. 2, a mask layer 120 'and a first photoresist layer are sequentially formed on the oxide layer 110', and then, the first photoresist layer is exposed and developed to form a patterned first photoresist layer 130 ', in which a plurality of openings are formed to expose the mask layer 120'. Next, the mask layer 120 ', the oxide layer 110' and the substrate 100 'exposed by the opening are etched to form an isolation trench 200'. In this embodiment, the material of the mask layer 120 'includes silicon nitride, and the material of the oxide layer 110' includes silicon oxide.
Referring to fig. 3, the patterned first photoresist layer 130 ' is removed, an insulating material layer is filled in the isolation trench 200 ', and the insulating material layer is planarized to form an insulating layer 210 ', such that an upper surface of the insulating layer 210 ' is flush with an upper surface of the mask layer 120 '. Next, the mask layer 120' is removed.
Referring to fig. 4, a polysilicon layer 300 'and a second photoresist layer are sequentially formed on the oxide layer 110' and the insulating layer 210 ', and then the second photoresist layer is exposed and developed to form a patterned second photoresist layer 310', and a plurality of openings are formed in the patterned second photoresist layer 310 'to expose the polysilicon layer 300'.
Next, referring to fig. 5, the polysilicon layer 300 ' is etched using the patterned second photoresist layer 310 ' as a mask layer to form gates 301 ', 302 ', and then the patterned second photoresist layer 310 ' is removed.
In the above method for manufacturing a semiconductor device, the sharp corner portion (i.e., the region indicated by a in fig. 3) of the insulating layer 210' may be damaged during the subsequent gate structure process, thereby causing mismatch of the semiconductor device. Meanwhile, the manufacturing process (especially, the related processes of photolithography and etching) of the isolation trench and gate structure process may cause device-to-device variation.
In order to avoid the above situation, the present embodiment adjusts the process flow of the method for manufacturing the semiconductor structure, and fig. 6 is a flowchart of the method for manufacturing the semiconductor structure provided in the present embodiment. Referring to fig. 6, the method for manufacturing a semiconductor structure according to the present embodiment includes:
step S01: providing a substrate, and preparing a polycrystalline silicon layer on the substrate;
step S02: etching the polysilicon layer and the substrate to form an isolation trench;
step S03: forming an insulating layer in the isolation groove, wherein the upper surface of the insulating layer is lower than the upper surface of the polycrystalline silicon layer;
step S04: and etching the polysilicon layer to form a grid electrode.
The method for fabricating the semiconductor structure provided in this embodiment is described in detail below. First, referring to fig. 7, step S01 is performed to provide a substrate 100, and a polysilicon layer 300 is prepared on the substrate 100. Specifically, an oxide layer 110 is further formed between the substrate 100 and the polysilicon layer 300. Optionally, the material of the oxide layer 110 includes silicon oxide.
Next, referring to fig. 8 to 9, step S02 is performed to etch the substrate 100 and the polysilicon layer 300 to form an isolation trench. Specifically, referring to fig. 8, a first photoresist layer is formed on the polysilicon layer 300, and then the first photoresist layer is exposed and developed to form a patterned first photoresist layer 400, wherein a plurality of openings are formed in the patterned first photoresist layer 400 to expose the polysilicon layer 300. Subsequently, referring to fig. 9, the polysilicon layer 300 and the substrate 100 exposed by the opening are etched using the patterned first photoresist layer 400 as a mask layer to form an isolation trench 200. Next, the patterned first photoresist layer 400 is removed. Optionally, a plasma strip process is used to remove the patterned first photoresist layer 400.
Referring to fig. 10-12, step S03 is performed to form an insulating layer 210 in the isolation trench 200, wherein an upper surface of the insulating layer 210 is lower than an upper surface of the polysilicon layer 300. Specifically, referring to fig. 10, firstly, an insulating material layer 220 is filled in the isolation trench 200, and the insulating material layer 220 extends to cover the polysilicon layer 300 on both sides of the isolation trench 200; subsequently, referring to fig. 11, the insulating material layer 220 is planarized such that the upper surface of the insulating material layer 220 is flush with the upper surface of the polysilicon layer 300; next, referring to fig. 12, the insulating material layer 220 is etched to a certain thickness to form an insulating layer 210, such that the upper surface of the insulating layer 210 is lower than the upper surface of the polysilicon layer 300. Meanwhile, the upper surface of the insulating layer 210 is higher than the upper surface of the oxide layer 110. Optionally, the material of the insulating layer includes silicon oxide.
Referring to fig. 13-14, step S04 is performed to etch the polysilicon layer to form a gate. Specifically, referring to fig. 13, first, a second photoresist layer is formed on the polysilicon layer 300 and the insulating layer 210, and then, the second photoresist layer is exposed and developed to form a patterned second photoresist layer 500, wherein a plurality of openings are formed in the patterned second photoresist layer 500 to expose the polysilicon layer 300; subsequently, referring to fig. 14, the opening-exposed polysilicon layer 300 is etched using the patterned second photoresist layer 500 as a mask layer until a portion of the oxide layer 110 is exposed; next, the patterned second photoresist layer 500 is removed. Optionally, a plasma strip process is used to remove the patterned second photoresist layer 500.
When the method for manufacturing the semiconductor structure provided by the embodiment is used for manufacturing the static random access memory, the random variation of the process parameters of the static random access memory caused by the influence of the process flow is reduced, the mismatch is reduced, and the stability, the reliability and the yield of the static random access memory are improved.
In summary, the present invention provides a method for manufacturing a semiconductor structure, including: providing a substrate, and preparing a polycrystalline silicon layer on the substrate; etching the polysilicon layer and the substrate to form an isolation trench; forming an insulating layer in the isolation groove, wherein the upper surface of the insulating layer is lower than the upper surface of the polycrystalline silicon layer; and etching the polysilicon layer to form a grid electrode. The preparation method of the semiconductor structure provided by the invention reduces the damage of the gate structure process to the isolation trench by improving the process flow of semiconductor manufacturing, thereby improving the electric leakage phenomenon. Meanwhile, the difference between devices mainly caused by photoetching and etching in the preparation process of the isolation groove and the gate structure is reduced, so that the mismatch phenomenon of the semiconductor device is improved, and the stability and the reliability of the semiconductor device are improved.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A method for fabricating a semiconductor structure, comprising:
providing a substrate, and preparing a polycrystalline silicon layer on the substrate;
etching the polysilicon layer and the substrate to form an isolation trench;
forming an insulating layer in the isolation groove, wherein the upper surface of the insulating layer is lower than the upper surface of the polycrystalline silicon layer;
and etching the polysilicon layer to form a grid electrode.
2. The method of fabricating a semiconductor structure according to claim 1, wherein an oxide layer is further formed between the polysilicon layer and the substrate.
3. The method of claim 2, wherein an upper surface of the insulating layer is higher than an upper surface of the oxide layer.
4. The method of fabricating a semiconductor structure of claim 2, wherein etching the polysilicon layer and the substrate to form an isolation trench comprises:
forming a patterned first photoresist layer on the polysilicon layer;
etching the polycrystalline silicon layer and the substrate by taking the patterned first photoresist layer as a mask layer to form an isolation groove; and
and removing the patterned first photoresist layer.
5. The method of fabricating a semiconductor structure according to claim 3, wherein the forming of the insulating layer in the isolation trench comprises:
filling an insulating material layer in the isolation trench, wherein the insulating material layer extends to cover the polycrystalline silicon layers on two sides of the isolation trench;
carrying out planarization treatment on the insulating material layer to enable the upper surface of the insulating material layer to be flush with the upper surface of the polycrystalline silicon layer;
and etching the insulating material layer with a certain thickness to form an insulating layer, wherein the upper surface of the insulating layer is lower than the upper surface of the polycrystalline silicon layer.
6. The method of fabricating a semiconductor structure of claim 2, wherein etching the polysilicon layer to form a gate comprises:
forming a second patterned photoresist layer on the polysilicon layer, wherein the second patterned photoresist layer covers the insulating layer;
etching the polycrystalline silicon layer by taking the patterned second photoresist layer as a mask layer until part of the oxide layer is exposed; and
and removing the patterned second photoresist layer.
7. The method of claim 4 or 6, wherein the patterned first photoresist layer and the patterned second photoresist layer are removed using a plasma stripping process.
8. The method of fabricating a semiconductor structure of claim 6, wherein the polysilicon layer is dry etched.
9. The method of claim 2, wherein the oxide layer comprises silicon oxide.
10. The method of claim 1, wherein the insulating layer comprises a material comprising silicon oxide.
CN202010884225.3A 2020-08-28 2020-08-28 Method for manufacturing semiconductor structure Pending CN111883485A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010066608A (en) * 1999-12-31 2001-07-11 황인길 Method for forming gate of transistor
US6281082B1 (en) * 2000-03-13 2001-08-28 Chartered Semiconductor Manufacturing Ltd. Method to form MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill
CN105551994A (en) * 2016-02-17 2016-05-04 上海华力微电子有限公司 Method for verifying tunnelling oxide layer reliability of flash memory
CN106158757A (en) * 2016-07-27 2016-11-23 上海华虹宏力半导体制造有限公司 Flush memory device manufacture method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010066608A (en) * 1999-12-31 2001-07-11 황인길 Method for forming gate of transistor
US6281082B1 (en) * 2000-03-13 2001-08-28 Chartered Semiconductor Manufacturing Ltd. Method to form MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill
CN105551994A (en) * 2016-02-17 2016-05-04 上海华力微电子有限公司 Method for verifying tunnelling oxide layer reliability of flash memory
CN106158757A (en) * 2016-07-27 2016-11-23 上海华虹宏力半导体制造有限公司 Flush memory device manufacture method

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